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    Plasma Etching Processes for Interconnect Realization in VLSI
    Plasma Etching Processes for Interconnect Realization in VLSI
    Plasma Etching Processes for Interconnect Realization in VLSI
    Ebook160 pages1 hour

    Plasma Etching Processes for Interconnect Realization in VLSI

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    This is the first of two books presenting the challenges and future prospects of plasma etching processes for microelectronics, reviewing the past, present and future issues of etching processes in order to improve the understanding of these issues through innovative solutions.This book focuses on back end of line (BEOL) for high performance device realization and presents an overview of all etch challenges for interconnect realization as well as the current etch solutions proposed in the semiconductor industry. The choice of copper/low-k interconnect architecture is one of the keys for integrated circuit performance, process manufacturability and scalability. Today, implementation of porous low-k material is mandatory in order to minimize signal propagation delay in interconnections. In this context, the traditional plasma process issues (plasma-induced damage, dimension and profile control, selectivity) and new emerging challenges (residue formation, dielectric wiggling) are critical points of research in order to control the reliability and reduce defects in interconnects. These issues and potential solutions are illustrated by the authors through different process architectures available in the semiconductor industry (metallic or organic hard mask strategies).
    • Presents the difficulties encountered for interconnect realization in very large-scale integrated (VLSI) circuits
    • Focused on plasma-dielectric surface interaction
    • Helps you further reduce the dielectric constant for the future technological nodes
    LanguageEnglish
    PublisherElsevier Science
    Release dateApr 14, 2015
    ISBN9780081005903
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      Book preview

      Plasma Etching Processes for Interconnect Realization in VLSI - Nicolas Posseme

      Plasma Etching Processes for Interconnect Realization in VLSI

      Nicolas Posseme

      Table of Contents

      Cover image

      Title page

      Copyright page

      List of Acronyms

      Preface

      1: Introduction

      Abstract

      1.1 Integration processes related to copper introduction

      1.2 Dielectric material with low-k value (<4)

      2: Interaction Plasma/Dielectric

      Abstract

      2.1 Porous SiOCH film etching

      2.2 Porous SiOCH film sensitivity to post-etch treatments

      3: Porous SiOCH Film Integration

      Abstract

      3.1 Trench first metallic hard mask integration

      3.2 Porous SiOCH integration using the via first approach

      3.3 Summary

      4: Interconnects for Tomorrow

      Abstract

      4.1 Consequence of porosity increase

      4.2 Process solutions for dielectric constant reduction

      4.3 Material solutions for dielectric constant reduction

      4.4 Alternative interconnect architectures for dielectric constant reduction

      4.5 Conclusion

      Bibliography

      List of Authors

      Index

      Copyright

      First published 2015 in Great Britain and the United States by ISTE Press Ltd and Elsevier Ltd

      Apart from any fair dealing for the purposes of research or private study, or criticism or review, as permitted under the Copyright, Designs and Patents Act 1988, this publication may only be reproduced, stored or transmitted, in any form or by any means, with the prior permission in writing of the publishers, or in the case of reprographic reproduction in accordance with the terms and licenses issued by the CLA. Enquiries concerning reproduction outside these terms should be sent to the publishers at the undermentioned address:

      ISTE Press Ltd

      27-37 St George’s Road

      London SW19 4EU

      UK

      www.iste.co.uk

      Elsevier Ltd

      The Boulevard, Langford Lane

      Kidlington, Oxford, OX5 1GB

      UK

      www.elsevier.com

      Notices

      Knowledge and best practice in this field are constantly changing. As new research and experience broaden our understanding, changes in research methods, professional practices, or medical treatment may become necessary.

      Practitioners and researchers must always rely on their own experience and knowledge in evaluating and using any information, methods, compounds, or experiments described herein. In using such information or methods they should be mindful of their own safety and the safety of others, including parties for whom they have a professional responsibility.

      To the fullest extent of the law, neither the Publisher nor the authors, contributors, or editors, assume any liability for any injury and/or damage to persons or property as a matter of products liability, negligence or otherwise, or from any use or operation of any methods, products, instructions, or ideas contained in the material herein.

      For information on all Elsevier publications visit our website at http://store.elsevier.com/

      © ISTE Press Ltd 2015

      The rights of Nicolas Posseme to be identified as the author of this work have been asserted by him in accordance with the Copyright, Designs and Patents Act 1988.

      British Library Cataloguing in Publication Data

      A CIP record for this book is available from the British Library

      Library of Congress Cataloging in Publication Data

      A catalog record for this book is available from the Library of Congress

      ISBN 978-1-78548-015-7

      Printed and bound in the UK and US

      List of Acronyms

      ARC   Anti-reflective coating

      ATRP   Terpinene

      BARC   Bottom anti-reflective coating

      BEOL   Back-end-of-line

      CCP   Capacitively coupled plasma

      CD   Critical dimension

      CMOS   Complementary metal oxide semiconductor

      CMP   Chemical–mechanical planarization

      CVD   Chemical vapor deposition

      DEMS   Diethoxymethylsilane

      DFCCP   Dual frequency capacitively coupled plasma

      DMDCS   Dichlorodimethylsilane

      DS   Downstream

      EM   Electromigration

      ER   Etch rate

      ESL   Etch stop layer

      FC   Fluorocarbon

      FDSOI   Fully depleted silicon on insulator

      FEOL   Front-end-of-line

      FSG   Fluorine-doped silicon glass

      FTIR   Fourier transform infrared spectroscopy

      HDMS   Hexamethyldisilazane

      HF   Hydrofluoric acid

      HSQ   Hydrogen silesquioxane

      IC   Integrated circuit

      ICP   Inductively coupled plasma

      ITRS   International Technology Roadmap for Semiconductor

      MEOL   Middle-end-of-line

      MER   Mass etch rate

      MERIE   Magnetically enhanced reactive ion etcher

      MHM   Metal hard mask

      MOSFET   Metal oxide semiconductor field effect transistor

      MSQ   Methyl silsesquioxane

      MTBC   Mean time between clean

      OTMSA   Trimethylsilylacetate

      P4   Post-porosity plasma protection

      PECVD   Plasma enhanced chemical vapor deposition

      PL   Planarizing layer

      PPLK   Photopatternable low-k

      PR   Photoresist

      RC   Resistive-capacitive

      RF   Radio frequency

      RIE   Reactive ion etching

      RMS   Root mean square

      SEM   Scanning electron microscopy

      SOI   Silicon on insulator

      TCP   Transformer coupled plasma

      TDDB   Time-dependent dielectric breakdown

      TEOS   Tetra ethyl ortho silicate

      TFMHM   Trench first metallic hard mask

      TMCS   Trimethylchlorosilane

      TMDS   Tetramethyldisilazane

      TMSDEA   Trimethylsilydiethylamine

      ULK   Ultra low-k

      UV   Ultra violet

      VLSI   Very large scale integrated

      VUV   Vacuum Ultraviolet

      XPS   X-ray photoelectron spectroscopy

      Preface

      Electronics and information systems play an ever-increasing role in the worldwide economy. With a global income of $265 billion in 2008, the semiconductor industry contributed to more than $1,300 billion in the electronics industry and $5,000 billion in services, which represented nearly 10% of the gross domestic product. Electronics and information systems have penetrated and transformed all aspects of life, including transportation, communications, health and well being, government services, banking systems, entertainment and education.

      Micro- and nanoelectronics are the key enabling technologies for electronics, information and communications technology, and as a result, the semiconductor market is increasing at double the rate of gross domestic product growth. The specific position of the microelectronics industry has been made possible by the constant downscaling of device dimensions, which increases the performance to fulfill the current societal needs in consumer electronics that can now be divided into two main paths: performance improvement and energy efficiency. For this, during the last 50 years, integrated circuits have evolved from a 100-transistors chip in 1966 to multibillion- transistors circuits in 2010, with the smallest device measuring less than 20 nm.

      However, the problem with the constant downscaling in dimension is that the resistive–capacitive (RC) delay coming from interconnects has become the main issue for devices with high performance. That is xiv Plasma Etching Processes for Interconnect Realization in VLSI why copper-based interconnects have been introduced at the end of the 1990s to reduce the resistivity of wires, and low dielectric constant materials (low-k dielectrics) were introduced to deal with interconnects capacitance and signal propagation delay. But these changes have not been done without some difficulty.

      Indeed, for the last 10 years, low-k dielectrics (i.e. materials with a lower dielectric constant than silicon dioxide) have evolved from fluorine-doped silicon glass (FSG; k = 3.2), to organosilicate (SiOCH; k = 3.0 and 2.7) and porous SiOCH (k = 2.55 and 2.4). Further decreasing the dielectric constant requires us to increase the porosity. Unfortunately, the presence of interconnected pores has amplified the dielectric sensitivity to plasma-based processes that are required for interconnects fabrication. It is thus impossible to define patterns in porous low-k materials without damaging their electrical properties with current etching technologies. Moreover, the mechanical strength of the dielectric, already significantly degraded by a decrease in network connectivity in SiOCH, is now reduced even further when porosity is added. For these reasons, technological roadmaps have constantly been revised and chip manufacturers are currently planning to step back to more robust dense materials with larger dielectric constant, thus degrading the

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