library IEEE; use IEEE.STD_LOGIC_1164.

ALL;

entity universalshiftregister is

port (A1 : in std_logic; A2 : IN STD_LOGIC_VECTOR(3 DOWNTO 0); CLK1: IN STD_LOGIC; RESET:IN STD_LOGIC; SEL : IN STD_LOGIC_VECTOR(1 DOWNTO 0); OUTPUT1 : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); OUTPUT2 : OUT STD_LOGIC);

end universalshiftregister;

architecture Behavioral of universalshiftregister is

TYPE STATES IS (SISO,SIPO,PISO,PIPO);

signal next_state : states;

SIGNAL INTER:STD_LOGIC_VECTOR(3 DOWNTO 0):="0000"; signal count : integer range 0 to 25000000; signal clock : std_logic:='0'; begin

process(clk1) begin if(clk1'event and clk1='1') then count <=count+1; if(count = 25) then clock <= not clock; count <=1; end if; end if; end process;

PROCESS(SEL)

BEGIN

CASE SEL IS

WHEN "00" =>

NEXT_STATE <= SISO;

WHEN "01" =>

NEXT_STATE <= SIPO;

WHEN "10" =>

NEXT_STATE <= PISO;

WHEN OTHERS =>

NEXT_STATE <= PIPO;

END CASE;

end process;

process (clock,RESET,NEXT_STATE)

begin if (clock'event and clock ='1') then IF (RESET='1') THEN INTER <= "0000"; ELSE

CASE NEXT_STATE IS

WHEN SISO =>

INTER <= A1 & INTER(3 downto 1); OUTPUT2 <= INTER(0);

WHEN SIPO => INTER <= A1 & INTER (3 downto 1);

OUTPUT1 <= INTER;

WHEN PISO =>

INTER <= A2 ; INTER<=INTER(0) & INTER(3 downto 1); OUTPUT2 <= INTER(0);

WHEN PIPO => INTER <= A2;

OUTPUT1 <= INTER;

END CASE;

END IF; end if; END PROCESS;

end Behavioral;