Experiment No.

Date: 4th Sept. 2012

Reg. No. 12MVD0023

Exp.No.2

Design and Implementation of Sequential Circuits

Aim: To design and implement the following combinational circuit. a. Flip-Flop using behavioral modeling b. Serial-In Serial Out, Parallel-In Parallel Out Shift register using Structural Modeling c. Serial-In Parallel Out, Parallel-In Serial Out Shift register using behavior level Modeling d. Ring Counter and Johnson counter using behavior level Modeling and structural level modeling. Software Details: For design Functional Simulation: ModelSim For design Synthesis: Quartus II For design Implementation: Quartus II Hardware Details: Family: Cyclone II Device: EP2C Package: FBGA Pincount: 484

Experiment No. 2

Date: 4th Sept. 2012

Reg. No. 12MVD0023

/*program for d, s-r, j-k, t-ff */

module ff_seq (d, reset_n, s, r, j, k, t, clk, q_d, q_s, q_r, q_j, q_k, q_t);

//module name. //input output declaration

input d; input s; input r; input j; input k; input clk; input reset_n; input t;

//input port declaration .

Experiment No. 2

Date: 4th Sept. 2012

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output q_d; output q_s; output q_r; output q_j; output q_k; output q_t;

//output port declaration.

reg q_d; reg q_s; reg q_r; reg q_j; reg q_k; reg q_t; initial q_t=1'b0;

//output as register.

always@(posedge clk or negedge reset_n) begin

//edge declaration. //program for d-ff.

if (reset_n==0) begin

Experiment No. 2 q_d<=0; end else begin q_d<=d; end

Date: 4th Sept. 2012

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if (reset_n==0) begin q_s<=0; q_r<=1; end else case({s,r}) 2'b00: begin q_s<=q_s; q_r<=q_r; end 2'b01: begin q_s<=0; q_r<=1; end

//program for s-r flip flop.

//s=0,r=0 then memory state.

//if s=0,r=1 then q_s=0,q_r=1.

Experiment No. 2 2'b10: begin q_s<=1; q_r<=0; end default : begin q_s<=0; q_r<=0; end endcase

Date: 4th Sept. 2012 //if s=1,r=0 then q_s=1,q_r=0.

Reg. No. 12MVD0023

//any other condition q_s=0,q_r=0.

if(reset_n==0)

//program for j-k flip flop. //if reset is applied.

begin q_j<=0; q_k<=0; end else case({j,k}) 2'b00: begin q_j<=q_j; //when j=0,k=0 then memory state.

Experiment No. 2 q_k<=q_k; end

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2'b01: begin q_j<=0; q_k<=1; end

//when j=0,k=1 q_j=0,q_k=1.

2'b10: begin q_j<=1; q_k<=0; end

//when j=1,k=0 then q_j=1,q_k=0.

2'b11: begin q_j<=!q_j; q_k<=!q_k; end

//when j=1,k=1 then toggle.

default: begin q_j<=0; q_k<=0;

//defaut case .

Experiment No. 2 end endcase

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if(reset_n==1&& t==1)

//program for t flip flop.

q_t<=~q_t;

//toggle.

else q_t<=q_t; end endmodule

input d,clk,reset_n; output q,q_n; reg q,q_n;

//input port declaration . //output port declaration.

always@(posedge clk,negedge reset_n) begin if (reset_n==0)

Experiment No. 2 begin q<=0; q_n<=1; end else begin q<=d; q_n<=!d; end end endmodule

Date: 4th Sept. 2012 //if reset is active.

Reg. No. 12MVD0023

//if reset is not applied.

Experiment No. 2

Date: 4th Sept. 2012

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TEST BENCH
`include "ff_seq.v" `timescale 1ns/100ps //including design fie. //for time axis and resolution.

module ff_seq_tb;

reg s; reg r; reg d; reg clk; reg reset_n; reg j; reg k; reg t;

//declaration of test module.

wire q_d; wire q_s; wire q_r; wire q_j; wire q_k; wire q_t;

//declaration of output.

Experiment No. 2

Date: 4th Sept. 2012

Reg. No. 12MVD0023

ff_seq a1 (d, reset_n, s, r, j, k, t, clk, q_d, q_s, q_r, q_j, q_k, q_t);

// calling design module.

//list of all the input,output pins.

always #10 clk=~clk; //clock of 50 mhz//

initial begin clk=1'b0; reset_n=1'b0; d=1'b0; //initial input at t=0ns//

Experiment No. 2 s=1'b1; r=1'b0; j=1'b1; k=1'b0; t=0;

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#10 reset_n=1'b1; d=1'b1; s=1'b1; r=1'b0; j=1; k=0; t=1; //input at 10 ns//

#20 reset_n=1'b1; d=1'b0; s=1'b0; r=1'b1; j=0; t=1; k=1;

//input at 30 ns//

Experiment No. 2 #20 reset_n=1'b1; d=1'b1; s=1'b0; r=1'b0; j=1; k=1; t=1; // input at 50 ns//

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#20 reset_n=1'b1; d=1'b0; s=1'b1; r=1'b0; j=0; k=0; t=1;

//input at 70 ns//

#20

//hold value up to 90 ns//

$finish; $stop;

//end simulation. //stop testing.

end endmodule

Experiment No. 2

Date: 4th Sept. 2012

Reg. No. 12MVD0023

RING COUNTER

module cnt_ring (out, user, store, clk, reset_n, load, data_shift);

input reset_n; input clk; input [3:0]user; input load;

output [3:0]out; output [3:0]store; output [3:0]data_shift;

reg [3:0]out; wire [3:0]store; wire [3:0]data_shift;

assign data_shift= {out[0],out[3:1]};

Experiment No. 2 assign store =user;

Date: 4th Sept. 2012

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always@(posedge clk or negedge reset_n) begin if (reset_n==0) out<=store; else if(load==1) out<=user; else out<=data_shift; end endmodule

Experiment No. 2

Date: 4th Sept. 2012

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TEST BENCH

`include "cnt_ring.v" `timescale 1ns/100ps

module cnt_ring_tb; reg clk; reg reset_n; reg [3:0]user; reg load;

wire [3:0]out; wire [3:0]store; wire [3:0]data_shift;

cnt_ring a1

(out, user, store, clk, reset_n, load, data_shift);

always #10 clk=~clk;

Experiment No. 2 initial begin

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reset_n=0; clk=0; user=4'b1000; load=0; #10 reset_n=1; load=0; #20 reset_n=1; load=0; #20 reset_n=1; load=0; #20 reset_n=1; load=0; #20 user=3'b1010; reset_n=1; load=0; #20 reset_n=1;

Experiment No. 2 load=0; #20 reset_n=1; load=0;

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#20 reset_n=1; load=1; user=3'b0100;

#20 reset_n=1; load=0;

#20 reset_n=1; load=0; #20 reset_n=0; load=0; #20 $stop; $finish; end endmodule

Experiment No. 2

Date: 4th Sept. 2012

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JOHNSON COUNTER

module cnt_jonson (out, user, store, clk, reset_n, load, data_shift);

input reset_n; input clk; input [2:0]user; input load;

output [2:0]out; output [2:0]store; output [2:0]data_shift;

reg [2:0]out; wire [2:0]store; wire [2:0]data_shift;

assign data_shift= {~out[0],out[2:1]}; assign store =user;

Experiment No. 2

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always@(posedge clk or negedge reset_n) begin if (reset_n==0) out<=store; else if(load==1) out<=user; else out<=data_shift; end endmodule

Experiment No. 2

Date: 4th Sept. 2012

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TEST BENCH

`include "cnt_jonson.v" `timescale 1ns/100ps

module cnt_jonson_tb; reg clk; reg reset_n; reg [2:0]user; reg load;

wire [2:0]out; wire [2:0]store; wire [2:0]data_shift;

cnt_jonson a1 (out, user, store, clk, reset_n, load, data_shift);

always

Experiment No. 2 #10 clk=~clk; initial begin

Date: 4th Sept. 2012

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reset_n=0; clk=0; user=3'b000; load=0;

#10 reset_n=1; load=0;

#20 reset_n=1; load=0;

#20 reset_n=1; load=0;

#20 reset_n=1; load=0;

Experiment No. 2 #20 reset_n=1; load=0;

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#20 reset_n=1; load=0;

#20 reset_n=1; load=0;

#20 reset_n=1; load=0;

#20 reset_n=1; load=1; user=3'b111;

#20 reset_n=1; load=0;

Experiment No. 2 #20 reset_n=1; load=0;

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#20 reset_n=0; load=0;

#20

$stop; $finish; end endmodule

Experiment No. 2

Date: 4th Sept. 2012

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Functional Simulation of Johnson Counter:

Experiment No. 2

Date: 4th Sept. 2012

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C. Serial-In Parallel Out, Parallel-In Serial Out Shift register using behavioral Modeling

Serial-In Parallel-Out Shift Register:

RTL Code for Serial-In Parallel Out Shift register using Behavioral Modeling

module reg_sipo (data_in, load, shift, rl, reset_n, clk, data_out, data );

input data_in; input load; input shift; input rl; input reset_n; input clk;

output [7:0]data_out; output [7:0]data;

Experiment No. 2

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reg [7:0]data_out; wire [7:0]data;

assign data=rl?data_out>>1:data_out<<1; always@(posedge clk or negedge reset_n) begin if(reset_n==0) begin data_out<=8'b0; end

else if (load==1) begin data_out<={7'b0,data_in}; end

else if(shift==1) begin data_out<={data[7:1],data_in}; end else data_out<=data_out; end endmodule

Experiment No. 2

Date: 4th Sept. 2012

Reg. No. 12MVD0023

TESTBENCH:
`include "reg_sipo.v" `timescale 1ns/100ps module reg_sipo_tb;

reg data_in; reg load; reg shift; reg rl; reg reset_n; reg clk;

wire [7:0]data_out; wire [7:0]data;

reg_sipo a1

(data_in, load, shift, rl, reset_n, clk, data_out, data );

Experiment No. 2

Date: 4th Sept. 2012

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always #10 clk=~clk; initial begin reset_n=0; clk=0; load=0; data_in=0; rl=1; shift=0;

#10 reset_n=1; rl=0; load=1; data_in=1; shift=0;

#20 reset_n=1; rl=0; load=0; shift=1; data_in=1;

Experiment No. 2 #60 reset_n=1; rl=0; load=0; shift=1; data_in=0;

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#60 reset_n=1; rl=0; load=0; shift=1; data_in=1; #40

$stop; $finish;

end endmodule

Experiment No. 2

Date: 4th Sept. 2012

Reg. No. 12MVD0023

Functional Simulation of SIPO Shift Register:

Experiment No. 2

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Experiment No. 2

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Functional Simulation of Ring Counter:

Experiment No. 2

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Functional Simulation of flip - flop

Experiment No. 2

Date: 4th Sept. 2012

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ii) Parallel-in Serial-Out Shift Register:

RTL Code for Parallel-In Serial Out Shift (PISO) register using Behavioral Modeling:

module reg_piso (data_in, load, shift, rl, reset_n, clk, data_out, data_valid, data, eoc, cnt);

input [7:0]data_in; input load; input shift; input rl; input reset_n; input clk;

output data_out;

Experiment No. 2 output data_valid; output eoc; output [7:0]data; output [3:0]cnt;

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reg data_out; reg data_valid; reg eoc; reg [7:0]data; reg [3:0]cnt;

always@(posedge clk or negedge reset_n) begin

if(reset_n==0) begin data_out<=0; data_valid<=0; eoc=0; end

else if (load==1) begin data<=data_in; data_out<=0;

Experiment No. 2 data_valid<=0; eoc<=0; cnt<=4'b1000; end

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else if(shift==1&&cnt!=0) begin data<=rl?data>>1:data<<1; data_out<=rl?data[0]:data[7]; data_valid<=1; eoc<=0; cnt<=cnt-1'b1; end

else if(shift==1&&cnt==0) begin data_out<=0; data_valid<=0; eoc<=1; end

else ; end endmodule

Experiment No. 2

Date: 4th Sept. 2012

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TestBench:

`include "reg_piso.v" `timescale 1ns/100ps module reg_piso_tb;

reg [7:0]data_in; reg load; reg shift; reg rl; reg reset_n; reg clk;

wire data_out; wire data_valid; wire eoc; wire [7:0]data; wire [3:0]cnt;

reg_piso a1

(data_in,

load, shift, rl,

Experiment No. 2 reset_n, clk, data_out, data_valid, data, eoc, cnt);

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always #10 clk=!clk;

initial begin

data_in =0; load=0; shift=0; rl=0; reset_n=0; clk=0;

#10 data_in =8'hfa; load=1; shift=0;

Experiment No. 2 rl=1; reset_n=1;

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#20 load=0; shift=1; rl=1; reset_n=1;

#180

$finish; $stop; end endmodule

Experiment No. 2

Date: 4th Sept. 2012

Reg. No. 12MVD0023

Functional Simulation of PISO Shift Register: