Mukarram Ali

Fa09-BEE-151
4 Bit Carry Look Ahead Adder
I made first all required modules and then called them in
full adder modules. To check its working, made its test
bench too.

Modules

Module for c1
module c_1(c1,p0,g0,c0);
input p0,g0,c0;
output c1;
wire w1;
and(w1,p0,c0);
or(c1,w,g0);
endmodule

Module for c2
module c_2(c2,p0,p1,g0,g1,c0);
input p0,p1,g0,g1,c0;
output c2;
wire w1,w2;
and(w1,p1,g0);
and(w2,p0,p1,c0);
or(c2,w1,w2,g1);
endmodule

Module for c3
module c_3(c3,p0,p1,p2,g0,g1,g2,c0);
input p0,p1,p2,g0,g1,g2,c0;
output c3;
wire w1,w2,w3;
and(w1,p0,p1,p2,c0);
and(w2,p1,p2,g0);
and(w3,p2,g1);
or(c3,w1,w2,w3,g2);
endmodule

Module for P0
module P_0(P0,p0,p1,p2,p3);
input p0,p1,p2,p3;
output P0;
and(P0,p0,p1,p2,p3);
endmodule

Module for G0
module G_0(G0,p1,p2,p3,g0,g1,g2,g3);
input p1,p2,p3,g0,g1,g2,g3;
output G0;
wire w1,w2,w3;
and(w1,g2,p3);
and(w2,g1,p2,p3);
and(w3,go,p1,p2,p3);
or(G0,w1,w2,w3,g3);
endmodule

Module for Sum

module sum(s,p,g,a,b,cin);
input a,b,cin;
output s,p,g;
xor(p,a,b);
and(g,a,b);
xor(s,p,cin);
endmodule

4bit Full Adder module

module fa_4bit(s,cout,a,b,cin);
input [3:0]a,b;
input cin;
output [3:0]s;
output cout;
wire [3:0]p,g;
wire P,G,c1,c2,c3;
sum s0(s[0],p[0],g[0],a[0],b[0],cin);
c_1 c0(c1,p[0],g[0],cin);

sum s1(s[1],p[1],g[1],a[1],b[1],c1);
c_2 C0(c2,p[0],p[1],g[0],g[1],cin);
sum s2(s[2],p[2],g[2],a[2],b[2],c2);
c_3 C1(c3,p[0],p[1],p[2],g[0],g[1],g[2],cin);
sum s3(s[3],p[3],g[3],a[3],b[3],c3);
P_0 Cap_P(P,p[0],p[1],p[2],p[3]);
G_0 Cap_G(G,p[1],p[2],p[3],g[0],g[1],g[2],g[3]);
c_1 c4(cout,P,G,cin);
endmodule

Test bench
module tbfa;
reg [3:0]a,b;
reg cin;
wire[3:0] sum;
wire cout;
fa_4bit f0(sum, cout, a, b, cin);
initial
begin
a=4'b0101; b=4'b1010; cin=1'b1;
# 15a=4'b0101; b=4'b1010; cin=1'b0;
#15 a=4'b0101; b=4'b1110; cin=1'b1;
end
endmodule