ABSTRACT

The Fast Fourier Transform (FFT) has become almost ubiquitous and most important in high speed signal processing. This paper explains the implementation of configurable FFT implementation using split radix algorithm. FFT operations up to 512 points can be performed using this approach. In this paper a FFT is realized and implemented using a soft micro controller. The soft microcontrollers provide an advantage of configurable interface over the hard micro controller. In traditional microcontroller implementing a radix 2 structure will be quite complex, slow and resource consuming. However in hardware the radix 2 structure can be efficiently and effectively implemented. This paper employs hardware software co design approach, where a high performance radix 2 FFT implementation is developed in hardware .The software part of design utilizes this radix hardware to implement a split radix FFT algorithm. Open Source Wishbone Bus is used as an interface between software and hardware block. We implemented Single RAM memory strategy which results in single memory location for both input and outputs of butterfly without any conflicts. The implementation was made on a Complex programmable logic device(CPLD) because it can achieve higher computing speed than digital signal processors, and also can achieve cost effectively ASIC-like performance with lower development time, and risks. In this system, the hardware is modeled by Verilog while the software is written in C.