VLSI TECHNOLOGY TITLE: BATCH : Cy/C4 ROLL NO : 13 REG NO : 1030309058 DATE:

TUTORIAL -9 29-03-2012

Modeling of mod6 Counter

AIM: Modeling of mod6 Counter and Verify on ESDK kit

MOD6 COUNTER:VHDL PROGRAM:

Library IEEE; Use ieee.std_logic_1164.all; Use ieee.std_logic_arith.all; Use ieee.std_logic_unsigned.all; Entity mod6_counter is Port (rst, clk: in bit; count: buffer integer range 0 to 5); End mod6_counter; Architecture test of mod6_counter is Begin Process Begin Wait until clk event and clk = '1'; If (rst = '1' or count >= 5) then Count <=0; Else Count <= count + 1; End if; End process; End test;

ATMIYA INSTITUTE OF TECHNOLOGY & SCIENCE

VLSI TECHNOLOGY

TUTORIAL -9

COMPILATION REPOR:-

VECTOR WAVEFORM :-

Conclusion:-

Grade

Lab-In-Charge

H.O.D.

ATMIYA INSTITUTE OF TECHNOLOGY & SCIENCE