National Institute of Applied Sciences Department of Electrical & Computer Engineering

MicroWind
An Introduction to micro-electronics for Windows 95

Version 1.0

Etienne Sicard

Unpacking YourpackageforMICROWINDcontainsthefollowingitems: u u TheUser'sManual(thepresentbook) Thediskettescontainingthesoftware,runninginWindows95environment

TheUser'smanualcontainsinformationonhowtooperatetheprogramandhowto executethecommands.Italsocontainsexplanationsforasetof30microelectronics projectsandsuggestedactivities. SystemRequirements YourcomputersystemshouldhaveaPCconfigurationincludingthefollowingfeatures: l l l Aminimummemoryof8Mb 640x480,256colors(a800x600resolutionisrecommended) Windows95/NT

HowtoInstalltheSoftware Theinstallationofthesoftwareontheharddiskisrecommended.Toinstalltheprograms ontheharddisk,performthefollowingstepbystepprocedure: SelectStart>ExecutecommandunderWindows95, Insertthedisketteintodrivea: Typea:installandpress Thiscommandcreatesadirectorynamedmicrowindontheharddisk. Consequentlyallthefilesofthediskettewillbecopiedintothis microwinddirectory. AbouttheSingleLicense Thesinglelicenseauthorizesyoutouse onecopyofthesoftwareandincludesonecopy ofthedocumentation.Youmayusethecopyofthesoftwareandthedocumentationonno morethanonepersonalcomputeratatime.Youareallowedtomakeonearchivalcopyof thesoftwareforyourpersonaluse.Youmaynottransfer,sell,ordistributethesoftware. Youcannotgivecopiesofthesoftwareorofthedocumentationtoanyone. ISBN287649017X 2

EditedbyINSAToulouse,AvdeRangueil31077ToulouseCedex4FRANCE

AbouttheSiteLicense Thesitelicenseauthorizesyoutouse tencopiesofthesoftwareandincludesonecopyof thedocumentation.Foreachcomputerwhenoperatingtheprogramsimultaneouslyone morethanonecomputeranauthorizedcopyoftheprogramisrequiredforeachofthem Youcanmakearchivalcopiesofthesoftware.Youmaynottransfer,sell,ordistributethe software.Youcannotgivecopiesofthesoftwareorthedocumentationtoanyperson.

Abouttheauthor ETIENNESICARDwasborninParis,France,inJune1961.HereceivedaB.Sdegreein 1984andaPhDinElectricalEngineeringin1987bothfromtheUniversityofToulouse.He wasgrantedaMonbushoscholarshipandstayed18monthsattheUniversityofOsaka, Japan.Previouslyaprofessorofelectronicsinthedepartmentofphysics,attheUniversity of Balearic Islands, Spain, E. Sicard is currently an associate professor at the INSA ElectronicEngineeringSchoolofToulouse.Hisresearchinterestsincludeseveralaspects of CAD tools for the design of integrated circuits including crosstalk fault analysis, electromagneticcompatibility,thedesignofmicrosystemsandofeducationalsoftware. Copyright1998 EtienneSicard INSADGEIAvdeRangueil 31077TOULOUSECedex4,FRANCE Tel:+33.561.55.98.42 Fax:+33.561.55.98.00 email: etienne@dge.insatlse.fr webinformation: http://www.insatlse.fr/~etienne
o o Windows95isatrademarkofMICROSOFTCORPORATION. IBMPCisatrademarkofINTERNATIONALBUSINESSMACHINECORP.

MICROWIND1.05

Contents

SoftwareInstallation Introduction License 1. TutorialonMOSdevices TheMosModel1 TheMOSModel3 TutorialonLevel3Parameters 2. DesignofaCMOSInverter Simulation ParametricAnalysis 3. BasicGates CompilingtheNANDGate 3InputOR TheXORgate ComplexGates 4. ArithmeticGates HalfAdder FullAdder Comparator 5. Latches&Memories RSLatch DLatch RAMMemory RAM4x4bit

Page 2 6 7 8 15 16 18 22 27 31 34 35 37 39 41 43 43 46 48 50 50 52 54 56

MICROWIND1.06

Contents(ctd)
6. OtherProjects 4BitAdder Multiplier2x2bits TwoBitCounter WideRangeAmplifier InterfacewithPSPICE Analog/DigitalConverter Digital/Analogconverter Input/OutputPad, PadRing DesignRules ProgramOperation ListofCommands QuickReferenceSheet Instructor'sGuide References 62 62 64 66 68 70 71 74 76 78 82 92 93 116 121 123

7. 8. 9. 10. 11. 12.

MICROWIND1.07

Introduction

ThepresentbookisaguidetousingtheMicrowindeducationalsoftwareonaPC computer. The MICROWIND program allows the student to design and simulate an integrated circuit.ThepackageitselfcontainsalibraryofcommonlogicandanalogICstoviewand simulate. MICROWIND includes all the commands for a mask editor as well as new originaltoolsnevergatheredbeforeinasinglemodule.Youcangainaccessto Circuit Simulation by pressing one single key. The electric extraction of your circuit is automaticallyperformedandtheanalogsimulatorproducesvoltageandcurrentcurves immediately. AspecificcommanddisplaysthecharacteristicsofpMOSandnMOS,wherethesizeofthe deviceandtheprocessparameterscanbeveryeasilychanged.AlteringtheMOSmodel parameters and,then,seeing theeffectsontheVdsandIdscurvesconstitutesagood interactivetutorialondevices. TheProcessSimulator showsthelayoutinaverticalperspective,aswhenfabricationhas been completed. This feature is a significant aid to supplement the descriptions of fabricationfoundinmosttextbooks. TheLogicCellCompilerisaparticularlysophisticatedtoolenablingtheautomaticdesignof aCMOScircuitcorrespondingtoyourlogicdescriptioninVERILOG.TheDSCHsoftware, whichisauserfriendlyschematiceditorandalogicsimulatorpresentedinacompanion manual,isusedtogeneratethisVerilogdescription.Thecelliscreatedincompliancewith theenvironment,designrulesandfabricationspecifications. A set of CMOS processes ranging from 1.2m down to stateoftheart 0.25m are proposed. 7

MICROWIND1.08

Thechaptersofthismanualhavebeen summarizedbelow.ChaptersOnethroughSix presentatutorialonmicroelectronicsandICdesign.ChapterOneisdedicatedtothe simulationofthesingleMOSdevice,withdetailsonthedevicemodelling.ChapterTwo presents the CMOS Inverter, Chapter Three the basic logic gates, Chapter Four the arithmetic functions. The latches and memories are detailed in Chapter Five. As for Chapter,itdealswithvariousprojectssuchasacounter,amultiplier,aCMOSanalog amplifier, the Analog/Digital and Digital/Analog converter principles and a RAM memory. ThedetailedexplanationofthedesignrulesisinChapterSeven.Theprogramoperation andthedetailsofallcommandsaregiveninChapterEightandNine.AQuickreference sheet,thecompletelistoffilesandtheinstructorguidearereportedattheendofthe presentmanual. ThemajorupdatesofMICROWINDcomparedtotheDOSversionconcernthesupportof advanced technologies, improvements in editing commands, the possibility to handle very complex designs and the VERILOG compilation from highlevel description into layout.Thenewsoftware,DSCH,concerninglogiceditingandsimulationisnowpartof thepackage.

License
PleasenotethatMICROWINDisalicensedsoftware,thathasbeenlicensedinFranceby LangageetInformatiqueInc,Toulouse,andbyINSAinallothercountries. Thesinglelicenseauthorizesyoutouse onecopyofthesoftwareandincludesonecopy ofthedocumentation.Thesitelicenseauthorizesyoutouse tencopiesofthesoftware and includes one copy of the documentation. An authorized copy of the program is requiredforeachoneofthecomputeroperatingtheprogramsimultaneously.Youmay nottransfer,sell,ordistributethesoftware. MICROWIND is recommended by EUROPRACTICE, the American Society for Engineering Education (ASEE), and supported by the National Comity for Micro ElectronicsEducation(CNFM).

MICROWIND1.09

1.TutorialonMOSDevices

TousetheMICROWINDprogramusethefollowingprocedure: Gotothedirectoryinwhichthesoftwarehasbeencopied (ThedefaultdirectoryisMICROWIND) DoubleclickontheMicroWindicon

TheMICROWINDdisplaywindowisshowninFigure1.Itincludesfourmainwindows: themainmenu,thelayoutdisplaywindow,theiconmenuandthelayerpalette.The cursorappearsinthemiddleofthelayoutwindowandiscontrolledbyusingthemouse. Thelayoutwindowfeaturesagridthatrepresentsthecurrentscaleofthedrawing,scaled inlambda()unitsandinmicron. Thelambdaunitisfixedtohalfoftheminimumavailablelithographyofthetechnology. Thedefaulttechnologyisa0.8mtechnology,consequentlylambdais0.4m.

MICROWIND1.010

Fig. 1. The MICROWIND window as it appears at the initialization stage..

The MOS device

TheMOSsymbolsarereportedbelow.ThenchannelMOSisbuiltusingpolysiliconasthe gatematerialandN+diffusiontobuildthesourceanddrain.ThepchannelMOSisbuilt usingpolysiliconasthegatematerialandP+diffusiontobuildthesourceanddrain.

nMOS

pMOS

Manual Design
Byusingthefollowingprocedure,youcancreateamanualdesignofthenchannelMOS. Thedefaulticonisthedrawingiconshownabove.Itpermitsboxediting.Thedisplay windowisempty.Thepaletteislocatedinthelowerrightcornerofthescreen.Aredcolor indicatesthecurrentlayer.Initiallytheselectedlayerinthepaletteispolysilicon.Thetwo firststepsareillustratedinFigure2. 10

MICROWIND1.011

Fixthefirstcorneroftheboxwiththemouse. Whilekeepingthemousebuttonpressed,movethemousetothe oppositecornerofthebox.

Releasethebutton.ThiscreatesaboxinpolysiliconlayerasshowninFigure2. Theboxwidthshouldnotbeinferiorto2,whichistheminimumwidthofthe polysiliconbox.

Fig. 2. Creating a polysilicon box.

ChangethecurrentlayerintoN+diffusionbyaclickonthepaletteoftheDiffusionN+ button.MakesurethattheredlayerisnowtheN+Diffusion.Drawandiffusionboxat thebottomofthedrawingasinFigure3.Ndiffusionboxesarerepresentedingreen.The intersectionbetweendiffusionandpolysiliconcreatesthechannelofthenMOSdevice.

Fig. 3. Creating the N-channel MOS transistor

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MICROWIND1.012

Process Simulation

Clickonthisicontoaccess processsimulation.Thecrosssectionisgivenbyaclickofthe mouseatthefirstpointandthereleaseofthemouseatthesecondpoint.Intheexample below(Figure4),threenodesappearinthecrosssectionofthenchannelMOSdevice:the gate (red), the left diffusion called source (green) and the right diffusion called drain (green),overasubstrate(gray).Thegateisisolatedbyathinoxidecalledthegateoxide. Variousstepsofoxidationhaveleadtoathickoxideonthetopofthegate.

Fig. 4. The cross-section of the nMOS devices.

Thephysicalpropertiesofthesourceandofthedrainareexactlythesame.Theoretically, thesourceistheoriginofchannelimpurities.InthecaseofthisnMOSdevice,thechannel impuritiesaretheelectrons.Therefore,thesourceisthediffusionareawiththelowest voltage. Thepolysilicongatefloatsoverthechannel,andsplitsthediffusioninto 2zones,the sourceandthedrain.Thegatecontrolsthecurrentflowfromthedraintothesource,both ways.Ahighvoltageonthegateattractselectronsbelowthegate,createsanelectron channelandenablescurrenttoflow.Alowvoltagedisablesthechannel.

Mos Characteristics

ClickontheMOScharacteristicsicon.ThescreenshowninFigure5appears.Itrepresents theId/VdsimulationofthenMOSdevice.

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MICROWIND1.013

Fig. 5. N-Channel MOS characteristics.

The MOS size (width and length of the channel situated at the intersection of the polysilicongateandthediffusion)hasastronginfluenceonthevalueofthecurrent.In Figure5,theMOSwidthis12.8mandthelengthis1.2m.ClickonOKtoreturntothe editor.Ahighgatevoltage(Vg=5.0)correspondstothehighestId/Vdcurve.ForVg=0, nocurrentflows.ThemaximumcurrentisobtainedforVg=5.0V,Vd=5.0V,withVs=0.0. The MOS parameters correspond to SPICE Level 3. You can alter the value of the parameters,orevenaccesstoLevel1.YoumayalsoskiptoPMOS.Youmayaswelladd somemeasurementstofitthesimulation.Finally,youcansimulatedeviceswithother sizesintheproposedlist.

Add Properties for Simulation

PropertiesmustbeaddedtothelayouttoactivatetheMOSdevice.Themostconvenient waytooperate theMOSistoapplyaclocktothegate,anothertothesourceandto observethedrain.Thesummaryofavailablepropertiesisreportedbelow.

VDD property VSS property Clock property Node visible Pulse property

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MICROWIND1.014

Applyaclocktothedrain.ClickontheClockicon,clickontheleftdiffusion.The Clockmenuappears(Seebelow).ChangethenameintodrainandclickonOK. Adefaultclockwith3nsperiodisgenerated.TheClockpropertyissenttothe nodeandappearsattherighthandsideofthedesiredlocationwiththename drain.

Fig. 6. The clock menu.

Applyaclocktothegate.ClickontheClockiconandthen,clickon thepolysilicongate.Theclockmenuappearsagain. ChangethenameintogateandclickonOKtoapplyaclockwith6nsperiod. Watchtheoutput:ClickontheVisibleiconandthen,clickontherightdiffusion. Thewindowbelowappears.ClickOK.TheVisiblepropertyisthensent tothenode.Theassociatedtexts1isinitalic.Thewaveformofthisnode willappearatthenextsimulation.

Fig. 7. The visible node menu.

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MICROWIND1.015

Save before Simulation

Clickon File inthemainmenu.Movethecursorto Saveas... andclickonit.Anew windowappears,intowhichyouenterthedesignname.Type,forexample, myMos.Use thekeyboardforthisandpress .ThenclickonOK.Afteraconfirmationquestion,the designissavedunderthatfilename.

IMPORTANT:AlwayssaveBEFOREanysimulation!

Analog Simulation
Clickon Simulate onthemainmenu.Thetimingdiagramsoftheinverter appear,as showninFigure8.

Fig. 8. Analog simulation of the MOS device.

Whenthegateisatzero,nochannelexistssothenodes1isdisconnectedfromthedrain. Whenthegateison,thesourcecopiesthedrain.ItcanbeobservedthatthenMOSdevice driveswellatzerobutatthehighvoltage.Thefinalvalueis4.2V,thatisVDDminusthe thresholdvoltage.ClickonMoreinordertoperformmoresimulations.Clickon Stopto returntotheeditor. 15

MICROWIND1.016

The MOS Model 1

FortheevaluationofthecurrentIdsbetweenthedrainandthesourceasafunctionof Vd,VgandVs,youmayusetheoldbutneverthelesssimpleMODEL1describedbelow. Themodel1isaccurateforchannellengthofmorethan10m. CUTOFFMODE.Vgs<0 Ids=0

LINEAR MODE. Vds<Vgs-Vt, Ids = KP ((Vgs-Vt)Vds- )) SATURATED MODE. Vds>Vgs-Vt, Ids = KP/2 (Vgs-Vt)2

Inthoseformulas,WistheMOSchannelwidth,ListheMOSchannellength.VTOisthe thresholdvoltage.TheparameterKPisevaluatedbythefollowingformula: nisthe mobilityofelectrons,pthemobilityofholes,andTOXthegateoxidethickness. KP(n)=n0S/TOX KP(p)=p0S/TOX where(0.8mtechnology) n=510V.cm2 r(SiO2)=3.9 TOX=150nm p=270V.cm2 0=8.85e14Farad/cm

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MICROWIND1.017

When dealing with submicron technology, the model 1 is 200300% higher than the measurements,asshownaboveforthepredictionofa20x0.8 mnchannelMOSwithKP computedaccordingto0.8moxidethickness.

The MOS Model 3

Fortheevaluationofthecurrent Ids asafunctionofVd,VgandVsbetweenDrainand Source, we commonly use the following equations, close from the SPICE model 3 formulations.Theformulationsarederivedfromthemodel1andtakeintoaccountaset ofphysicallimitationsinasemiempiricalway. CUTOFFMODE.Vgs<0 Ids=0 NORMALMODE.Vgs>Von Ids=Keff with von=1.2vth vth=VTO+GAMMA( PHI vb PHI ) vde=min(vds,vdsat) vdsat=vc+vsat vc 2 + vsat 2 vsat=vgsvth LEFF vc=VMAX 0.06 LEFF=L2LD 17 W Vde (1+KAPPAvds)Vde((Vgsvth) )) LEFF 2

MICROWIND1.018

Keff=

KP (1+ THETA(vgs - vth))

SUBTHRESHOLDMODE.Vgs<Von vdsisreplacedbyvonintheaboveequations. Ids=Ids(von,vds)e q(vgs - von) nkT

Inthoseformulas,WcorrespondstotheMOSchannelwidth,LtotheMOSchannellength andVTOtothethresholdvoltage.TheKPparameterisevaluatedbythefollowing formulainwhich:nisthemobilityofelectrons,pthemobilityofholes,andTOXthe gateoxidethickness. KP(n)=n0S/TOX KP(p)=p0S/TOX where(0.8technology) n=510V.cm2 r(SiO2)=3.9 TOX=150nm n=2 k=1.381e23 T=300K q=1.6e19 Temperatureeffects: n=n0(T300)e(1.5) p=p0(T300)e(1.5) vt=vt00.002(T300) p=270V.cm2 0=8.85e14Farad/cm

Tutorial on SPICE Level 3 Parameters

ClickontheMOScharacteristicsicon.ThescreendisplaystheId/Vdsimulationofthe nMOSdevice.YoucanchangetheMOSparametervaluesdirectlyonthescreenandsee 18

MICROWIND1.019

theeffectontheMOSsimulation.NoticethatKPincludesthevaluesofTOX(thinoxide thickness)andofU0(thecarriermobility)asdescribedinthepreviouschapter. Fitting the model with measurements ClickonAddMeasurement.Theprogramscansthecurrentdirectoryanddisplaysthelist ofmeasurement files withand appendixcalled " .MES".Choose Es207_n20x20.MES.It correspondstothemeasurementsperformedonarealMOSdevicewithsizeW=20 m, L=20m,fabricatedbyATMELES2intheir0.8 mtechnology(ES208.RUL).Youshould alwaysstartwithmeasurementsforadevicewithaverylargewidthandlength.The second order effects are reduced in such devices. The measured data is added to the drawing,asshownintheFigure9.

Fig.9.Themeasureddatafileisaddedtothesimulation(Es207_20x20.MESfile).

Theprinciplesforfittingthesimulationwiththemeasurementsaredescribedbelow. ClickonIdvs.Vg.ThecurveshowninFigure10isusedtofitVTOandDecrease VTOdownto0.7inordertoshiftthecurvestotheright,andincreaseGAMMA upto0.65toadjustthesetofcurves.Themeasurementstepforvbulkis1.0V whilethesimulationstepis0.5Vinthefigure.

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MICROWIND1.020

Fig.10.TheId/VgtofindVTOandfitGAMMA(Es207_20x20.MESfile).

ClickonIdvs.Vd.IncreaseTHETAtobendthecurveinordertofinda compromise.Althoughnotsatisfactory,theresultisquitecorrect.

Fig.10.Fittingthemodelwiththemeasureddatafile(Es207_20x20.MESfile).

NowloadanewmeasurementsuchasEs207_N20x0,8.mes.ClickonIdvs.Vg IncreaseLDinordertofittheslopeintheId/Vgcurve.

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MICROWIND1.021

Fig.11.SmallchannelMOSmeasurement(Es207_20x0,8.MESfile).

ClickonIdvs.Vd.AdjustVMAXtofitthetransitionpointbetweenthelinearand thesaturatedregionaccordingtothemeasurement.Next,adjustKAPPAtoadapt thepositiveslopeinthesaturatedregion.

Fig.11.SmallchannelMOSmeasurement(Es207_20x0,8.MESfile).

ClickonId(log)/Vg.Verifythattheslopeiscorrectinsubthresholdmode.Ifnot youcanadjusttheslopeusingNSS.Noticethatthemeasurementlimitisinthe orderofthenA.Thisiswhynoreliabledataisavailablebelow109A(Figure12).

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MICROWIND1.022

Fig.12.SmallchannelMOSmeasurementinthesubthresholdregion(Es207_20x0,8.MESfile).

The PMOS Transistor

Thepchanneltransistorsimulationfeaturesthesamefunctionsasthenchanneldevice. ClickonpMOS inthemenu.ThesoftwareswitchestothepchannelMOSsimulation,as showninFigure13.NotethatthepMOSgivesonlyhalfofthemaximumcurrentgivenby thenMOSwiththesamedevicesize.

Fig.13.SimulationofthepchannelMOS.

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3.DesignofaCMOSInverter

ThischapterisdedicatedtothelayoutdesignofasimpleCMOSinverter.Youwilllearn howtodrawmanuallyalltheelementsofthecell(i.e.boxes,layers,text,andproperties). Youwillusethedesigntoolsquiteintensively.

The CMOS Inverter

TheCMOSinverterincludes2transistors.Oneisanchanneltransistor,theotherap channeltransistor.Thedevicesymbolsarereportedbelow.Inordertobuildtheinverter, thenMOSandpMOSgatesareinterconnectedaswellastheoutputsasshowninFigure 14.

nMOS

pMOS Devicesymbols

NPN

Vdd

Vss(Ground)

Input

Output

Input

Output

InverterSymbol InverterPrinciples

Fig. 14. The schematic diagram of the CMOS inverter with one nMOS at the bottom and one pMOS at the top.

Manual Design
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MICROWIND1.024

Using the following procedure, you can create a manual design of the inverter. The defaulticonisthedrawingiconshownabove.Itallowsboxediting.Thedisplaywindow is empty. The palette is located in the lower right corner of the screen. A red color indicatesthecurrentlayer.Initiallytheselectedlayerinthepaletteispolysilicon.Thetwo firststepsareillustratedinFigure15. Fixthefirstcorneroftheboxwiththemouse. Whilekeepingthemousebuttonpressed,movethemouse. totheoppositecornerofthebox. Releasethebutton.ThiscreatesaboxinpolysiliconlayerasshowninFigure24. Theboxwidthshouldnotbelowerthan2,whichistheminimumwidthofthe polysiliconbox.

Fig. 15. Creating a polysilicon box.

Now,drawtwomoreboxesasinFigure16.Trytokeepclosetotheshapeandsizeofthe example.

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Fig. 16. Creating three polysilicon boxes.

ChangethecurrentlayerintoN+diffusionbyaclickinthepaletteonthe DiffusionN+ button.BesurethattheredlayerisnowtheN+Diffusion.Drawandiffusionboxatthe bottomofthedrawingasinFigure17.Ndiffusionboxesarerepresentedingreen.The intersectionbetweentheN+diffusionandthepolysiliconcreatesthechanneloftheMOS device.

Fig. 17. Creating the N-channel and P-Channel devices.

Change the current layer into P+ diffusion by a click in thepalette onthe button P+ Diffusion.DrawapdiffusionboxatthetopofthedrawingasinFigure29.Ndiffusion boxes are represented in green. The intersection between the P+ diffusion and the polysiliconcreatesthechannelofthepMOSdevice. 25

MICROWIND1.026

ChangethecurrentlayerintoNWellbyaclickonthecorrespondingbuttoninthepalette. Drawawellallaroundthep+diffusion,asinFigure18.Usekeyboardarrows(upkey)to viewtheupperpartofthelayout.

Fig. 18. Creating the well for the P-Channel Device.

Process Simulation

Clickonthisicontoaccessprocesssimulation.Thecrosssectionisgivenbyaclickon the mouse at the first point and the release of the mouse at the second point. In the examplebelow(Figure19),thecrosssectionofthenchannelMOSdeviceappearsonthe left,andthecrosssectionofthepchannelMOSdeviceontheright.

Fig. 19. The cross-section of the nMOS and pMOS devices.

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Contacts and Metal Interconnects

Thediffusionareasmustbejoinedusingametallayer.Themetallayerisisolatedfromthe diffusionsbyathicksilicondioxideSiO2layer.Thecontactlayerisusedtodrillaholein theoxideinordertojointhemetalandthediffusions.Youcoulddrawthecontactbox manuallybyselectingthelayerContactanddrawinga2x2box. Afastsolutionistousethepredefinedmacrosatthetopofthepalette.Variouscontacts builtaccordingtodesignrulesareproposed.

Contact diffn/ metal Contact poly/ metal Contact diffp/ metal Contact via/ metal

Fig. 20. The contact macros.

Choosethediffn/metalcontacticoninthepalette.Thecontactoutlinewillappear.Fixthe contactinsidethen+diffusionarea.Clickagainonthediffn/metalcontactandplaceitat theuppercornerofthenwellbox.ThiscontactisusedtopolarizethewellatVDD.The diffusionN+inthenwellmakesanohmiccontactandpreparesfortheVDDpolarization usingmetallayers.Finally,clickonthediffp/metaliconandfixthecontactinsidethep+ diffusionarea. Select the metallayer inthe palette. Draw ametal bridge between the n+ and p+ contacts.TheCMOSinverterlayoutisalmostcompleted(Figure21).Theremainingtaskis todefinewherethesupply,theground,theinputandtheoutputare.

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Fig. 21. The metal bridge and the inverter are completed.

Add Properties for Simulation

Propertiesmustbeaddedtothelayouttofixtheground,thesupply,theinputandthe outputs.Thesummaryofavailablepropertiesisreportedbelow.

VDD property VSS property Clock property Node visible Pulse property

Fortheinverterexample,wemustassigntheupperpdiffusiontoaVDDpowersupply, andthelowerndiffusionboxtoaVSSgroundvoltage.Wealsoneedtospecifyaclockas theinputfortheINnodeandhavealookattheoutputOUT.

StuckatVdd:ClickontheVddiconandclickontheupperpdiffusionbox. TheVddpropertyissenttothenode. 28

MICROWIND1.029

AlsoclickintheNWellregioninsidewhichthepMOSislocated.TheNWell mustalwaysbeatVDDvoltagetokeepthepMOSjunctionsinverted. HoldatVss:ClickontheVssicon,clickonthelowerndiffusionbox. TheVsspropertyissenttothenode. ApplyaclocktonodeIN:ClickontheClockiconandonthepolysilicongate. TheClockmenuappears(Seebelow).ClickonOK.Adefaultclockwith3ns periodisgenerated.TheClockpropertyissenttothenodeandappearsat therighthandsideofthedesiredlocationwiththenameclock1.

Fig. 22. The clock menu.

Watchtheoutput:ClickontheVisibleiconandthen,onthemetalbridge. Thewindowbelowappears.ClickOK.TheVisiblepropertyissenttothenode. Theassociatedtexts1isinitalic.Thechronogramofthisnodewillappear inthenextsimulation.

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Analog Simulation
IMPORTANT:AlwayssaveBEFOREsimulation!ClickonFileinthemainmenu.Move thecursorto Saveas... andclickonit.Anewwindowappears,intowhichyouareto enterthedesignname.Type,forexample,MYINV.Usethekeyboardforthisandpress . ThenclickonOK.Afteraconfirmationquestion,thedesignissavedunderthatfilename.

Click on Simulate in the main menu. The timing diagrams of the inverter appear, as showninFigure23.ClickonMoreinordertoperformmoresimulations.Clickon Stopto return totheeditor.ThegatedelayiscomputedatVDD/2,thatis2.5V,between the signalselectedintheStartNodelistandthesignalselectedwiththeStopNodelist.

Fig. 23. Analog simulation of the CMOS inverter. The output has the opposite value of the clock input.

Click on Voltage & Currents to see both currents and voltages (Figure 24). The currentpeakscanbeseenintheupperwindow.Allvoltagesarereportedinthe lowerwindow.Thecurrentscalecanbeadjustedusingapredefinedlistofvalues. SomecurrentisconsumedatVDDsupply,mainlywhentheoutputoftheinverter risestoVDD.SomecurrentisconsumedatVSS,mainlywhentheoutputgoesdown tozero.

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Clickon Voltagevs.Voltage toseetheDCtransfercharacteristicsoftheinverter (Figure24bottom).ThecommutationpointoftheinverterVcistheinputvoltagefor whichtheoutputisclosetoVDD/2.InthecaseofFigure24,Vcisaround1.8V. ClickonBacktoEditortoreturntotheeditor.

Fig. 24. Current consumption of the CMOS inverter (top) and DC characteristics of the CMOS inverter(bottom).

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Is your layout correct ?

Clickontheaboveicontoanswerthequestion.The DesignRuleChecker(DRC)scansthe designandverifiesasetofdesignrules.Theerrorsarehighlightedinthedisplaywindow, withanappropriatemessagegivingthenatureoftheerror.Detailsaboutthepositionand typeoferror(s)appearonthescreen. Onlyanerrorfreelayoutcanbesenttofabrication.SeeChapter8formoredetailsabout thedesignrulesandsomegraphicalexampleswhichwillhelpyoutounderstand the originoftheerror.

Parametric Analysis of the Inverter

ClickonAnalysis>ParametricAnalysis.Clickontheoutputnodeoftheinverterinthe layout.Thewindowbelowappears.Theparametricanalyzerallowsyoutoinvestigate easilytheinfluenceofvariousparametersontheinverterdelay.

Fig. 25. The parametric analyzer

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SelecttheDelayintheMeasurementmenu. SelectpowersupplyintheParameterchoice. Click on Start Analysis. An iterative procedure conducts simulations and extractsthedelayfromthesimulationforeachvalueofVDDpowersupplyas definedintheRangemenu.TheresultinFig.25showsthatthegatedelay decreasesrapidlywiththepowersupply.

Fig. 26. Investigation of the VDD supply effect on the power consumption (top), and the effect of the output capacitance load on the delay (bottom).

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Otherpossibleinvestigationsconcernthefrequencyanddissipation.Thetemperature, thenodecapacitanceandthevoltagesupplyareparametersworthofinterestare.Fig 26givesanaccountoftheincreaseofthepowerconsumptionwiththeVDDsupply.Fig 26alsopointsout(bottom)thedelayincreasewiththeoutputcapacitanceload. In order to obtain this curve, you should select the Node Capacitance in the parameterlistfirst,andthenmodifytheitemsFrom,ToandStepaccording toFig.26.Oncethosemodificationshavebeenmade,youcanstarttheanalysis.As expected,thegatedelayincreasesrapidlyalongwiththeoutputcapacitance.

Save & Quit

Click on F2 or File > Save. The design is saved under the current name. The MSK appendixisautomaticallyaddedtotheusersfilename.ToleaveMICROWIND,clickon File>LeaveMicrowindinthemainmenu.

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4.BasicGates

The Nand Gate

ThetruthtableandtheschematicdiagramoftheCMOSNANDgatewith2inputsare showninFigure26.TheNANDgateconsistsoftwonMOSinseriesconnectedtotwo pMOSinparallel. NAND2inputs A B OUT 0 0 1 0 1 1 1 0 1 1 1 0

A Output B NANDSymbol

B Output

NANDdesign Fig. 26. The truth table and schematic diagram of the CMOS NAND gate design.

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MICROWIND1.036

Compiling the Nand Gate

YoumayloadtheNANDgatedesignusingthecommand File>Read>NAND.MSK. YoumayalsodrawtheNANDgatemanuallyfortheInvertergate. Analternativesolutionistousethelogiceditortogeneratetheverilogdescriptionofthe NANDgate,andtocompilethisverilogdescriptionintolayout.Inthiscase,completethe followingprocedure: AddtheNANDsymbol,twobuttonsandonelampinthelogiceditorDSCH. Addinterconnectsandverifythelogicbehaviorofthecell.

InDSCH,ClickonFile > CreateVerilogFile,andclickonSave.The Verilogtextisexample.txt.

InMicrowind,ClickonCompile>CompileVerilogFile.Selectexample.txt intheappropriatedirectory.TheresultisreportedinFigure27.

36

MICROWIND1.037

Fig. 27. A NAND cell created by the CMOS compiler.

Simulation of the NAND Gate

ThecompilerhasalreadyfixedthepositionofVDDpowersupplyandthegroundVSS. ThetextsA,B,andShavealreadybeenfixedtothelayout.

Make the node visible Add a Clock

ClickontheClockicon

andclickinsidethepolysiliconboxofthegateA.

Theclockwindowappears. ClickonOKtoassignthedefaultclockparameterstoA. Now, click inside the polysilicon box of the gate B. A new clock window appears. ClickonOKtoassignthenewclockparameterstoB. Noticethattheclockperiodhasbeenautomaticallymultipliedbytwo inordertoscanalllogicinputcombinations.

37

MICROWIND1.038

ClickontheVisibleiconandontheoutputnodeS.

ClickonSimulate.ThetimingdiagramsappearasshowninFigure28. TherisetimeisfasterbecauseofthepMOSdevicesinparallel.

Fig. 28. Simulation of the NAND gate.

The 3-Input OR Gate

ThetruthtableandtheschematicdiagramofthethreeinputORgateareshowninFigure 29.YoumayusetheDSCHlogiceditoragaintodesignaschematicdiagramoftheOR gate,generateaVerilogdescription,andcompilethetextfileinMicrowind.Ascanbe seenintheschematicdiagramandinthecompiledresults,thegateisthesumofaNOR3 gateandaninverter.InCMOS,theNegativegates(NAND,NOR,INV)arefasterand simplerthanthenonnegativegates(AND,OR,Buffer).

38

MICROWIND1.039

Oncethecellhasbeencompiled,addoneclocktoeachinput(A,BandC).Addthevisible propertytotheoutputout.ThenclickonSimulate.
OR3Inputs A B C Or3 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 1

A B Output

B C OR Symbol C Nor3 A B C Output

OR gate design

Fig. 29. The truth table, design and schematic diagram of the NOR3 gate (NOR3.MSK).

39

MICROWIND1.040

Fig. 30. Simulation of the OR gate with 3 inputs (OR3.MSK).

The XOR Gate

ThetruthtableandtheschematicdiagramoftheCMOSXORgateareshowninFigure46. Nosimpleimplementationispossible,evenifmanydifferentsolutionscanbegiven.The proposedsolutionconsistsofatransmissiongateimplementationoftheoperator.
XOR2inputs A B OUT 0 0 0 0 1 1 1 0 1 1 1 0 A Output B XORSymbol A N1

AXORB

XORgatedesign Fig. 31. The truth table and schematic diagram of the XOR gate.

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MICROWIND1.041

ThetruthtableoftheXORcanbereadasfollow:IFB=0,OUT=A,IFB=1,OUT=Inv(A). TheprincipleofthecircuitpresentedinFigure31istoenabletheAsignaltoflowtonode N1ifB=1andtoenabletheInv(A)signaltoflowtonodeN1ifB=0.Thenode OUTinverts N1,so that we canfind the XOR operator. Notice that the nMOSand pMOS devices situatedinthemiddleofthegateserveaspasstransistors. ThefileiscalledXOR.MSKandisreadyforsimulation.Clickon Simulate inthemain menu.Dontforgettocheckthechronogramvalues. YoumayalsouseDSCHtocreatethecell,generatetheVerilogdescriptionandcompile theresultingtext.InMicrowind,theVerilogcompilerisabletoconstructtheXORcellas reportedinFigure32.

Fig. 32. The layout design of the XOR gate (XOR.MSK).

SIMULATION. Add clock properties to the inputs A and B, a visible property to the outputandverifythetruthtableoftheXORgate(Figure32).Youmayalsoaddavisible property to the nxor intermediate node which serves as an input of the second inverter.SeehowthesignalisalteredbyVtn(whenthenMOSisON)andVtp(whenthe pMOSisON).Fortunately,theinverterregeneratesthesignal.

41

MICROWIND1.042

Fig. 33. Simulation of the XOR gate (XOR.MSK).

Complex Gates
TheonelinecomplexgatecompilerisabletogeneratetheCMOSlayoutcorrespondingto anydescriptionbasedontheoperators AND and OR,alsocalledcomplexgates.Inthe equation,thefirstparameteristheoutputname.Inthepresentcasethatnameis s.The sign'='isobligatory.The'/'signcorrespondstotheoperationNOTandcanbeusedonly rightafterthe'='sign.Theparenthesis'('')'areusedtobuildthefunction,where'.'isthe ANDoperatorand'+'istheORoperator.

Thecomplexgatecompilerproducescompactcellswithhigherperformancesintermsof spacingandspeedthanNAND/NORbasedconventionallogiccircuits. 42

MICROWIND1.043

Fig. 34. A compiled complex gate (CARRY cell)

COMPILERSYNTAX CELL F ORMULA Inverter out=/in NANDgate n=/(a.b) ANDgate s=(a.b) 3InputOR s=a+b+c 3InputNAND out=/(a.b.c) ANDORGate cgate=a.(b+c) CARRYCell cout=(a.b)+(cin.(a+b)) TRANSISTORSIZE.Thedefaultdevicesizeisgivenbythedesignrules.Youmaychange thenMOSandpMOSwidthintheoptionmenubeforeclickingonCOMPILE. IMPLEMENTATION.Thepchanneltransistorsarelocatedatthetopofthenchannel transistornet.Ifthe'/'operatorhasnotbeenspecifiedafterthe'='sign,aninverteris addedattherighthandsideofthecompiledcell.ThatiswhyanANDgateiscompiledas aNANDgatefollowedbyaninverter.

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MICROWIND1.044

4.ArithmeticGates

Half-Adder Gate
TheHalfAddergatetruthtableandschematicdiagramareshowninFigure34.TheSUM functionismadewithanXORgate,theCarryfunctionisasimpleANDgate.Loadthe layoutdesignoftheHalfAdderthroughthe F3 (eq.to File>Read)and HADD.MSK sequence.

HALFADDER A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1

Fig. 34. Truth table and schematic diagram of the half-adder gate (HADD.MSK).

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MICROWIND1.045

FULLCUSTOMLAYOUT.Youmaycreatethelayoutofthehalfadderfullybyhand using the XOR gate first by inserting the AND gate layout (Command File > Insert AND2.MSK,orCompilecarry=A.B).Thendrawtheinterconnectsbetweengates. Usethepolysiliconlayerforshortconnectionsonly,becauseofthehighresistanceofthis material. Use metal as much as you can, and Poly/Metal, Diff/Metal contact macros situatedintheupperpartofthePalettemenutolinkthelayerstogether. VERILOGCOMPILING.YoumayuseDSCHtocreatetheschematicdiagram;verifythe latterwithbuttonsandlampsandgeneratetheVerilogtextbyusingthecommandFile >CreateVerilogFile.WithoutusingDSCH,youmayalternativelyuseatexteditor (NotePadorWordPad),andenterthefollowingVERILOGtext.

Fig. 35. VERILOG description of the half-adder gate (Hadd.txt)

ClickonthecommandFile>Compile>CompileVerilogFile.Selectthetextfile createdjustbeforebyasimpletexteditor.

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MICROWIND1.046

Fig. 36. Load the VERILOG description of the half-adder gate (Hadd.txt)

Clickon Compile. Whenthe compilingis complete,click onOK. Theresultisshown below.TheXORgateisroutedontheleftandtheANDgateisroutedontheright.

Fig. 37. Compiling of the VERILOG description of the half-adder gate (Hadd.txt)

Now, add two clocks inside label A and B, then add an eye on Carry and Sum. Click on Simulate in the main menu. The timing diagrams appear and you shouldverifythetruthtableofthehalfadder.ClickonStoptoreturntotheeditor.

46

MICROWIND1.047

Fig. 38. Simulation of the half-adder (HADD.MSK).

Full-Adder Gate
ThetruthtableandschematicdiagramforthefulladderareshowninFigure39.TheSUM ismadewithtwoXORgatesandtheCARRYisacomplexgate,asshownbelow.
FULLADDER A B C SUM CARRY 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

Fig. 39. The truth table and schematic diagram of a full-adder (FADD.MSK file).

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MICROWIND1.048

Youmayedittheschematicdiagramofthefulladder using DSCH.Verify thecircuit behaviorandgenerateitscorrespondingVerilogdescription.TheVERILOGdescriptionof theFulladderisgivenbelow(fadd.txt):

module fulladd(sum,carry,a,b,c); input a,b,c; output sum,carry; // internal node wire sum1; xor xor1(sum1,a,b); xor xor2(sum,sum1,c); and and1(c1,a,b); and and2(c2,b,c); and and3(c3,a,c); or or1(carry,c1,c2,c3); endmodule

Click on the command File > Compile > Compile Verilog File. Select the text file fadd.txtshownabove.ClickonCompile,andonOKattheendofthecompilation. In Figure40,theXORgatesareattheleftsideofthedesignwhilethecomplexgateisatthe rightsideofthecell. ThesimulationofthefullAdderisconductedasfollow.First,addaclockonlabelsA, BandC.ForclockA,enlargethevalueoftheclockinordertoslowdownthe chronogram.Thecelliscomplexandcannotreactveryrapidly.Donothesitatetozoomin somepartsofthelayouttobesuretoaddthepropertytothedesiredlabel.Thenaddan eyetocarryandsum.TheresultisgiveninFigure41.

Fig. 40. Compiling of a full-adder described in VERILOG.

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MICROWIND1.049

Fig. 41. Simulation of a full-adder (File FADD.MSK).

Comparator
Thetruthtableandtheschematicdiagramofthecomparatoraregivenbelow.TheA=B equality represents an XNOR gate, and A>B, A<B are operators obtained by using invertersandANDgates.
COMPARATOR A B A>B A<B A=B 0 0 0 0 1 0 1 0 1 0 1 0 1 0 0 1 1 0 0 1

49

MICROWIND1.050 Fig. 42. The truth table and schematic diagram of the comparator (COMP.SCH).

UsingDSCH,thelogiccircuitofthecomparatorisdesignedandverifiedatlogiclevel. Then the conversion into Verilog is invoked (File > Make verilog File). Microwind compilestheverilogtextintolayout.Thelayoutandsimulationofthecomparatorisgiven inFigure43.TheXNORgateislocatedattheleftsideofthedesign.TheinverterandNOR gatesareattherightside.Aftertheinitialization,A=Brisesto1.TheclocksAandB producethecombinations00,01,10and11.NoticethesmallglitchonA>Batt=12ns.This glitchisnotadesignerror.Onthecontrary,itshowsthatduringthetransitionofAandB thesituationA>Boccursandthatthecellisfastenoughtoreact.

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MICROWIND1.051

Fig. 43. Simulation of a comparator (COMP.MSK file).

5.LatchesandMemories

RS Latch
TheRSLatchismadeupoftwointerconnectedNANDgates.TheResetandSetinputsare activelow.ThememorystatecorrespondstoReset=Set=1.ThecombinationReset=Set=0 shouldnotbeused.
RSLATCH R S Q nQ 0 0 X X 0 1 0 1 1 0 1 0 1 1 Q nQ

Reset nQ

Q Set

Fig. 44. The truth table and schematic diagram of a RS latch made from 2 NAND gates (RS.MSK).

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MICROWIND1.052

DESIGN.YoucanusetheVERILOGcompilerforthecreationoftheRSlatchwithcell declarationsasfollow.Seers.txttextfile.

Fig. 45. The design of a RS latch made from 2 NAND gates (RS.MSK).

SIMULATION.AssignanegativepulsetoR.Thepulseiconisoneofthesimulationicons andisshownbelow.Selectthisicon,thenclickneartheResetlabel.Thepulseparameter windowappears.Thedefaultpulseispositive.Invertthevoltagecursorssituatedonthe leftofthewindowinordertoprogramanegativepulse.

Pulse property

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MICROWIND1.053

Assign another negative pulse to Set. The pulse is automatically delayed from the previous pulse assigned to Reset. Click on Simulate in the main menu. The timing diagramsappearasreportedinFigure46. Thesimulationstepsarethefollowing: InputsRandSarefixedto1.Thelatchisinamemorystate.

AnegativepulseisappliedtoR.ThelatchoutputQgoestoalevelof0. Ashorttimeafter,anegativepulseisappliedtoS.ThelatchoutputQgoesto1.

Fig. 46. The simulation of a RS latch (RS.MSK).

D Latch

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MICROWIND1.054

ThetruthtableandschematicdiagramofthestaticDlatch,alsocalledStaticDFlipFlop, areshowninFigure47.ThedatainputDistransferredtotheoutputiftheclockinputisat level1.Whentheclockreturnstolevel0,thelatchkeepsitslastvalue.

DLATCH D H Q nQ 0 0 Q nQ 1 0 Q nQ 0 1 0 1 1 1 1 0

D Q H

nQ

Fig. 47. The truth table and schematic diagram of a D Latch (File DLATCH.MSK).

MANUALDESIGN.Usetheonelinecompilertocreatesuccessivelyoneinverter nd=/d, andtwocomplexgateswhichincludetheAND/NORcellsusingthesyntax Q=/(nQ+ (nd.h)) and nQ=/(Q+(d.h). Build the interconnections and run the Design Rule Checker.AssignaclocktoHandaclocktoD. VERILOG COMPILING. Compile the cells using the following description file dlatch.txt. Otherwise you can load a design of the Dlatch using the commands File > Read> DLATCH.MSK(Figure48).

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MICROWIND1.055

Fig. 48. The design of a D-latch (DlatchLevel.MSK).

SIMULATION. Click on Simulate of the main menu. The timing diagrams appear as reportedinFigure49.Thesimulationstepsarelistedbelow: TheclockHisatlevel0sothatthelatchcanbeinamemorystate. TheinputDchanges.Nothingchangesintheoutput. TheclockHgoestolevel1.TheoutputQcopiestheinputD. TheclockHgoesbacktolevel0.TheoutputQkeepsitslastvalue.

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MICROWIND1.056

Fig. 49. The simulation of a D-latch (DLatchLevel.MSK).

RAM Memory
TheschematicdiagramofthestaticmemorycellusedinHighCapacityStaticRAMsis giveninFigure50.Thecircuitconsistsof2crosscoupledinvertersandtwonMOSpass transistors.ThecellhasbeendesignedtobeduplicatedinXandYinordertocreatea largearrayofcells.UsualsizesforMegabitSRAMmemoriesare256x256cellsorhigher. TheselectionlineSelconcernsallthecellsofonerow.Thelines DataandnDataconcern allthecellsofonecolumn.
Data Data

Memory

Select Fig. 50. The schematic diagram of the static RAM cell (RAM.MSK).

TheRAMlayoutisgiveninFigure64.Clickon File>Read>RAM.MSK toreadit.The DataandnDatasignalsaremadewithmetalandcrossthecellfromtoptobottom.This allowseasymatrixstyleduplicationoftheRAMcell.

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MICROWIND1.057

Fig. 51. The layout of the static RAM cell (RAM.MSK).

WRITECYCLE.Values1or0mustbeplacedon Data,andthedatainvertedvalueon nData.Thentheline Sel goesto1.ThetwoinverterlatchtakestheDatavalue.When returningto0,theRAMisinamemorystate. READCYCLE.Inordertoreadthecell,theline Sel mustbeasserted.TheRAMvalue propagatestoData,anditsinvertedvaluepropagatestonData. SIMULATION.ThesimulationparameterscorrespondtothewritecycleintheRAM.The simulationstepsareasfollows: . Memreaches1,nMem0(unpredicatablevalue). Datagetstovalue1andnDatatovalue0. Selisasserted.Thememorycellreachesstaysat1. Datagetstoavalueof0andnDatagetstoavalueof1. Selisstillasserted.Thememorycellgets0. Selisinactive.TheRAMisinamemorystate.

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MICROWIND1.058

Fig. 52. Write cycle for the static RAM cell (RAM.MSK).

Complete RAM 4x4 Bit

YoucanduplicatetheRAMcellintoa4x4bitarrayusingthecommand Edit>Duplicate XY.SelectthewholeRAMcellandanewwindowappears.Enterthevalue4forXand 4forYintothemenu.ClickonGenerate.Theresultisshownbelow.

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MICROWIND1.059

Fig. 53. Duplicating the RAM Cell in X and Y Thecolumndecoderisbasedonthefollowingschematicdiagram.Onelineisasserted whilealltheotherlinesareatzero.Inthiscircuitonelinewaspickedoutfromachoiceof fourlines.UsingANDgateswouldbeaneasysolution,butinordertosavetheinverter, wechoseNORgateswithinvertedinputs.

Fig. 54 - a. A line selection circuit

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MICROWIND1.060

Fig. 54- b . A line selection layout and its corresponding simulation (RamLineSelect.MSK)

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MICROWIND1.061

TheNORgateheightshouldbeadjustedtothatoftheRAMcellheight.Whenmakingthe finalassemblybetweenblocks,thecommandEdit>MoveAreaisveryimportant.This commandhelpstomoveaselectedblockwithalambdastep. Therowdecoderisbasedonthesameprinciplesasthoseofthelinedecoder.Themajor modificationisthatthedataflowsbothways,thatisfirstlyfromthecelltothereadcircuit (Readcycle)andsecondlyfromthewritecircuittothecell(Writecycle).Fig.55proposes anarchitectureforthis. ThenchannelMOSdeviceisusedasaswitchcontrolledbythecolumnselection.When thenchannelMOSisonandWriteisasserted,thedataissuedfromDataInisamplified bythebuffer,flowsfromthebottomtothetopandreachesthememory.If Writeisoff,the 3stateinverterisinhighimpedance,whichallowsonetoreadtheinformation.

Fig. 55. Row selection and Read/Write circuit (RamRow.MSK)

ThefinallayoutoftheRAM4x4isproposedinFig.56.Thesimulationproposesthe read andwritecyclesataspecificRAMcelladdress.

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Fig. 56. RAM 4x4 layout and simulation (Ram44.MSK)

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MICROWIND1.063

ThesimulationofFig.56canbedescribedasfollows.A[00]fixedlineselectionselectsthe upperline,thatwaysel0isassertedwhileallothersareat0.Thememorycellsmem00 andmem01donotreachthesameinitialstate:mem00getsto0andmem01isat1.When DataInisatzero,writingazerohasnoeffectonMem00.Butwhenthecolumnselection changes,DataIn=0iscopiedtoMem01. WhenDataInrisesto1(t=10ns),andwhenwriteis1,thememorycellschangefrom0to1. Itisinteresting topointoutthatthememorycellfightsagainstthelogicvaluebefore surrendingandchangingitsinternalstate.

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6.OtherProjects

This section expounds some typical layout projects and presents the general design principlesforthelayoutofeachproject.Thelatterarereadytosimulateitems.Theycan besimulatedinanytechnology,from1.2mto0.12m.Belowishowtoproceed: ClickRead>Filename, Selectthefilename, ClickSimulate.

Noticethatmostofthoselayoutsarecomplexandrequireasignificantamountoftimefor extractionandforsimulation.

Four-Bit Adder
Thiscircuitincludeonehalfadderandthreefulladders(SeeFigure57).Theresultofeach stagepropagatestothenextone,fromthetoptothebottom.Thecircuitallowsafourbit additionbetweentwonumbersA3,A2,A1,A0andB3,B2,B1,B0.Figure58detailsthefour bitadderlayout,andFigure59showsthecorrespondingsimulation.
4BITAdder(ADD4.MSK) NODE DESCRIPTION A3,A2,A1,A0 Firstnumber B3,B2,B1,B0 Secondnumber S3,S2,S1,S0 Result

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MICROWIND1.065 S0 S1 S2 S3 S4

A0 B0

A1 B1

A2 B2

A3 B3

Half adder

Full adder

Full adder

Full adder

Fig. 57. Schematic diagram of the four-bit adder (ADD4.MSK).

Fig. 58. Design of the four-bit adder (ADD4.MSK).

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Fig. 59. Simulation of the four-bit adder (ADD4.MSK).

2x 2 Bit Multiplier
ThemultipliercellismadeupofafulladdercellandaNANDgate.Thecellisbuiltforan iterativeimplementation,anda2x2bitmultiplicationisproposed.Thecircuitmultiplies inputA(2bits)withinputB(2bits)whichproducesaresultP,asdetailedinFigure60. Thecircuitdesigniscomplexandthesimulationtakesalotoftime.Themultiplierlayout isshowninFigure61.InthesimulationofFigure62,themultiplicationtimeis5nSinthe worstcase.

MULTIPLIER2x2BITS NODE DESCRIPTION A0,A1 DigitalInputA B0,B1 DigitalInputB S0 Bit0resultofthemultiplicationAxB S1 Bit1 S2 Bit2 S3 Bit3

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MICROWIND1.067
B1 0 A0 B0 0

0 0 A1 P0

0 P1 P3 P2

Fig. 60. Truth table and schematic diagram of the 2x2 bit multiplier (MUL22.MSK).

Fig. 61. Design of the 2x2 bit multiplier (MUL22.MSK).

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Fig. 62. Simulation of the 2x2 bit multiplier (MUL22.MSK).

Two-Bit Counter
The onebit counter is a static register controlled by a single clock H. Its schematic diagramisshowninFigure63.Inordertobuildatwobitcounterweusedtwocounter cellsthatwehaveinterconnectedasfollows:theclockofthesecondstageistheoutputof thefirstone.Theclocks HandnHchangesthestateofC0ateachrisingedge.Theclock C0 changes the state of C1 at each rising edge. The outputs C0 and C1 make a 2bit counter.ThelayoutisreportedinFig.64anditscorrespondingsimulationisshownin Figure65. TwoBitCounter NODE DESCRIPTION H Firststageclock nH InvertedclockH P1 Internalregisternodeofstage1 C0 Firstcounteroutput nC0 InvertedclockC0 P2 Internalregisternodeofstage2 C1 Secondcounteroutput nC1 InvertedclockC1

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H Div 2

H Clock Divider

H One Stage

H div 2 One Stage

H div 4

Fig. 63. Schematic diagram of the 2-bit counter (DivFreq.MSK).

Fig. 64. Design of the 2-bit counter (DivFreq.MSK).

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Fig. 65. Simulation of the 2-bit counter (DivFreq.MSK).

Wide-Range Amplifier
Thewiderangeamplifierisbuiltusingavoltagecomparatorandapoweroutputstage. Its schematic diagram is reported in Fig. 66. The difference between V+ and V is amplifiedanditproducesaresult,codified:Vout.Thegainnear2.5Vismorethan1,000. UsetheVoltagevs.VoltagesimulatormodetogetthetransfercharacteristicsVout/V+. Theinputrangeisaround0.5Vto4.0V. YoucaneasilybuildafollowerbydesigninganextraconnectionfromVouttoV.This layoutisshowninFigure66.Theoutputstageisnotstrongenoughtobeabletodrive largeloadssuchasoutputpads.
WIDERANGEAMPLIFIER NODE DESCRIPTION V+ Positiveanaloginput V Negativeanaloginput Vbias Biasvoltage Vout Analogoutput

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Output

Vout V+

B Vbias

AmplifierSymbol

Outputstage Vbias

WideRangeAmplifier

Differentialpair

Fig. 65. Node description and schematic diagram of the analog amplifier (AMPLI2.MSK).

. Fig. 66 Design of the analog amplifier (AMPLI2.MSK).

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MICROWIND1.072

Fig. 67. Transient simulation of the analog amplifier (AMPLI2.MSK) connected as a follower

Fig. 68. DC Simulation of the analog amplifier (AMPLI2.MSK) in follower mode, using voltage vs. Voltage mode.

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Interface with PSPICE

ThesimulationofthetransientandDCcharacteristicsoftheamplifiercanbeperformed usingMicrowind.Unfortunately theACresponsecannotbe computed. Thecommand File>MakeSpiceFileconvertsthedesignintoaPSPICEcompatibledescriptionbased onMOSdevicesandparasiticcapacitances(Fig.69).

Fig. 69. Generation of the file AMPLI2.CIR compatible with SPICE

Figure69depictstheinterfacewindow.TheleftpartofthewindowdetailsthelistofMOS deviceswiththeirassociatedwidthandlengthinlambdaunit.Therightpartliststhe contents of the PSPICE compatible file, "AMPLI2.CIR" generated from the electrical extractionofthelayoutAMPLI2.MSK. ToobtaintheACresponseoftheamplifier,theAMPLI2.CIRsourcefilemustbemodified asfollows:anACsourcemustbedeclared(ChoosetheinputV+andadd"AC10"),and the.TRANmodemustbereplacedby.ACDEC101K100MEGforexample(ACanalysis, 10points/decade,from1KHzto100MHz).RunPSPICEandseetheresult.TheDBmode isdrawnusingthecommandVDB(outputnode)inthePLOTcommand"AddTrace".

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Analog-Digital Converter
Theanalogdigitalconverterconvertsananalogvalue Vin intoatwobitdigitalvalue calledA0,A1.TheflashconverterusesthreeconvertersandacodinglogictoproduceA0 andA1(Figure70).Averycomplexlogiccircuitand255comparatorswouldbeusedfor anADCeightbitflash. Thepolysiliconhasahighresistance(50persquare)andcanbeusedasaresistornetwork (LeftofFigure71),whichgeneratesintermediatevoltagereferencesusedbythevoltage comparators located in the middle. The resistance symbol is inserted in the layout to indicatetothesimulatorthatanequivalentresistancemustbetakenintoaccountforthe analogsimulation. Openloop amplifiers are used as voltage comparators. The comparisons address the decodinglogicsituatedtotherightandthatprovidescorrectA0andA1coding.
ANALOG/DIGITALCONVERTER NODE DESCRIPTION V Analoginput C0 Resultofcomparisonwith1.25V C1 Resultofcomparisonwith2.5V C2 Resultofcomparisonwith3.75V A1 Digitaloutput A0 Digitaloutput 5V Vin

Polyresistor

3.75V 2.5V 1.25V 0V

Ampliferusedascomparator + + + C0 C1 CodingLogic A0 C2 A1

Fig. 70. Node description and schematic diagram of the analog-digital converter (ADC.MSK).

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Fig. 71. Design of the analog-digital converter (ADC.MSK).

Fig. 72. Simulation of the analog-digital converter (ADC.MSK).

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In the simulation shown in Figure 72, the comparators C0 and C1 work well but the comparatorC2isusedintheupperlimitofthevoltageinputrange.Thegenerationof combinations00,01and10iscorrect.Thegenerationof11isslow.

Digital-Analog Converter
Thedigitalanalogconverterconvertsadigitalthreebitinput(A0,A1,A2)intoananalog valueData.Thepolysiliconresistivenetgivesintermediatevoltagereferenceswhichflow totheoutputviaatransmissiongatenet.Theresistancesymbolisinsertedinthelayoutto indicatetothesimulatorthatanequivalentresistancemustbetakenintoaccountforthe analogsimulation. TheschematicdiagramisshowninFigure73.Thelayoutofthedigitalanalogconverteris showninFigure74.
DIGITALANALOGCONVERTER NODE DESCRIPTION Ai nAi Vout InputAi InvertedinputAi Analogoutput

5V

Polyresistor

4.375V 3.75V 3.125V 2.5V Data 1.875V 1.25V 0.625V 0V A2 A0 nA0 A1 nA1 nA2

Fig. 73. Node description and schematic diagram of the digital-analog converter (DAC.MSK).

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Fig. 74. Design of the digital-analog converter (DAC.MSK)

Fig. 75. Simulation of the digital-analog converter (DAC.MSK).

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ThesimulationoftheDAC(Fig.75)showsaregularincreaseoftheoutputvoltage Vout withtheinputcombinations,from000(0V)to111(4.375V).Eachinputchangeprovokesa capacitancenetworkchargeanddischarge.

Input-Output Pad Interfacing

Wegiveheresomedetailsaboutinputoutputpadinterfacing.Thebasicbondingpadsize is 100x100m. The pad consists of a sandwich of metal2, via and metal1 layers. For advanced technologies, all metal layers are stacked on the top of each other. Use the processsimulatortoverifythatthepassivationoxidehasbeenremovedfromoverthe pad,sothatagoldconnectioncanbefixeduponit. The inputoutput pad contains one input stage with a polysilicon resistor and two protectiondiodes.Theoutputstagecontainsachainofinverters.Thelaststageisa3state invertersothatthebuffercanbeturnedoff.
INPUT/OUTPUTPAD NODEDESCRIPTION Vout Digitaloutputvalue EN Enabledigitaloutput nEN InvertedEnabledigitaloutput Data Padinputvalue

nEn

DataOut

PAD

En InputResistor DataIn

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Fig. 76. Design of an input-output pad (PAD.MSK)

Pad Ring

Clickonthechiplibraryiconandclickon Pads.ThewindowreportedinFig.77appears. Selectthesize100x100mwhichenablesthepadringoptions.Apadringwith3padsin Xand3padsinYisgeneratedbyaclickon GeneratePad.Inthatcase,asetofpadsis addedtoyourcircuit.TheVSSpadissituatedatthebottom,andtheVDDpadatthetop withtheassociatedpowerrings.

Fig. 77. Pads added to generate a pad ring around the chip.

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MICROWIND1.080

Figure78displaysanexampleofcircuitwithitsinputoutputpadsandinterconnects.The chipcontainsapadringof28input/outputs(CHIP.MSKfile).

Fig. 78. A complete chip with I/O pads and internal logic and analog cells (CHIP.MSK)

ESD Protections Theinputpadincludessomevoltageboostingandundervoltageprotectionslinkedwith problemsofelectrostaticdischarge(ESD).Suchprotectionsarerequiredastheoxideofthe gateconnectedtotheinputcouldbedestroyedbyovervoltage.Oneofthemostsimple ESDprotectionismadeupofasetoftwodiodesandaresistance(Fig.79).Onediode handlesthenegativevoltageflowinginsidethecircuit(N+/Psubstrate),theotherdiode (P+/Nwell)handlesthepositivevoltage. ThelayoutoftheN+/P_SubstratediodeincludesasimpleN+diffusioninthePsubstrate (thecathodeK),surroundedbyP+contactswhichpolarizethePsubstrate(theanodeA). ThecurrentstartsflowingbetweenAandKifthevoltageisroughlyover0.6V.Inthe reverse mode, the current is very small, in the order of some picoAmpere. The polarizationofthePsubstrateisusually0V.ThediodeN+/Pwillbeonifthevoltageof theN+regionislessthan0.6V. 80

MICROWIND1.081

Fig. 79. Detail of the Input protection used against electrostatic discharge (CHIP.MSK)

Onesimplewaytoaddadiodeinthelayoutistoclickonthecelllibraryicon,thenclick ontheContactsmenuandtoasserttheoptions:Diffp/MetalandDiffN+on Nwell.ThiscreatesaP+/Nwelldiodewithitsappropriatecontacts(Fig.80).

Fig. 80 -a : Create a diode based on a Diffp/Metal contact in nwell

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MICROWIND1.082

Fig. 8- b :. Create a diode for I/O pad protections

Path between Pads and Cells

Draw a path

Thepathcommandconsiderstheeasyeditingofapathinonelayeronly(Fig.81). Thepathwidthcanbechanged,aswellasthealignmenttotheroutinggrid.Asetof contactscanalsobeplacedatbothendsofthepath.Thiscommandisveryusefulfor VDDandVSSsupplydrawingandsinglelayerinterconnects.

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MICROWIND1.083

Fig. 81. The path menu and a path example

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MICROWIND1.084

7.DesignRules

ThissectiongivesinformationaboutthedesignrulesusedbyMicrowind.Youwillfindall thedesignrulevaluescommontoallCMOSprocesses.Allthoserules,aswellasprocess parametersandanalogsimulationparametersaredetailedhere. Theevolutionoftheintegratedcircuittechnologyresidesmainlyinthereductionofthe featuresize,alsocalledlithography.Asthechartbelow(Fig.82)shows,in1986,the minimum feature size was around 1.2m. Ten years later, the lithography had been downsized to 0.25m. For year 2000, the lithography around 0.12m is expected for leadingedgeproductssuchashighperformancemicroprocessors.
Lithography Lambda (m) Year Metal layers Power Supply (V) 1.2m 0.8m 0.6m 0.35m 0.25m 0.18m 0.12m 0.6 0.4 0.30 0.2 0.15 0.1 0.07 1986 1988 1992 1994 1996 1998 2000 2 2 3 5 6 6 6 5.0 5.0 3.3 3.3 2.5 1.9 1.5 250 200 120 75 65 50 40 0.8 0.7 0.6 0.5 0.45 0.40 0.30 Oxide(A) Threshold (V) Typical Microwinddesign

gate delay rulefile (picosec) 840 800 410 360 260 250 240 ams12.rul es208.rul ams06.rul cmos035.rul cmos025.rul cmos018.rul cmos012.rul

Fig.82:TechnologicaltrendsforMOSdevices

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MICROWIND1.085

As can be noticed, the number of metal layers used for interconnects has been continuously increasing in the course of the past ten years while the power supply decreasedduetothereductionoftheMOSgateoxidethickness,andthustheloweroxide breakdown voltage. The MOS threshold voltage was also significantly reduced. The overallconsequenceofthistechnologyscaledownisthegatedelaydecreaseleadingto higheroperatingfrequencies, althoughtherapidreductionofthepowersupplyslows downthegainintermsofperformances. Somedetailsaboutthesizeandelectricalpropertiesoftheinterconnectsarereportedin Fig.83.Themetalpitchisfollowingthelithography,buttheinterconnectthicknessisnot reducedwiththesametrend.Thecrosssectionoftheinterconnectisreduced,leadingtoa higher resistance per length unit. Starting at 0.18 m, one could replace aluminum by copperduetothelowerresistivityofthelatteranditsmuchgreaterabilitytodrivehigh currents.
Technology Metal layers Lower metal Pitch(m) 1.2m 0.7m 0.5m 0.35m 0.25m 0.18m 0.12m 2 2 3 5 6 6 7 1.8 1.2 0.75 0.6 0.45 0.3 0.22 Upper metal Pitch(m) 2.4 1.6 1.25 1.2 0.9 0.6 0.5 Thickness metal (m) 1.2 1.1 1.0 1.0 0.9 0.8 0.7 Static Resistance (ohm/sq) 0.025 0.025 0.04 0.05 0.06 0.07 0.08 Alu,Sio2 Alu,Sio2 Alu,SiO2 Tu,Alu,SiO2 Tu,Alu,Sio2 Tu,Cu,SiO2 Tu,Cu,SiO2 cmos12.rul cmos07.rul cmos05.rul cmos035.rul cmos025.rul cmos018.rul cmos012.rul Interconnect Materials Microwindfile

Fig.83:Technologicaltrendsforinterconnects

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MICROWIND1.086

Design Rules
Thesoftwarecanhandlevarioustechnologies.Theprocessparametersarestoredinfiles withtheappendix'.RUL'.ThedefaulttechnologycorrespondstotheATMELES22metal 0.8mCMOSprocess.ThedefaultfileisES208.RUL. To select a foundry, click on File > Select Foundry and choose the appropriate technologyinthelist. NWell

r101 nwell

r102 psubstrate nwell

r101 r102 Diffusion r201 r202 r203 r204

Minimumwellsize:12 Betweenwells:12

Minimumdiffusionsize:4 Betweentwodiffusions:4 Extrawellafterdiffusion:6 Betweendiffusionandwell:6

r203

P+diff

r202

P+diff

r201 r204

nwell

N+diff

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MICROWIND1.087

Polysilicon r301 r302 r303 r304 r305 r306 r307 Polysiliconwidth:2 Polysilicongateondiffn+:2 Polysilicongateondiffp+:2 Betweentwopolysilicons:3 Polyv.sotherdiffdiffusion:2 Diffusionafterpolysilicon:4 ExtensionofPolyafterdiff:2

r305

P+diff r302 r304 r306 nwell

r301

N+diff r307

r306

Contact r401 r402 r403 r404 r405 Contactwidth:2 Betweentwocontacts:3 Extrametalovercontact:2 Extrapolyovercontact:2 Extradiffovercontact:2

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MICROWIND1.088 r403 r402 metal r404

r401 r405

contact

N+diff

poly

Metal1 r501 r502 Metalwidth:3 Betweentwometals:3

r501 metal r502 metal

Via r601 r602 r603 r604 r605 Viawidth:3 BetweentwoVia:3 BetweenViaandcontact:3 Extrametalovervia:2 Extrametal2overvia:2
r604 r602 via r601 r603 contact metal2

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MICROWIND1.089

Metal2 r701 r702 Metalwidth:5 Betweentwometal2:5

r701 metal2 r702 metal2

Via2 r801 r802 r803 r804 Metal3 r901 r902 Metal3width:6 Betweentwometal3s:5 Via2width:3 BetweentwoVia2s:4 BetweenVia2andvia:4 Extrametal2&metal3overvia2:3

Via3 ra01 ra02 ra03 ra04 Via3width:4 BetweentwoVia3s:6 BetweenVia3andvia2:6 Extrametal4andmetal3overvia3:6

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MICROWIND1.090

Metal4 rb01 rb02 Metal4width:10 Betweentwometal4s:22

Via4 rc01 rc02 rc03 rc04 Via4width:4 BetweentwoVia4s:6 BetweenVia4andVia3:6 Extrametal4&metal5overvia4:6

rc02 via4 rc01 rc03 Via3 metal5&metal4

rc04

Metal5 rd01 rd02 Metal5width:10 Betweentwometal5s:22

rd01 metal5 rd02 metal5

Pads rp01 rp02 rp03 rp04 rp05 Padwidth:100m(lambdaconversiondependingonthetechnology) Betweentwopads100m Openinginpassivationv.svia:5m Openinginpassivationv.smetals:5m Betweenpadandunrelatedactivearea:20m

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MICROWIND1.091

rp03 PAD

rp02

rp01

Parasistic Capacitors
EachdepositedlayerisseparatedfromthesubstratebyaSiO2oxideandgeneratedbya parasiticcapacitor.TheunitistheaF/m2(atto=1018).Polysilicon,MetalandMetal2 generateparasiticcapacitors.Diffusedlayersgeneratejunctioncapacitors(N+/P,P+/N). ThelistofcapacitanceshandledbyMICROWINDisgivenbelow. ThenamecorrespondtothecodenameusedinES208.RUL.
NAME DESCRIPTION VALUE CMEBody CMEPoly CM2Body CM3Body CM4Body CM5Body CM2Poly CM2Metal CPOOxyde CPOBody CDNDiffp CDPDiffn CLDn CLDp Metalonthickoxidetosubstrate Metalonpolysilicon Metal2onthickoxide Metal3onthickoxide Metal4onthickoxide Metal5onthickoxide Metal2onpolysilicon Metal2onmetal Polygate Polyonfieldoxide JunctiondiodeDiffninpwell,surface JunctiondiodeDiffpinnwell,surface JunctiondiodeDiffninpwell,lineic JunctiondiodeDiffpinnwell,lineic 17aF/m2 50 13 15 13 10 25 45 1500 60 420 350 260aF/m 310aF/m

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MICROWIND1.092

Design Rule File

AnexampleofdesignrulefileES208.RUL(ATMELES20.8mtechnology)isgivenbelow.
MICROWIND v1.00 * * Rule file for * Atmel ES2 0.7m * CMOS 2-metal * * 23 Fev 97 by Etienne Sicard * Modified : 6-Jun-97 Res,thick,GDS2, CIF * : 9-Jun-97 Metal,metal2 capas * * NAME Atmel-ES2 0.7m - 2 Metal * lambda = 0.4 (Lambda is set to half the gate size) metalLayers = 2 (Number of metal layers : 5) * * Design rules associated to each layer * * Well (1) r101 = 10 (well width) r102 = 10 (well spacing) * * Diffusion (12,14) * r201 = 4 (diffusion width) r202 = 4 (diffusion spacing) r203 = 6 (border of nwell on diffp) r204 = 6 (nwell to next diffn) r205 = 5 (diffn to diffp) * Poly (11) r301 = 2 (poly width) r302 = 2 (ngate width) r303 = 2 (pgate width) r304 = 3 (poly spacing) r305 = 1 (spacing poly and unrelated diff) r306 = 4 (width of drain and source diff) r307 = 2 (extra gate poly) * Contact (16) r401 = 2 (contact width) r402 = 3 (contact spacing) r403 = 2 (metal border for contact) r404 = 2 (poly border for contact) r405 = 2 (diff border for contact) * Metal (17) r501 = 3 (metal width) r502 = 3 (metal spacing) * Via (18) r601 = 3 (Via width) r602 = 3 (Spacing) r603 = 3 (To unrelated contact) r604 = 2 (border of metal&metal2) * metal 2 (19) r701 = 3 (Metal 2 width) r702 = 3 (spacing) * * Pads (Passiv is 20) * rp01 = 278 (Pad width) rp02 = 278 (Pad spacing) rp03 = 13 (Border of Via for passivation ) rp04 = 13 (Border of metals) rp05 = 63 (to unrelated active areas) * * * Thickness of layers * thpoly = 0.7 hepoly = 0.5 thme = 0.8 heme = 1.1 thm2 = 1.2 hem2 = 2.0 thpass = 1.0 hepass = 3.0 thnit = 0.5 henit = 4.0 * * Resistance (ohm / square) * repo = 25 reme = 0.075 rem2 = 0.040 * * Parasitic capacitances * cpoOxyde = 2300 (Surface capacitance Poly/Thin oxyde aF/m2) cpobody = 53 (Poly/Body) cmebody = 44 cmelineic = 12 (aF/m) cmepoly = 52 cm2body = 56 cm2lineic = 10 (aF/m) cm2poly = 44 cm2metal = 84 * * Crosstalk * cmextk = 50 (Lineic capacitance for crosstalk coupling in aF/m) cm2xtk = 80 (C is computed using Cx=cmextk*l/spacing) * * Junction capacitances * cdnpwell = 520 (n+/psub) cdpnwell = 600 (p+/nwell) cnwell = 100 (nwell/psub) cpwell = 100 (pwell/nsub) cldn = 310 (Lineic capacitance N+/P- aF/m) cldp = 820 (Idem for P+/N-) * * Nmos Model 3 parameters * NMOS l3vto = 0.8 l3vmax = 130e3 l3gamma = 0.4 l3theta = 0.2 l3kappa = 0.01 l3phi = 0.7 l3ld = -0.05 l3kp = 135e-6 l3nss = 0.07 * * Pmos Model 3 * PMOS l3vto = -1.1 l3vmax = 100e3 l3gamma = 0.4 l3theta = 0.2 l3kappa = 0.01 l3phi = 0.7 l3ld = -0.05 l3kp = 47e-6 l3nss = 0.07 * * MicroWind simulation parameters *

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MICROWIND1.093
deltaT = 4.0e-12 (Minimum simulation interval dT) vdd = 5.0 temperature = 27 * * CIF&GDS2 * MicroWind name, Cif name, Gds2 n, overetch for final translation * cif nwell CNWI 1 0.0 cif aarea CTOX 2 1.0 cif poly CPOL 11 0.0 cif diffn CNPI 12 1.0 cif diffp CPPI 14 1.0 cif contact CCON 16 0.1 cif metal CME1 17 0.0 cif via CVIA 18 -0.1 cif metal2 CME2 19 0.0 cif passiv CPAS 20 0.0 cif text text 0 0.0 * * End atmel-ES2 0.7m *

93

8.ProgramOperation

Getting Started
TogetyourMICROWINDprogramstarted,usethefollowingprocedure: InserttheMICROWINDdisketteintodrivea: UnderWindows95/NT,clickonStart>Execute Typea:installandpress CreateashortcuttotheexecutablefileMicrowindanddoubleclickonitto startthesoftware

ThesoftwarerunsonlyonWindows95orWindowsNT. NOTICE:Thecommandlinemayincludetwoparameters: 1. TheFirstparameteristhedefaultmaskfileloadedatinitialization 2. TheSecondparameteristhedesignrulefileloadedatinitialization Example: Thecommandmicrowindfaddams06.rulexecutesMICROWINDwithadefault maskfilefadd.MSKandtherulefileams06.RUL.

9.Commands

Copy ClickontheCopyicon.Movethecursortothedesignwindow,anddelimittheactivearea with the mouse. Consequently, all the graphics included in this area are copied. The externalshapeofthecopiedelementsappear.Fixthosecopiedelementsatthedesired locationbyaclickonthemouse. ClickonUndotocancelthecopycommand.

Cut ClickontheCuticon.Movethecursortothedesignwindow,anddelimittheactivearea withthemouse.Consequently,allthegraphicsincludedinthisareaareerased.Clickon Undotofixthoseelementsbackintothedesign. u Alayerisprotectedfromerasingifyouremovethetickinthepalettetwice.Inthe palette,anemptysquaretotherightofthelayerindicatesaprotectedlayer. Alayerisunprotectedfromerasingifyouselectitagaininthepalette.Atickinthe squaretotherightofthelayerindicatesanunprotectedlayer. Onebox only canbeerasedbyaclickinsidethatboxwhenthecutcommandis active.Theboxisthenerased.

SeeMovetomoveoneboxoragroupofboxes.

SeeStretchtostretchabox. CifOut MICROWINDconvertstheMSKlayoutintoCIFusingaspecificinterface.TheCIFfilecan beexportedtovariousindustrialsoftware.Thescreenisshownbelow.Therighttable givesthecorrespondencebetweenMICROWINDlayersandCIFlayers,thenumberof boxesinthelayoutandthecorrespondingoveretch.Theoveretchisusedtomodifythe finalsizeoftheCIFboxesinordertofittheexactdesignrules. ClickonConverttoCIFtostartconversion.Somepartsoftheresultappearintheleft window.

CompileoneLine ThecellcompilerisaspecifictooldesignedfortheautomaticcreationofCMOScellsfrom logicdescription.ClickonCompile>CompileOneLine.Themenubelowappears.The defaultequationcorrespondstoa3inputNORgate.Ifneedonecanusethekeyboardin ordertomodifytheequationandthenclickon Compile.Thegateiscompiledandits correspondinglayoutisgenerated.

Thefirstitemoftheonelinesyntaxcorrespondstotheoutputname.Thelatterisfollowed bythesign=,theoptionalsignnot/,andbythelistofinputnamesseparatedby theoperatorsAND.orOR..Ifneedbe,parenthesiscanbeadded.Theinputand outputnamesare8characterstringsmaximum. Thetablebelowshowsdifferentexamplesofcellformulas: COMPILERSYNTAX CELL F ORMULA Inverter out=/in NANDgate n=/(a.b) ANDgate s=(a.b) 3InputOR s=a+b+c 3InputNAND out=/(a.b.c) ANDORGate cgate=a.(b+c) CARRYCell cout=(a.b)+(cin.(a+b)) TRANSISTORSIZE.Thedefaultdevicesizeisgivenbythedesignrules.Youmaychange thenMOSandpMOSwidthintheoptionmenubeforeclickingonPILE. IMPLEMENTATION.Thepchanneltransistorsarelocatedonthetopofthenchannel transistornet.Ifsomelayoutalreadyexistsnearthoseicons,thecelloriginismovedtothe rightuntilenoughfreespaceisfound.Ifthe'/'operatorhasnotbeenspecifiedafterthe'=' sign,aninverterisaddedattherighthandsideofthecompiledcell.ThatiswhyanAND gateiscompiledasaNANDgatefollowedbyaninverter. CompileaVERILOGdescription The cell compiler can handle layout generations from a primitivebased VERILOG descriptiontextintoalayoutformautomatically.Clickon Compile> CompileVerilog File.SelectaVERILOGtextfileandclickonOK.Forinstance,the microwind directory containstheHADD.TXTfilewhichcorrespondstothedescriptionofahalfadder.

Themenubelowappears. Ifneedbemodifythetransistorsizingandclickon Compile. TheVERILOGtextiscompiledintoasetofbasicgatesanditscorrespondinglayoutis generated.

DesignRuleChecker

Thedesignrulechecker (DRC)scansallthedesignandverifiesthatalltheminimum designrulesarerespected.Clickontheiconaboveoron Analysis>DesignRuleChecker toruntheDRC.Theerrorsarehighlightedinthedisplaywindow,withanappropriate messagegivingthenatureoftheerror.Detailsaboutthepositionandtypeoftheerrors appearonthescreen.

Toobtainanyfurtherinformationaboutthedesignrules,seeChapter8.

DrawaBox

TheDrawBoxiconisthedefaulticon.Itcreatesaboxintheselectedlayer.Thedefault layerisPoly.IftheDrawBoxiconisnotselected,clickonit.Then,movethecursorto thedisplaywindowandfixthefirstcorneroftheboxwithapressofthemouse.Keep pressedanddragthemousetotheoppositecornerofthebox.Releasethemouseandsee howtheboxiscreated. Theactivelayerisselectedinthepalette.Theredcolorindicatestheactivelayer.Thetick specifiesthatallboxesusingthelayercanbeerased,stretchedorcopied.Removingthe tickprotectsthelayer. DuplicateXY

ThecommandDuplicateXYisveryusefultogenerateanarrayofidenticalcellssuch as RAM cells for example. Click on Edit > Duplicate XY, include the elements to duplicateinanareadefinedbythemouse,andthefollowingscreenappears.InbothX andY,thedefaultmultiplicationfactorisx2.Youmayadjustthespacebetweencells.By default,thecellstoucheachother.

ExtractOptions Theextractionoptionsaredetailedinthemenubelow.Thedefaultextractionincludesthe removal of redundant boxes (Purge) and the removal of overlaps (Merge). The fast extractiondoesnothandlePurgenorMergeoperations. TheMOSlevelcanbechosenbetweenlevel1and3.Seechapter2formoredetailsabout thosemodels. Other options concern the computation of lateral capacitances and vertical crosstalk capacitances.

FloatingNode Clickon Analysis>FloatingNodes toscanthelayoutanddetectnodesthatmightbe floating.ThenavigatorgivesthelistofthefloatingnodesintheNavigatormenu.Clickon thecorrespondingnametolocateitinthedrawing.Afloatingnodeisaninterconnectnot connectedtoadiffusion.Floatinggatesarelistedeveniftheyincludeaclockorpulse property.

Foundry ClickonFile>SelectFoundry.Thelistofavailableprocessesappears.Thedefaultdesign rulefileiswritteninboldcharacters.Varioustechnologiesareavailablefrom1.2downto 0.12m.Clickontherulefilenameandthesoftwarereconfiguresitselfinordertoadapt tothenewprocess. Hardcopy ClickonFile>PrintLayouttotransferthegraphicalcontentsofthescreentotheprinter. Youcanmakeacopyofthewindowintotheclipboardinordertoimportthescreeninto yourfavoritetexteditorbypressing<Alt>+<PrintScreen>.Inthetexteditororinthe graphic editor, simply click on Edit >Paste We recommend that you switch to monochromemodefirstbyinvokingthefunction File>Monochrom/Color.Inthatcase thelayoutwillbedrawninawhitebackgroundcolorusinggraylevelsandpatterns. Library

Thelibrarycontainsasetofpredefinedlayoutmacrossuchascontacts,devicesandpads. Thosecellsarebuiltaccordingtodesignrules,andcontainsizeparameters.Toinvokethe celllibraryclickontheaboveicon.

CONTACTS.Contactssuchaspolysilicon/metal,ndiffusion/metal,pdiffusion/metal andmetal/metal2metal2/Metal3,(etc..)canbeobtainedhere.Youmayalsorepeata numberofcontactsinXandY.Youmayalsogenerateapolarizationsealaroundthe contacttocreateapaddiodeprotectionforexample. ClickonGenerateContact.Theoutlineofthelatterappears.Thenclickonthemouseto setthisoutlineintheappropriateplace.

MOS.Thismacrogenerateseitheranchannelorapchanneltransistor.Theparameters ofthecellarethechannellength(defaultvalueisgivenbythedesignrules),itswidth, and the number of gates. Once those parameters are defined, the device outline appears.Clickonthemousetoplaceitintheappropriateplace.

PADS.Itispossibletoaddvariousitemssuchasasinglepad,atestpad(usually30x30 m),orevenasetofpadsallaroundandtothelayoutusingtheVDDandVSSpower rings.Inthelastcase(addingmorethanonepad),givethenumberofpadseachsideof thechipandifneedbemodifythewidthoftheVDDandVSStracks.

ROUTING.Thiscommandisusedtoroutinterconnectsinonemetallayer(metal1by default)forhorizontaltracksandinanothermetallayer(metal2bydefault)forvertical tracks.Theappropriatecontactisgeneratedautomatically.Thiscommandisvery usefulforcellroutingusingtwodifferentmetallayers.

PATH.ThiscommandissimilartotheROUTINGcommandbutitconsidersonlyone layer.Thepathwidthcanbechanged,aswellasthealignmenttotheroutinggrid.A setofcontactscanalsobeplacedatbothendsofthepath.Thiscommandisveryuseful forVDDandVSSsupplydrawingandsinglelayerinterconnects.

BUS.Thiscommandgeneratesasetofparallellineswithuserdefinedlayer,widthand spacing.Thiscommandisusefultobuildthefinalroutingofachip.

Measuredistance:Seeruler MOSdevice

Clickontheicon.TheId/VdcurveofthedefaultMOS(W=20m,L=Lminimum)appears. YoucanskiptoId/Vgmodetohighlightthethresholdvoltage,ortoId(log)/Vgtosee thesubthresholdbehavior.Youmayaddmeasurementsbyselectinga.MESfilethen skipfromNMOStoPMOSandselectthesizeofthedeviceinthelowermenu. Twomodelscanbeused: MOSModel1(BerkeleySpice) MOSModel3(SimplifiedversionofBerkeleySpice) Theeffectsofthechangingofthemodelparameterscanbeseendirectlyonthescreenbya clickonthelittlearrowswhichchangetheparametervalues. Also,theverticalscalecanbealtered,aswellassomeconfigurationparameters.

Measurements ClickonView>Measurementstoloadsomemeasurementstogetherwiththesimulations intheI/Vwindowproposedabove.ThiscommandisashortcuttothebuttonAdd MeasurementoftheMOScharacteristicswindow.

MoveaBox

Tomoveonebox,clickontheaboveicon.Usingthemouse,createanareawhichincludes thebox.Then,dragthemousetothenewlocationandreleasethemouse.Asaresult,the boxhasbeenmovedthenewplace.Repeatthesameinordertomoveasetofboxes.To protectalayerfrommoving,clickintherectanglethepalettethatissituatedontheright sideofthelayer.Thiswillremovethetick. File>New Clickon File> New inordertorestartthesoftwarewithanemptyscreen.Thecurrent designshouldbesavedbeforeassertingthiscommand,asallthegraphicinformationwill bephysicallyremovedfromthecomputermemory.No Undo isavailabletodisablethe Newcommand. File>Open Clickontheicon .Inthelist,doubleclickonthefiletoload..MSKisthedefault extensionthatcorrespondstothelayoutfiles.TheCIFfiles.CIFcanalsobeloaded.The appropriateconversionprogramtransformstheinputCIFintoMSKformat. File>Insert ThecommandFile>InsertisusedtoaddaMSKfiletotheexistingfiles.Theinserted layoutisfixedattherightlowersideoftheexistinglayout.Thecurrentfilenameremains unchanged.

File>Statistics

ThecommandFile>Statisticsprovidessomeinformationaboutthecurrenttechnology, thepercentageofmemoryusedbythelayoutandthesizeofthelayoutplusitsdetailed contents.Ifthelayouthaspreviouslybeenextractedorifyouclickextractnow,the numberofdevicesandnodeswillbeupdated.

ViewNode

Clickontheiconaboveoron View>ViewNode.Then,clickinthedesiredboxinthe layout.Afteranextractionprocedurehasbeencarriedout,youwillseethatalltheboxes connectedtothatnode.Inthecaseofalargelayout,thecommandmaytaketime.The associatedparasiticcapacitanceandthelistoftextlabelsaddedtotheselectedboxesare alsodisplayedinaspecificwindow. Click<Escape>orView>UnselectAlltounselectthelayout.

ViewInterconnect ThecommandView>ViewInterconnectperformsanelectricalextractionofthemetal and polysilicon boxes connected to the desired point. Compared to View Node, this commandworksfasterbutdoesnotconsiderdiffusedlayersthatcanextendthenode interconnectnetwork.Thecommandgivesthelistofconnectedtextlabels. Clickon<Escape>oronView>UnselectAlltounselectthelayout. Palette

Thepaletteislocatedontherightsideofthescreen.Alittletickindicatesthecurrent layer.Theselectedlayerbydefaultisapolysilicon(PO).Thelistoflayersisgivenbelow. Ifyouremovethetickontherightsideofthelayer,thelayerisswitchedtoprotected mode.TheCut,StretchandCopycommandsnolongeraffect thatlayer.Ifthetickis present,thelayerisunprotected.

View>ProcessAspect

Clickontheaboveicontoaccessprocesssimulation.Amouseoperatedlineisgivenand embodiesthecrosssection.Thearrowscanbeusedtomovethecrosssectiontotheright ortotheleftintheXaxis,andforwardandbackwardintheYaxis.

PspiceFile ClickonFile>PspiceFiletotranslateyourdesignintoaPSPICEcompatibledescription. Thecircuitextractorincludedinthesoftwaregeneratestheequivalentcircuitdiagramof thelayoutandaspicecompatiblenetlistreadytobesimulated.Youmayselectthemodel youwillbeusingforsimulation.Thechoiceliesbetweenmodel1andmodel3.

TheSPICEdescriptionincludesthelistofnchannelandpchanneltransistorsandtheir associatedwidth&length extractedfromthelayout.Thetextfilealsodetailsthenode names,parasiticcapacitances,anddevicemodels.TheSPICEfilenamecorrespondstothe currentfilenamewiththeappendix.CIR. LeaveMicrowind ClickonFile>LeaveMicrowind inthemainmenu.Ifyouhavemadeadesignorifyou havemodifiedsomedata,youwillbeaskedtosaveit.Afterconfirmation,youcanreturn toWindows.

Open ClickonFile>Openinthemainmenu.Thelistoflayoutdescriptionfilesappears.Click insidethefilenametoloadit. ParametricAnalysis Before running the parametric analysis, you should run a simulation first. Select the desired output node on which the delay measurement or frequency measurement is performed,thenclickonAnalysis>ParametricAnalysis.Clickonacelloutputnodein the layout. Thewindow below appears. Theparametric analyzer allowsyouto easily investigatetheinfluenceofvariousparametersonthecellperformance.

Intheparametermenu,youmayinvestigatetheinfluenceoftemperature, powersupplyorthatofanodecapacitance. Inthemeasurementmenuyoumaychoosetomonitortheriseandfalldelay, thepowerconsumption,orthefrequency. ClickonStartAnalysis.Aniterativeprocedurewillconductsimulationsand extracttherelevantparameters.Theresultbelowshowstheevolutionofthecell delaywhenitsoutputnodecapacitancehasbeenchanged.Noticethatforhigh capacitancevalues,thecellresponseisveryslow.Theinputclockparameters shouldbeconsequentlybeadjustedinordertofitwithlowspeeds.

RotateandFlip Toapplyarotationorafliptoonepartofthedesign,clickon Edit>RotateoronFlip< >.Delimittheactiveareaoftheboxesinthelayoutsothatitcanbemodifiedusingthe mouse. Save Click on File > Save to save the layout with its current name. The default name is EXAMPLE.MSK.

SaveAs Anewwindowappears,intowhichyouaretoenterthedesignname.Usethekeyboard andtypethedesiredfilename.PressSave.Yourdesignisnowregisteredwithinthe .MSKappendix.

Ruler Therulergivestheverticalandhorizontalmeasurementsdirectlyonthescreeninlambda andinmicron.TherulerissimplyerasedbythecommandView>ViewSameorbya pressof<ESC>.

SearchText Themostconvenientwaytofindatextinthelayoutistoinvoke Edit>Searchtext.The listoftextlabelsappearsinthenavigatormenu.Ifyouclickonthedesiredtext,thescreen isredrawnsothatthetextlabelisatthecenterofthewindow,withtwolinesdrawinga crossatthetextlocation.Itspropertiesappearinthenavigatormenu.

ClickonHidetoclosethenavigatorwindow.ClickonExtracttoaddtheelectrical propertiesoftheselectedtextifthelayouthasnotbeenpreviouslyextracted. NOTE:Inthecaseofaverylongtextlist,selectthefirstletterofthetextathand,press thatletteronthekeyboard.Thiswillautomaticallyeffectandalphabeticresearchandthe selectorwillmovetothefirstlabelstartingwiththeselectedletter. Simulate

TheaboveiconorthecommandSimulate>StartSimulationbothgiveaccesstothe automaticextractionandanalogsimulationofthelayout.

SimulationIcons Thesimulationiconsadd properties tothenodes. Propertiesareappliedtotheelectric nodesofthecircuitinordertoserveassimulationguides.Youmustspecifywhichnodeis assignedtowhichvoltagebeforestartingtheanalogsimulation.

VDD property VSS property Clock property Node visible Pulse property

VDD&VSS.Thenodeispushedtothepowersupplyvoltage(usually5V)icon Vdd, andpulledtotheground0VwithiconVss. CLOCK.Whenanodebecomesaclock,theparametersofthelatteraredividedas follows:risetime,levelone,falltime,andlevelzero.Allvaluesareexpressedinnan second(ns).Ifyouaskforasecondclock,theperiodwillbemultipliedbytwo.You mayalter level0 and level1 usingthekeyboard.Togenerateaclockstartingfrom VDDinsteadofVSS,clickon InvertL/H.UsePeriod*2tomultiplytheclockperiodby two.UsePeriod/2todividetheclockperiodbytwo. PULSE.Thepositiveimpulseappearsafteragivendelay,getsarisetime,thenstaysat leveloneforanotherdelay,anddropstozerowithafalltime.Ifyouaskforanother impulse , the initial delay is increased. The negative impulse can be obtained by invertingthevoltagevaluesoflevelsoneandzero. VISIBLENODE.Clickon andclickontheexistingtextinthelayouttomakethe chronogramsofthenodeappear.Initially,allnodesareinvisible,buttheclocksand impulsenodesaresubsequentlymadevisible.

Text Usethisicontofixatexttooneboxorlocationinthedesign.Thattextillustratesthe layoutandshouldbeusedasmuchaspossibleforeachsignificantnodesuchasinputs andoutputs.Clickontheicon,clickthedesiredlocationinthelayout,enterthetext usingthekeyboardandpress.Thetextisfixedintheappropriateplace.

SimulationMenu Thesimulationmenucontainsalistofbuttonswhichgiveaccesstosimulation parameters.Thelistofoptionsisdetailedbelow.

Select the node from which the delay counter is started at each crossing of VDD/2 The delay counter is stopped at each crossing of VDD/2 and the delay is drawn The minimum and maximum voltage of the selected node are displayed. At each period of the selected node, the frequency is displayed More simulation Restart simulation from time 0 Select the time scale within a list in the menu

Select the time interval between two simulation steps. Stop simulation. A second click and you are back to the editor

NOTE:Youcanmodifytheminimumsimulationstep t,butitmaybedangerous.Ifyou increase tthesimulationspeedimprovesbutthenumericalerrormayleadtounstable simulations.Ifyoudecrease t,thesimulationspeedisdecreasedtoobutthenumerical precisionisimproved.Theriskofcomputingdivergenceisreduced.

Voltagevs.time

ClickonVoltagevsTimetoobtainthetransientanalysisofall visiblesignals.Thedelaybetweentheselected startnode and selectedstopnodeiscomputedatVDD/2.Youcanchangethe selectedstartnodeinthenodelist,intherightuppermenuof thewindow.Youcandothesamefortheselectedstopnode.

VoltageandCurrents

ClickonVoltageandCurrentssoastomakeallvoltagecurves appearinthelowerwindow,andtheVDD,theVSSandthe desired MOScurrentsappear intheupper window. In that mode, the dissipated power within the simulation is also displayed.

Voltagevs.Voltage

Clickon Voltagevs.Voltage toobtaintransfercharacteristics betweentheXaxisselectednodeandtheYaxisselectednode. Initiallythestartnodeisthefirstclockorpulseofthenodelist, andthestopnodeisthefirstvaryingnode.Youcanchangethe XaxisandYaxisnodesintheselectionmenu This mode is useful for the computing of the Inverter characteristicsandfortheexhibitingofthecommutationpoint. It also allows the operational amplifier to draw the DC responseandtocheckupthegain.Finally,itisalsousefulfor theSchmitttriggertoseethehysteresisphenomenon. Thefirstsimulationcomputesthevalueofthe stopnode for start node varying from 0 to VDD. The second click on Simulate computes the same for start node varying from VDDto0.

Stretch&Move Toincreasethesizeofonebox,clickonthe ResizeIcon.Thenclickontheborderofthe box.Dragthemousetothenewlocationandreleasethemouse.Theboxisresized. Ifyoudefineanareawhichincludes someboxesortext,youareinmovemode.The elementsdisappear,andarereplacedbytheirbondingbox.Clickonthenewlocationto movethoseelements. Text Sometextcanbeaddedtoanyboxinsidethedesign.Thetextisautomaticallypropagated totheelectricalnodeattachedtoit.Toaddsometexttoaparticularplace,proceedas follows: Clickontheicon

Setthetextlocationwiththemouse.Adialogboxappears EnterthetextandpressOK.Thetextissetinthedrawing .Thenclickinsidetheexistingtext.Theold

Atextcanbemodifiedasfollows:clickon textappears.ModifyitandclickonOK. Undo

Donottakeintoaccountthelasteditingcommand.Itispossibletoundothecommands Cut,Paste,Copy,Move,Stretch,EditandCompile. UnselectAll

ClickonView>UnselectAll(or<ESC>)tounselectthelayout.Thiscommandisuseful todrawthelayoutbackintoitsdefaultcolorsaftercommandssuchas ViewInterconnect orViewNodewhichhighlightonesinglenode. ViewAll

Click View>ViewAll tofitthescreen withallthegraphicalelements currently on display.

ZoomIn&Out ThoseiconsperformZoomInandZoomOut.Whenzoomingin,theareadeterminedby the mouse will be enlarged to fit the display window. When zooming out, the area determinedbythemousewillcontainthedisplaywindow. Ifyouclickonce,azoomisperformedatthedesiredlocation. ClickCtrl+AforViewAll,andCtrl+oforzoomout.

10.QuickReferenceSheet

FILEMENU
Reset the program and start with a clean screen Read a layout data file Insert a layout in the current layout Translates the layout into CIF Save the layout Switch to monochrom/Color mode Access to the list of foundries (*.RUL) Layout properties : number of box, devices, size Quit Microwind and returns to Windows 95

Extract the electrical circuit and translates into SPICE

Print the layout

VIEWMENU

Unselect all layers and redraw the layout Fit the window with all the edited layout Redraw the screen

Zoom In, Zoom out the layout window Access to the measured I/V

Protect all layers from modifications Extract the electrical node starting at the cursor location Extract the node propagating on metal interconnects

View the 2D crosssection of the layout

SIMULATEMENU

Extract the electrical circuit an run the simulation Access to the single MOS characteristics in DC, model parameters and measurements Select MOS model, gain access to parameters

Access to the SPICE model and some extraction options : layout cleaning, handle lateral coupling ... Extract the electrical network and make a SPICE file

Remove redundant boxes, clean the data base

ANALYSISMENU

Verifies the layout and highlight the design rule violations Gives the list of nodes not connected to diffusion layers Shows the navigator menu Computes the effects of VDD, t, capacitance on delay, freq, etc...

PALETTE(

LISTOFICONS SeePage OpenalayoutfileMSK SavethelayoutfileinMSKformat Drawaboxusingtheselectedlayerofthepalette Deleteboxesortext. Copyboxesortext Stretchormoveelements ZoomIn ZoomOut Viewallthedrawing

Extractandviewtheelectricalnodepointedbythecursor Extractandsimulatethecircuit Measurethedistanceinlambdaandmicronbetweentwopoints 2Dverticalaspectofthedevice Designrulecheckingofthecircuit.Errorsarenotifiedinthelayout. Addatexttothelayout.Thetextmayincludesimulationproperties. Chiplibraryofcontacts,MOS,metalpath,2metalrouting,pads,etc... Viewthepalette StaticMOScharacteristics

LISTOFFILES

PROGRAM DESCRIPTION MICROWIND.EXE LayoutEditorandSimulator *.RUL Designrulefiles *.MSK Layoutfiles *.MES MOSI/VMeasurements *.CIR Spicecompatiblefiles *.TXT Verilogtextinputs *.RUL TheMICROWINDprogramreadstherulefiletoupdatethe simulatorparameters(Vt,K,VDD,etc...),thedesignrulesand parasiticcapacitorvalues.Adetaileddescriptionofthe.RUL fileisreportedattheendofChapter8. The MICROWIND software creates data files with the appendix.MSK.Thosefilesaresimpletextfilescontainingthe listofboxesandlayers,andthelistoftextdeclarations.The3D modulecansimulatethefabricationprocessofany.MSKfile. The MICROWIND program generates a SPICE compatible descriptionfilewhenthecommandFile>MakeSPICEFileis invoked.Forexample,ifthecurrent fileis MYTEST.MSK,a text file MYTEST.CIR is generated and contains the list of transistors,capacitorsandvoltagesourcescorrespondingtothe drawing,inSPICEcompatibleformat.

*.MSK

*.CIR

11.Instructor'sGuide

TUTORIALONMOS(1H) TheMicrowindprogrammaybeusedforabeginningelectronicsclasstodesignasingle MOS,toaddclocksandseehowtheMOSdeviceisturnedonoroff.Studentsshouldhave timetolookbothatthecrosssectionofthetransistorandtheI/Vcharacteristics. Possiblequestionstoaskstudentsincludethefollowing: Giveanapproximationofthethresholdvoltage.Itshouldbe0.75V. FindthemaximumcurrentIdsavailable.Itshouldbearound1mA. Modifythewidth(4>8)andfindthenewIdsmaximum.Itshouldbetwice aswideasthepreviousone,becauseofthelawIds=W/L(...). Modifythetemperature.Itisnotobviousthatalowertemperaturemakesthe devicerunfaster.Manystudentstendtothinktheoppositeway. DESIGNOFCMOSCELLS(16H) Itwilltakeabout16hourstocoverthedesignandsimulationsofaninverter,alogicgate, acomplexgate,anarithmeticcircuit,anamplifierandaconverter.Thisprogramallows studentstodesignandsimulateanIC. SwitchtothesimulationofthepchannelMOS.Pointouttheproblemofthe reducedmobility(n=500cm/V.s,p=250cm/V.s).

Althoughaveryuserfriendlyandhighlyintuitiveprogram,studentsshouldnevertheless learnitsbasiswithaninstructor.Threefourhoursessionsshouldbesufficienttolearn aboutthispackageanduseit.Werecommendthefollowingprocedure: ConductastepbystepmanualdesignoftheinverterasshowninChapter3.This providesthestudentwithagoodintroductiontothebasiccommandssuchas: DrawaBox EraseoneBox Changealayer Addtext AddVDD,VSSoraCLOCK Simulate Write

Simulateyourinverter.MinorproblemsmayoccuriftheVDDandVSSbusesare notcorrectlypolarized.Makearingoscillatorandobservetheresulting frequency.

UsetheDSCHlogiceditortodesignaschematicdiagram.Verifyitslogic behavior.ClickonMakeVerilogFileandsavethefile.Thencompilethe VERILOGtextfileusingtheMicrowindcommandCompileVerilog.Add clockpropertiesandverifythecorrectanalogbehaviorofthecell.

Conductarithmetic,latchoranalogcellprojectsorprojectssuchas: SchmittTrigger Multiplier Follower Shiftregister Oscillator Memorycell

Notes