BAO CAO CHUYEN E

e Tai:

HAI GII THUT NG NGT PWM IU CH P CAO V P THP CHO SPARSE MATRIX CONVERTER

Hng dan : PGS.TS Nguyen Van Nh Thc hien : Tran Vu

NI DUNG TRNH BY
CU TRC V 2 GII THUT IU KHIN NG NGT CA SPARSE MATRIX 9 KHA KT QU M PHNG S DNG CC KHI XILINX BLOCKSET KT QU THC NGHIM CA SPARSE MATRIX

NI DUNG TRNH BY
CU TRC V 2 GII THUT IU KHIN NG NGT CA SPARSE MATRIX 9 KHA 1.1 Phng php PWM th 1 cho tng chnh lu 1.2 Phng php PWM th 2 cho tng chnh lu 1.3 Phng php iu ch vetor khng gian cho tng nghch lu 1.4 Gin phi hp ng ngt ca Sparse Matrix Converter 1.5 H s cng sut u vo ca Sparse Matrix Converter 1.6 Kt lun KT QU M PHNG S DNG CC KHI XILINX BLOCKSET KT QU THC NGHIM CA SPARSE MATRIX

CU TRC CA SPARSE MATRIX CONVERTER 9 KHA

Sparse matrix 9 kha - Cng sut ch chy t ngun ti ti (Udc > 0, idc >0) - Mch kp bo v ca Sparse matrix 9 kha bao gm mt diode Dc v mt t Cc vi mt kha bn dn dc diode cho php nng lng c tr trong t tr ngc v ti

CU TRC CA SPARSE MATRIX CONVERTER 9 KHA

(a) Cc dng mch kp. (a) Mch kp truyn thng

(b) (b) Mch kp t-diode vi kha

(c) (c) Mch kp tch cc

Mch kp - Dng mch kp truyn thng c th c s dng bo v trnh cc gai in p ln gy bi dng cng sut ngc. - Mt dng mch kp khc l dng mch kp tch cc nh hnh (c) trn. Dng mch kp ny kt ni mt in tr cng sut dc theo t thng qua mt kha bn dn c th tiu tn bt c dng cng sut ngc no khi kha bn dn c ng li.

1.1 Phng php PWM th 1 iu ch p cao cho phn chnh lu

p ngun c dng

Su khong chia ca in p ba pha u vo

Dng sng p DC c to ra bi gii thut ng ngt 1

Gi s thi im ly mu nm trong khong [-/6, /6], ln in p pha A l ln nht, kha SA s ng duy tr trong mt chu k v 2 kha cn li SB v SC s ng trong nhng khong sau:

1.1 Phng php PWM th 1 iu ch p cao cho phn chnh lu

Gi tr trung bnh p DC trong mt chu k s l:

Tng qut gi tr trung bnh p DC trong mt chu k s l:

Bng I: Trng thi ng ngt tng chnh lu

Vdc_p Vsa Vsb Vsb Vsc Vsc Vsa Vdc_n Vsc Vsc Vsa Vsa Vsb Vsb Vdc Vac Vbc Vba Vca Vcb Vab ia idc 0 -idc -idc 0 idc ib 0 idc idc 0 -idc -idc ic -idc -idc 0 idc idc 0

1.2 Phng php PWM th 2 iu ch p thp cho phn chnh lu

p ngun c dng

-
6 6 2

5 7 3 11 6 6 2 6

Su khong chia ca in p ba pha u vo

Dng sng p DC c to ra bi gii thut ng ngt 2

Gi s ti thi im ly mu ln in p pha B l nh nht, kha SB s ng duy tr trong mt chu k v 2 kha cn li SA v SC s ng trong nhng khong sau:

1.2 Phng php PWM th 2 iu ch p thp cho phn chnh lu

Gi tr trung bnh p DC trong mt chu k s l:

Tng qut gi tr trung bnh p DC trong mt chu k s l:

1.3 Phng php vector khng gian cho phn nghch lu

uo

Thi gian T1, T2, T0 s c tnh ton khi vector khng gian quay vi in p VDC= 3Vm/2

Tuy nhin gi tr trung bnh in p DC thc s l

Do vy gi tr thi gian T1, T2 s c nhn thm vi h s b cho s chnh lch so vi gi tr thc s ca in p Vdc
Lc gic vector khng gian p u ra

1.3 Phng php vector khng gian cho phn nghch lu

Gi tr thi gian ng ngt phn phi trong khong 1

Gi tr thi gian ng ngt phn phi trong khong 2

Bng II: Trng thi ng ngt tng nghch l u

SAp SAn SBp SBn SCp SCn VA VB VC VAB 1 0 0 1 0 1 Vdc_p Vdc_n Vdc_n Vdc 1 0 1 0 0 1 Vdc_p Vdc_p Vdc_n 0 0 1 1 0 0 1 Vdc_n Vdc_p Vdc_n -Vdc 0 1 1 0 1 0 Vdc_n Vdc_p Vdc_p -Vdc 0 1 0 1 1 0 Vdc_n Vdc_n Vdc_p 0 1 0 0 1 1 0 Vdc_p Vdc_n Vdc_p Vdc 0 1 0 1 0 1 Vdc_n Vdc_n Vdc_n 0 1 0 1 0 1 0 Vdc_p Vdc_p Vdc_p 0 VBC 0 Vdc Vdc 0 -Vdc -Vdc 0 0 VCA -Vdc -Vdc 0 Vdc Vdc 0 0 0 idc iA -iC iB -iA iC -iB 0 0

1.4 Gin phi hp ng ct ca Sparse Matrix

Ts Ts*db Ts*dc

Gin ng ct pha chnh lu

Vab
db d0b +d1b d0b

Vac

dc d0c +d1c d0c

V0 V1 V2 V1 V0 V0 V1 V2 V1 V0

Gin ng ct pha nghch lu

1.5 H s cng sut u vo ca Sparse Matrix

Gi s dng ti c dng:

ui

Dng Idc s bng dng ti iA, -iC v 0 khi pha nghch lu iu ch tng ng vector V1, V2, V0 Gi tr trung bnh dng idc trong mt chu k s l
Lc gic vector khng gian dng u vo

(: gc lch pha gia p ti v dng ti)

pha chnh lu ln in p pha A l ln nht trong khong [-/6,/6], v vy kha SA s ng duy tr trong mt chu k v 2 kha cn li SB v SC s ng trong dbv dc

(Dng ngun)

(p ngun)

1.6 Kt lun - H s cng sut u vo lun c gi bng 1 . - Tt c cc kha phn chnh lu u c ng ct thi im dng bng 0 v vy an ton hn trnh c s qu p do dng gin on matrix truyn thng. - S kha ca Sparse matrix l t hn so vi matrix truyn thng . - Gii thut ng ct n gin hn.

NI DUNG TRNH BY
CU TRC V 2 GII THUT IU KHIN NG NGT CA SPARSE MATRIX 9 KHA KT QU M PHNG S DNG CC KHI XILINX BLOCKSET 2.1 S m phng v kt qu m phng gii thut ng ngt 1 2.2 S m phng v kt qu m phng gii thut ng ngt 2 KT QU THC NGHIM CA SPARSE MATRIX

2.1 S m phng gii thut ng ngt 1

Ngun ba pha Thng s ti R,L T s iu ch Chu k ng ct Ts Tn s p ra

380(V) (rms) p dy; 50Hz Rt = 15 , Lt = 10mH m = 0.7 Ts = 100s (fs = 10KHz) f0 = 60Hz

Kt qu m phng

Kt qu m phng

Kt qu m phng

2.2 S m phng gii thut ng ngt 2

Ngun ba pha Thng s ti R,L T s iu ch Chu k ng ct Ts Tn s p ra

380(V) (rms) p dy; 50Hz Rt = 15 , Lt = 10mH m = 0.7 Ts = 100s (fs = 10KHz) f0 = 60Hz

Kt qu m phng

Kt qu m phng

Kt qu m phng

NI DUNG TRNH BY
CU TRC V 2 GII THUT IU KHIN NG NGT CA SPARSE MATRIX 9 KHA KT QU M PHNG S DNG CC KHI XILINX BLOCKSET KT QU THC NGHIM CA SPARSE MATRIX 3.1 S iu khin v m hnh thc nghim ca Sparse Matrix 9 kha 3.2 Kt qu thc nghim v m phng ca gii thut ng ngt 1 3.3 Kt qu thc nghim v m phng ca gii thut ng ngt

3.1 S iu khin ca Sparse Matrix 9 kha

3.1 M hnh thc nghim ca Sparse Matrix 9 kha

S iu khin thc nghim ca Sparse Matrix

3.2 Kt qu thc nghim v kt qu m phng ca Sparse Matrix Gii thut ng ngt 1

Thng s thc nghim: Vpha=50V(rms); T s iu ch: Tn s ng ngt: Tn s p ra: Ti RL: Lc u vo: m=0,7; fsw = 10kHz (Ts=100s); f0=40Hz; R=30 ; L=30mH. Lfilter=1mH, Cfilter=20F.

Bng tm tt logic implementation thit k FPGA ca gii thut 1

Design Summary -------------Target Device : xc3s500e Target Package : fg320 Target Speed : -4 Number of Slice Flip Flops: 254 out of 9,312 2% Number of occupied Slices:3,198 out of 4,656 68% Number of 4 input LUTs: 5680 out of 9,312 60% Number of bonded IOBs: 26 out of 232 11% Number of BUFGMUXs: 2 out of 24 8% Number of MULT18X18SIOs: 2 out of 20 10%

Kt qu thc nghim v kt qu m phng ca Sparse Matrix

Dng sng p DC (gii thut ng ngt 1)

(a) Kt qu thc nghim dng sng p DC

(b) Kt qu m phng dng sng p DC

Dng sng p pha ca ti (gii thut ng ngt 1)

(a) Kt qu thc nghim dng sng p ti pha A

(b) Kt qu m phng dng sng p ti pha A

Kt qu thc nghim v kt qu m phng ca Sparse Matrix

Dng sng p dy ca ti (gii thut ng ngt 1)

(a) Kt qu thc nghim dng sng p dy ca ti

(b) Kt qu m phng dng sng p dy ca ti

(c) Phn tch FFT ph bin p dy ca ti

Kt qu thc nghim v kt qu m phng ca Sparse Matrix

Dng sng dng ca ti RL (gii thut ng ngt 1)

(a) Kt qu thc nghim dng sng dng ti RL

(b) Kt qu m phng dng sng dng ti RL

(c) Phn tch FFT ph bin ca dng ti RL

Kt qu thc nghim v kt qu m phng ca Sparse Matrix

Dng sng dng ngun (gii thut ng ngt 1)

(a) Kt qu thc nghim dng sng dng ngun

(b) Phn tch FFT ph bin ca dng ngun

3.3 Kt qu thc nghim v kt qu m phng ca Sparse Matrix Gii thut ng ngt 2

Thng s thc nghim: Vpha=50V(rms); T s iu ch: Tn s ng ngt: Tn s p ra: Ti RL: Lc u vo: m=0,7; fsw = 10kHz (Ts=100s); f0=40Hz; R=30 ; L=30mH. Lfilter=1mH, Cfilter=20F.

Bng tm tt logic implementation thit k FPGA ca gii thut 2

Design Summary -------------Target Device : xc3s500e Target Package : fg320 Target Speed : -4 Number of Slice Flip Flops: 255 out of 9,312 2% Number of occupied Slices:3,130 out of 4,656 67% Number of 4 input LUTs: 5,618 out of 9,312 60% Number of bonded IOBs: 26 out of 232 11% Number of BUFGMUXs: 2 out of 24 8% Number of MULT18X18SIOs: 2 out of 20 10%

Kt qu thc nghim v kt qu m phng ca Sparse Matrix

Dng sng p DC (gii thut ng ngt 2)

(a) Kt qu thc nghim dng sng p DC

(b) Kt qu m phng dng sng p DC

Dng sng p pha ca ti (gii thut ng ngt 2)

a) Kt qu thc nghim dng sng p ti pha A

(b) Kt qu m phng dng sng p ti pha A

Kt qu thc nghim v kt qu m phng ca Sparse Matrix

Dng sng p dy ca ti (gii thut ng ngt 2)

(a) Kt qu thc nghim dng sng p dy ca ti

(b) Kt qu m phng dng sng p dy ca ti

(c) Phn tch FFT ph bin p dy ca ti

Kt qu thc nghim v kt qu m phng ca Sparse Matrix

Dng sng dng ca ti RL (gii thut ng ngt 2)

(a) Kt qu thc nghim dng sng dng ti RL .

(b) Kt qu m phng dng sng dng ti RL

(c) Ph bin ca dng ti RL

Kt qu thc nghim v kt qu m phng ca Sparse Matrix

Dng sng dng ngun (gii thut ng ngt 2)

(a) Kt qu thc nghim dng sng dng ngun

(b) Phn tch FFT ph bin ca dng ngun

Cm n qu thy c v cc bn lng nghe