Self-controllabl le Voltage Level Circu uit for Low Power, High Speed S 7T SRAM Cell at a 45 nm Technology

Shyam Akashe, A Meenakshi Mishra,and Sanjay Sharma

Abstract- The trend of decreasing device si ize and increasing

chip densities involving several hund dred millions of transistors per chip has resulted in treme endous increase in design complexity. Power dissipation occurs o in various forms, such as dynamic, sub thresho old leakage, gate leakage, etc. and there is need to reduce e each of these. A low leakage power, 45-nm 7T SRAM is s designed in this paper. The stand-by leakage power of 7T T sram is reduced by incorporating a newly-developed leakage current reduction circuit called a Self-controlla able Voltage Level (SVL) circuit. Simulation result of 7t SR RAM design using CADENCE tool shows the reduction in total average power. In this design seven Transistor (7T) gated-ground sram is used as a Load Circuit. The Cadence C Virtuoso simulation in standard 45nm CMOS tec chnology confirms all results obtained for this paper. Keywords- Leakage Current, Low Power, SRAM, S SVL, VLSI I. INTRODUCTION In modern integrated chips, SRAM cells occupy a major on in the memory portion [1]. Now-a-days power dissipatio circuits has become an important design consideration. The equire that power advancements in the memory chip re consumption during the read and write opera ations must be low. Technology scaling results in a high density y of components but there is a significant increase in leakag ge current [2]. A minimum size SRAM cell is highly desirabl le for increasing the memory integration density. As the integrat tion of components increases, leakage power is becoming a prime concern in nd smaller devices todays memory chips. Lower voltages an cause a significant degradation of data stability in cells [3]. In und SRAM is used this design seven Transistor (7T) gated-grou as a Load Circuit. The bottom transistor is intended to cut off y mode to eliminate the ground path while the cell is in standby the leakage paths through the inverter NM MOS sources. This design has shown that the cell retains its va alue during standby even in the absence of a ground path. In thi is study, the bottom transistors gate is connected to the WORD D line. The bottom transistor is sized identically to the inverter r NMOS transistors to match their current carrying capacity. The e objective of this
Shyam Akashe is Associate Professor of ITM Gwalior, India (email: Vlsi.shyam@gmail.com) M Gwalior, India (email: Meenakshi Mishra is Research scholar of ITM mishra.meenakshi13@gmail.com) U Patiala, India (email: Sanjay Sharma is Associate Professor of TU sanjay.sharma@thapar.edu)

paper is to reduce leakage curren nt applying SVL technique and by investigate the transistor siz zing of the 7T SRAM cell for optimum power and leakage cur rrent. II. 7T SRAM CELL C DESIGN or SRAM cell is shown in fig1. The schematic of 7 transisto In this section, a new 7-transist tor SRAM cell which have low leakage current in stand-by mo ode. The gated-ground 7T cells are deemed superior in the e high performance process, while traditional 6T cells are deemed the best in the low power process. The layout of 7T SRAM M cell is shown in fig.2

Fig 1. Schematic of 7T SRAM Cell.

The 7 cell investigated is the e seven transistor (7T) gatedground SRAM cell depicted in Fig 1.This cell has an additional NMOS transistor pl laced in the ground path of a traditional 6T SRAM cell to red duce leakage while the cell is in standby mode.[4][5][6] Practice e has shown that the cell retains its value during standby even in n the absence of a ground rail. In this study, the bottom transi istors gate is connected to the WORD line. The bottom transi istor is sized identically to the inverter NMOS transistors to match their current carrying capacity.[7]

978-1-4673-0455-9/12/$31.00 2012 IEEE E

B.Read operation of 7T SRAM cell Given that Q stores 1, at first, WL is set to high to turn P1 and P2 off, next WL is maint tained at a high voltage to keep N5 on, BL is discharged throu ugh N3 and N5. Whereas BLB stays high because N4 insulates s BLB from the GND.The read operation waveform is shown in fig.4 .The storage nodes Q he datum from the BL during a and QB completely decouple th read operation. In contrast, when w Q stores 0, as long as turning P1 and P2 off, and turning N5 on, the BLB is N The read operation of the discharged through N4 and N5. proposed SRAM cell is differen nt from that of the 6T and 4T SRAM cells. In 7T SRAM cell, reading path is separated from writing path.

Fig. 2. Layout of 7T SRAM cell.

A. Write operation of 7T SRAM cell To write 1 to the storage node Q (0 to QB, espectively charged simultaneously), at first, BL and BLB are re and discharged. WL is set to low to turn P1 P and P2 on, next WL is maintained at a low voltage to keep N5 N off. Q is charged up to high-level by BL through P1, while QB Q is discharged to low-level by BLB through P2. When Q is ch harged sufficiently, set WL to high and turn P1 and P2 off. In co ontrast, to write 0 to the node Q (1 to QB, simultaneously) ), BL and BLB are discharged and charged, respectively. [8]

Fig. 4. Read operation waveform of 7T T SRAM cell with sense amplifier

Reading datum does not interfere the storage nodes. rage node, which stores 0, is Besides, the voltage of the stor closely maintained at the ground d level during a read operation. Therefore, the 7T SRAM cell has higher endurance against external noise. [8] III. Self-Controllab ble Voltage Level The portable systems which are driven by battery, echniques that reduce leakage There are two well-known te power (Pst). One is to use a multi-threshold-voltage m CMOS (MTCMOS) [9]. It effectively re educes Pst by disconnecting the power supply through the use of o high Vt MOSFET switches. However, there are serious dr rawbacks with the use of this technique, such as the fact that t both memories and flip-flops based on this technique cannot retain r data. The other technique involves using a variable thresho old-voltage CMOS (VTCMOS) [10] that reduces Pst by increa asing the substrate-biases. This technique also faces some serious problems, such as a large p due to the substrate-bias area penalty and a large power penalty supply circuits requires low leak kage power.

Fig.3. Write operation waveform of 7T SRAM cell

There is no additional power consumption ev ven if the write and read cycles come alternately, because ther re is no mismatch between the voltages level of bit lines in read cycles and that in write cycles. The write operation waveform is shown in fig.3

A self-controllable-voltage-level (SVL) circuitwhich c can supply a maximum DC voltage to an act tive-load circuit on request or can decrease the DC voltage supplied s to a load circuit in stand-by mode was developed. Thi is S V L circuit can drastically reduce stand-by leakage powe er of CMOS logic circuits with minimal overheads in terms of chip area and speed. When CL goes to a high level, VD increases to VDD (0.7V), while VS decreases to VSS (0V V), so the SRAM becomes active[11]. Three types of self-controllable voltage level (SVL) circuits are developed. Type-1 [Fig.5] has an upper SVL circuit, Type-2 [Fig.6] has a bines the upper and lower SVL circuit, and Type-3 [Fig.7] comb lower SVL circuits. In the following, for simplicity of explanation of the SVL circuit function, a SRAM cell is assumed as the load-circuit. The upper SVL consists of a single ET switch (n-SW) p-MOSFET switch (p-SW) and n-MOSFE connected in series. The on p-SW connects a power supply ode on request, and (VDD) and the load circuit in the active mo on n-SW connect VDD and the load circuit c in stand-by mode.

e stand-by inverter shown Fig. While gate voltage (VG) of the 4(a) is kept at 0, the p-MOSF FET (pMOS) is turned on while the n-MOSFET (n-MOS) is tu urned off. When control signal (CL) turns on n-SW1 and turns off p-SW, VDD is supplied to the inverter through n-SWs. Thus, T a drain-to-source voltage (Vdsn), that is, a drain voltage (VD) of the off n-MOS, can be expressed as Vdsn= VDD mv, (1)

Fig .6. Schematic diagram of LSVL ba ased 7T SRAM cell.

Where v is a voltage drop of f the single n-SW and Vdsn can be changed by varying m or v (or both). Decreasing Vdsn by t barrier height of the off nincreasing m or v will increase the MOS; that is, it will decrea ase the drain induced-barrierlowering (DIBL) effect and, co onsequently, increase Vthn this results in a decrease in the sub threshold t current of the n-MOS (Istn); that is, the leakage current through the inverter decreases. S circuit, a negative control In the case of the Type-2 SVL signal (CLB) turns on p-SW1 an nd turns off nSW so that VSS is supplied to the stand-by inverter with VG of 0 (i. e. , m v) through m p-SWs. Thus, according to Equation (1), reduced ore, source voltage (VS) is Vdsn reduces Istn Furthermo increased by mv, so the substr rate bias (i.e., back-gate bias) (Vsub), expressed by Vsub= mv, (2) on in the DIBL effect and the is increased. Both the reductio increase in the back-gate bias (BGB) effect lead to further increase in Vthn.

Fig. 5.Schematic diagram of USVL based 7T SRAM cell c

Similarly, the lower SVL circuit, which inc corporates a single n-SW and p-SW connected in series, is located between a ground-level power supply (VSS) and the e load circuit. The lower SVL circuit not only supplies VSS S to the active-load circuit through the on n-SW but also sup pplies VSS to the stand-by load circuit through the use of th he on p-SW.The effect of the SVL circuit on the leakage current c through the load circuit (i.e., reduction in current) was w examined. The SVL circuit and the load circuit were desi igned using 45 nm CMOS technology. The effective gate length of both the n-MOSFET and pMOSFET was 45 nm, the threshold voltag ge (Vthn) of the nMOSFETs was 0.21 V, and the threshold voltage (Vthp) of the p-MOSFETs was -0.27 V.

The DIBL effect on n-M MOS in the stand-by inverter incorporating the Type-3 SVL L circuit is further decreased, since Vdsn in this case can be ex xpressed as Vdsn= VDD 2mv, (3) b [given by Eq. (2)] also occurs The BGB effect due to Vsub in the Type-3 circuit.The wavef form of SVL based 7T SRAM is shown in fig.8.The operation mode of SVL circuit is shown in TABLE I. IV. CIRCUIT SIMUL LATION AND RESULTS In this paper a SVL based connection c is used in proposed 7T SRAM cell. The parameter rs and result of SVL based 7T SRAM cell using cadence virtuo oso tool is given in TABLE (II) and TABLE (III) respectively.
TABL LE II PARAMETERS OF 7T SRAM CELL
Process Technology Power Supply Voltage Fig. 7. Schematic diagram of SVL based 7T SRAM ce ell. Pre-Charge Voltage 0.7V 1V 45nm

TABL LE III SIMULATION RESULT OF SV VL BASED 7T SRAM CELL Circuit 7T SRAM during Write 7T SRAM during Read 7T SRAM with USVL 7T SRAM with LSVL 7T SRAM with SVL Leakage Current 1.347 uA 1.25 uA 1.155 A 1.077 A 0.04 A

IV. ACKNOWL LEDGEMENT This work was supported ITM I University Gwalior, with collaboration Cadence design sy ystem. The authors would also like to thank to Professor R.D Gupta G sir for their enlightening technical advice..
Fig. 8. Waveform of SVL based 7T SRAM cel TABLE I OPERATION MODE

Mode Active

Upper SVL Circuit pMOS switch is turned on VDD is supplied

Lower SVL S Circuit s is turned on nMOS switch Vss is su upplied pMOS switch s is turned on VS(>VSS S) is supplied

Standby Mode

nMOS switch is turned on VD (<VDD) is supplied

V.CONCL LUSION SVL circuit will play a major role in future. The effect of c through the load circuit the SVL circuit on the leakage current (i.e., reduction in current) was examined. e The SVL circuit and the load circuit were designed using u 45nm CMOS technology. Sub threshold memory design has h received a lot of attention in the past years, but most of them m use large number of transistor to achieve sub threshold region n operation. The new technique inherently process variation tolerant, t this makes the new approach attractive for nano computing in which process nstraint. In this circuit we have variations is a major design con several advantages in different modes m that is in operating mode high Vds to load circuits for hig gh speed operation, in stand-by mode load Vds through On MOS M switches to Load circuits for minimum stand-by leakage e power, data retention, high

noise immunity and SVL circuit small stand-by power dissipation, negligible speed degradation, negligible area overhead, high noise immunity, data retentions at stand-by mode. REFERENCES
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