Carry Skip Adders

- A verilog implementation
Abhiram L S 1MS13LVS01

Aim
To simulate and synthesize a 32 bit carry skip adder.

Working of a carry skip adder

Delay of an N-Bit carry skip adder

T=Tsetup+MTcarry+((N/M)-1)Tcarry+Tsum Tsetup is the time taken for inputs to be available at the adders, Tcarry is the time taken to compute the carry Tsum is the time taken to compute the sum M is the number of bits in each block and N is the number of bits in the binary numbers Maximum combinational path delay (On synthesis) = 19.529ns

Simulation Results

RTL Schematics

What is new??
Carry skip chain can be used for all N-bits of input data

Limitations
Performs most efficiently only when the number is such that corresponding bits of the two binary numbers are not equal. Every time the adder encounters a set of equal bits, it has to generate a new carry The delay in generating the carry is involved.

References
M.D. Ercegovac and T. Lang, Digital Arithmetic. San Francisco: Morgan Daufmann, 2004. Israel Koren, Computer Arithmetic Algorithms. Pub A K Peters, 2002. John P Uyemura, Introduction to vlsi circuits and systems., 2nd Edition