Verilog Language

DataandTypes

Outline
LanguageElements Constants DataValues DataTypes Identifier

LanguageElements
Tokens
predefinedwordsorconstructsrecognizedbythe compilers usedtobuildbiggerconstructsuchasexpressionsand statements e.g.,numbers,strings,operators,identifiers,comments,..

Comments
Commentsaretoken Providingdocumentsaboutthesourcecode Noeffectonprogramcorrectnessandperformance

LanguageElements
WhiteSpaces
nontextcharactersusedtoseparatetokens e.g.,<Space>,<Tab>,<Newline>,<Endoffile>

CompilerDirectives
removedbythepreprocessorbeforecompilationstarts commandstocontrolcompilationprocess

e.g.,`defineNBITS64//textmacro
`includealu.h//fileinclusion

LanguageElements
Comments

// helloWorld.v Compilerdirectives `include hello.h module helloworld; tokens initial $display("Hello World!"); endmodule
Whitespace

Data
Variableorconstant Syntax:Integerconstantinbinary
binary_number ::= [ size ] binary_base binary_value binary_base ::= [s|S]b | [s|S]B binary_value ::= binary_digit { _ | binary_digit } binary_digit ::= x_digit | z_digit | 0 | 1 x_digit ::= x | X z_digit ::= z | Z | ?

(Ex)
5sb1011 // 5-bit (=5b01011), signed 6sb10 // 6-bit (=6b000010), signed 7b110_1001 // 7-bit (=7b1101001) 8b1110_0110 // 8-bit (=8b11100110) 9b1101 // 9-bit (=9b000001101) 16b1111_1111_1111_1111 // 16-bit

Data
Variableorconstant Syntax:Integerconstantinbinary
binary_number ::= [ size ] binary_base binary_value binary_base ::= [s|S]b | [s|S]B binary_value ::= binary_digit { _ | binary_digit } binary_digit ::= x_digit | z_digit | 0 | 1 x_digit ::= x | X z_digit ::= z | Z | ?

Thesizefieldisoptional.Ifmissing,thedefaultsizeisassumed (32bits) (ex)sb1011 // 32-bit (=32sb1011), signed

b10 // 32-bit (=32b10)

Data
Variableorconstant Syntax:Integerconstantinbinary
binary_number ::= [ size ] binary_base binary_value binary_base ::= [s|S]b | [s|S]B binary_value ::= binary_digit { _ | binary_digit } binary_digit ::= x_digit | z_digit | 0 | 1 x_digit ::= x | X z_digit ::= z | Z | ?

Iftheconstantcontainsx,z,or?,thebitvalueofthemost significantbitisduplicated.Thebitvalue?ishandledasthez. (ex)4bzx // 4-bit (=4bzzzx) 5bxz // 5-bit (=32bxxxxz) b?x // 32-bit (=32bzx)

Data
Syntax:Integerconstantindecimal
decimal_number ::= decimal_digit | { _ | decimal_digit } | [ size ] decimal_base unsigned_number | [ size ] decimal_base x_digit { _ } | [ size ] decimal_base z_digit { _ } decimal_base ::= [s|S]d | [s|S]D decimal_digit ::= 0-9

(Ex)Decimalconstantcanberepresentedwithoutthenumberbase.
12 1_023 7sd127 12d2048 d32 // // // // // 32-bit (=32b1100) 32-bit (=32b1111111111) 7-bit (=7sb1111111), signed 12-bit (=12b100000000000) 32-bit (=32b100000)

Data
Syntax:Integerconstantinoctal
octal_number ::= [ size ] octal_base octal_value octal_base := [s|S]o | [s|S]O octal_value ::= octal_digit { _ | octal_digit } octal_digit ::= x_digit | z_digit | 0-7

(Ex)
7so17 8ozx 9o?x o331 // // // // 7-bit (=7b0001111), signed 8-bit (=8bzzzzzxxx) 9-bit (=9bzzzzzzxxx) 32-bit (=32b011011001)

Data
Syntax:Integerconstantinhexadecimal
hex_number ::= [ size ] hex_base hex_value hex_base ::= `[s|S]h | `[s|S]H hex_value ::= hex_digit { _ | hex_digit } hex_digit ::= x_digit | z_digit | 0-9 | a-f | A-F

(Ex)
8h87 // 8-bit (=8b10000111) 32h80123 // (=32b10000000000100100011)

Data
Unaryminusoperator()canbeusedwithaninteger constant Theoperatorperforms2scomplementofthe numberthatitprecedes.
(Ex)
-5b1011 +8b11001010 -7so17 -7sd127 -8h87 // // // // // (=5b10101) (=8b11001010) (=7b1110001) (=7b0000001) (=8b01111001)

Data
Syntax:realconstant
real_number ::= unsigned_number.unsigned_number | unsigned_number[.unsigned_number] exp [sign] unsigned_number exp ::= e | E sign ::= + |

(Ex)
21.125 3.2E-5 // 3.210-5 -0.001315 -0.031415E2 // -0.031415102

Data
Syntax:string Stringliteralsarerepresentedasasequenceofany ASCIIcharacterbutanewline Theyareenclosedinapairofdoublequotes.
(Ex)
Hello! World Welcome to Verilog!

DataValues
DataValues=#ofBits BitValues:Fourpossiblevalues
0, 1: Boolean binary values X (x): ambivalent, unknown Z (z): value corresponding to high-impedance signal ?: Z
Bit Values

Value 0 1 x or X z or Z

Description 0, logic 0, or false 1, logic 1, or true Unknown or not determined Unknown or not determined

DataValues
ValueX

DataTypes
BasicDataTypes:Integer,Time,Real,Realtime,Reg,Net Type reg net integer time real realtime Data Types Description Used to describe or model logic function, hold integer value Used to model wire connection, carry integer value Hold 32-bit integer value Hold 64-bit integer value for simulation time Hold real value Hold real value for simulation time

DataTypes
Reg DataType reg typevariablesareprimarilyusedtomodellogic functions. regtypevariablesaredeclaredusingthefollowing syntax:
reg_declaration ::= reg [ signed ] [ range ] list_of_variable_identifiers ; range ::= [ constant_expression : constant_expression ] list_of_variable_identifiers ::= variable_type { , variable type} variable_type ::= variable_identifier [ = constant_expression ] | variable_identifier dimension { dimension }

DataTypes
Reg DataType
reg_declaration ::= reg [ signed ] [ range ] list_of_variable_identifiers ; range ::= [ constant_expression : constant_expression ] list_of_variable_identifiers ::= variable_type { , variable type} variable_type ::= variable_identifier [ = constant_expression ] | variable_identifier dimension { dimension }

(ex) reg-type variable declarations reg t, u; // t, u: 1-bit, unsigned reg [7:0] v; // 8-bit, unsigned reg signed [8:1] w; // 8-bit signed reg [3:0] reg_file [7]; // array reg [7:0] img_1 [47:0][31:0] //2-d array

DataTypes
Reg DataType
reg_declaration ::= reg [ signed ] [ range ] list_of_variable_identifiers ; range ::= [ constant_expression : constant_expression ] list_of_variable_identifiers ::= variable_type { , variable type} variable_type ::= variable_identifier [ = constant_expression ] | variable_identifier dimension { dimension }

(ex) variable declaration with initialization reg y = 0; // y=0 reg [7:0] y1=0, y2=1; //y1=0, y2=1 reg [3:0] y3; //y3=4bxxxx reg [1:0] y4 [1:0]; y4[1]=2bxx,y4[0]=2bxx

DataTypes
NetTypes nettypes:supply0,supply1,tri,triand,trior,trireg, tri0,tri1,wand,wire,wor nettypevariablesareprimarilyusedtomodel interconnections Nettypevariablesaredeclaredusingthefollowing syntax:

net_declaration ::= net_type [ signed ] [ delay3 ] list_of_net_identifiers ; | net_type [ drive_strength ] [ signed ] [ delay3 ] list_of_net_decl_identifiers ; | net_type [ vectored | scalared ] [ signed ] range [ delay3 ] list_of_net_identifiers ; | net_type [ drive_strength ] [ vectored | scalared ] [ signed ] range [ delay3 ] list_of_net_decl_assignments ; | trireg [ charge_strength ] [ signed ] [ delay3 ] list_of_net_identifiers; | trireg [ drive_strength ] [ signed ] [ delay3 ] list_of_net_decl_assignments; | trireg [ charge_strength ] [ vectored | scalared ] [ signed ] range [ delay3 ] list_of_net_identifiers; | trireg [ drive_strength ] [ vectored | scalared ] [ signed ] [ range ] [ delay3 ] list_of_net_decl_assignments; net_type ::= supply0 | supply1 | tri | triand | trior | tri0 | tri1 | wand | wire | wor list_of_net_identifiers ::= net_identifier [ dimension { dimension }] { , net_identifier [ dimension { dimension }] } list_of_net_decl_assignments ::= net_decl_assignment { , net_decl_assignment } net_decl_assignment ::= net_identifier = expression

DataTypes
NetTypes
(ex) tri [7:0] l; wire signed [8:1] m; // signed wire y=a & b; // with assignment wire [1:0] w1 [7:0]; // array