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The hyper transport protocol defines a high-performance and scalable interconnect between CPU, memory, and I/O devices.

Conceptually, the architecture of the Hyper Transport I/O link can be mapped into five different layers, which structure is similar to the Open System Interconnection (OSI) reference model. In Hyper Transport technology: 1. The physical layer defines the physical and electrical characteristics of the protocol. This layer interfaces to the physical world and includes data, control, and clock lines 2. The data link layer includes the initialization and configuration sequence, periodic Cyclic redundancy check (CRC), disconnect/reconnect sequence, information packet for flow control and error management, and double word framing for other packets. 3. The protocol layer includes the commands, the virtual channels in which they run, and the ordering rules that govern their flow. The HyperTransport technology I/O link is a narrow, high speed, low power I/O bus that has been designed to meet the requirements of the embedded markets, the desktop, workstation, and server markets, and networking and communications markets. HyperTransport technology links are capable of extremely fast signaling with clock speeds of up to 800 MHz, and Double Data Rate (DDR) memory signaling, to provide an effective throughput of 1.6 gigatransfers per pinpair on a 32-bit link. The result is a maximum aggregate throughput of 12.8 gigabytes per second, per link. This paper focuses on the benefits that HyperTransport technology gives system designers and the advanced capabilities that HyperTransport technology offers.