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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity counter is
Port ( clk : in STD_LOGIC;
rst : in STD_LOGIC;
din : in STD_LOGIC_VECTOR (3 downto 0);
dout : out STD_LOGIC_VECTOR (3 downto 0);
up_dn : in STD_LOGIC;
load : in STD_LOGIC);
end counter;
begin
process(clk, rst)
begin
if rst='1' then
scale<=(others=>'0');
elsif clk'event and clk='1' then
scale<= scale+1;
end if ;
end process;
clk_s<= scale(22);
end if;
end if;
end process;
dout<= cnt;
end Behavioral;