Overview

Why VLSI? Moores Law. Why FPGAs? The VLSI and system design process.

Why VLSI?
Integration improves the design:
lower parasitics = higher speed; lower power; physically smaller.

Integration reduces manufacturing cost(almost) no manual assembly.

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

VLSI and you

Moores Law
Gordon Moore: co-founder of Intel. Predicted that number of transistors per chip would grow exponentially (double every 18 months). Exponential improvement in technology is a natural trend: steam engines, dynamos, automobiles.

FPGA-Based System Design: Chapter 1 Copyright 2004 Prentice Hall PTR

Microprocessors:
personal computers; microcontrollers.

DRAM/SRAM/flash. Audio/video and other consumer systems. Telecommunications.

FPGA-Based System Design: Chapter 1

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Moores Law plot

The cost of fabrication

Current cost: $2-3 billion. Typical fab line occupies about 1 city block, employs a few hundred people. New fabrication processes require 6-8 month turnaround. Most profitable period is first 18 months-2 years.

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Cost factors in ICs

Mask cost vs. line width

1,000,000 900,000 800,000 700,000 600,000 500,000 400,000 300,000 200,000 100,000 0 .25 micron .18 micron .13 micron .09 micron

For large-volume ICs:

packaging is largest cost; testing is second-largest cost.

For low-volume ICs, design costs may swamp all manufacturing costs.
$10 million-$20 million.

mask cost ($)

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Field-programmable gate arrays

FPGAs and VLSI

FPGAs are programmable logic devices:

Logic elements + interconnect. Provide multi-level logic.
LE LE LE Interconnect network LE LE LE
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FPGAs are standard parts:

Pre-manufactured. Dont worry (much) about physical design.

Custom silicon:
Tailored to your application. Generally lower power consumption.

FPGA-Based System Design: Chapter 1

FPGA-Based System Design: Chapter 1

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Standard parts vs. custom

Challenges in system design

Multiple levels of abstraction: logic to CPUs. Multiple and conflicting constraints: low cost and high performance are often at odds. Short design time: Late products are often irrelevant.

Do you build your system with an FPGA or with custom silicon?

FPGAs have shorter design cycle. FPGAs have no manufacturing delay. FPGAs reduce inventory. FPGAs are slower, larger, more power-hungry.

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

The system design process

May be part of larger product design. Major levels of abstraction:

Dealing with complexity

Divide-and-conquer: limit the number of components you deal with at any one time. Group several components into larger components:
transistors form gates; gates form functional units; functional units form processing elements; etc.
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specification; architecture; logic design; circuit design; layout.

FPGA-based system design

FPGA-Based System Design: Chapter 1

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FPGA-Based System Design: Chapter 1

Hierarchical name

Instantiating component types

Interior view of a component:

components and wires that make it up.

Each instance has its own name:

add1 (type full adder) add2 (type full adder).

Exterior view of a component = type:

body; pins.
a cout

sum

Each instance is a separate copy of the type:

cout

Full adder
cin

Add1.a
a Add1(Full adder) b cin

Add2.a
sum a Add2(Full adder) b cin
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sum

b
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FPGA-Based System Design: Chapter 1

FPGA-Based System Design: Chapter 1

A hierarchical logic design

Net lists and component lists

Net list:
net1: top.in1 in1.in net2: i1.out xxx.B topin1: top.n1 xxx.xin1 topin2: top.n2 xxx.xin2 botin1: top.n3 xxx.xin3 net3: xxx.out i2.in outnet: i2.out top.out

Component list:
top: in1=net1 n1=topin1 n2=topin2 n3=topine out=outnet i1: in=net1 out=net2 xxx: xin1=topin1 xin2=topin2 xin3=botin1 B=net2 out=net3 i2: in=net3 out=outnet
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box1

box2

z
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Component hierarchy
top

Hierarchical names
Typical hierarchical name:
top/i1.foo
component pin

i1

xxx

i2

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 1

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Layout and its abstractions

Stick diagram
VDD

Layout for dynamic latch:

Q'

VSS
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'
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Transistor schematic
+ '
D '

Mixed schematic

Q'

Q'

inverter

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 1

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Levels of abstraction
Specification: function, cost, etc. Architecture: large blocks. Logic: gates + registers. Circuits: transistor sizes for speed, power. Layout: determines parasitics.

Circuit abstraction
Continuous voltages and time:
+
v v

FPGA-Based System Design: Chapter 1

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FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Digital abstraction

Register-transfer abstraction

Discrete levels, discrete time:

a
a cout

Abstract components, abstract data types:

0010

sum full sum adder

t b
b

t
cin

+
0001

t a
a cout

sum full sum adder

+
0100
t

0011

cin

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

FPGA-Based System Design: Chapter 1

Copyright 2004 Prentice Hall PTR

Top-down vs. bottom-up design

Design abstractions
English Executable program

Top-down design adds functional detail.

Create lower levels of abstraction from upper levels.

specification behavior
registertransfer Throughput, design time Function units, clock cycles Literals, logic depth nanoseconds microns
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Bottom-up design creates abstractions from low-level behavior. Good design needs both top-down and bottom-up efforts.

FPGA-Based System Design: Chapter 1 Copyright 2004 Prentice Hall PTR

function

Sequential machines Logic gates transistors rectangles

cost

logic circuit layout

FPGA-Based System Design: Chapter 1

FPGA design
FPGA manufacturer creates an FPGA fabric; system designer uses the fabric. FPGA fabric design issues:

Why do we care about layout?

We wont design layout. Layout determines:
Logic delay. Interconnect delay. Energy consumption.

Study sample user designs. Select interconnect topology. Create logic element structures. Design circuits, layout.
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We want to understand sources of FPGA characteristics.

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FPGA-Based System Design: Chapter 1

FPGA-Based System Design: Chapter 1

Design validation
Must check at every step that errors havent been introduced-the longer an error remains, the more expensive it becomes to remove it. Forward checking: compare results of lessand more-abstract stages. Back annotation: copy performance numbers to earlier stages.

FPGA-Based System Design: Chapter 1 Copyright 2004 Prentice Hall PTR