Thc hnh thit k h thng nhng Lab 1

Bi 1: Lm quen vi cch to project v thit k hm EXOR trn Quartus II trn board DE2.
A. To Project trn Quartus II
Bc 1: M Quartus II 9.0 Web Edition.

Bc 2: To mt project

- To mt th mc l m s sinh vin d lm vic sut qu trnh thc hnh lab. V d: D:\0123xxxx\EmbSysLab\Bai1. - t tn project s lm vic l light.

Bc 3: Ch r 1 file no cn a vo project Quartus qun l. Phn ny tm thi cha c file no nn ta chn next.

Bc 4: Ch r loi chip FPGA trn board DE2. Bc ny i hi chnh xc.

H chip l Cyclone II

Tn chip l EP2C35F672C6 cho board DE2

Bc 5: Ch r nhng cng c h tr thm t nh cung cp i tc ca Altera. Trong bc ny chn next.

Bc cui cng: Quartus tm tt cu hnh lm vic cho project va c to ra.

B. Thc hnh thit k hm EX-OR

Cho on chng trnh VHDL m t hm f = x1 EX-OR x2:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity light is Port ( x1 : in std_logic; x2 : in std_logic; f : out std_logic); end light;

architecture model of light is begin f <= (x1 and not(x2))or(not(x1) and x2); end model; Bc 1: To mt file son tho m t on VHDL trn v a vo project light.

Son tho on code trn v save li t tn l light.vhd.

Bc 2: Thc thi bin dch code. Compiler s bin dch cc file verilog trong project theo trnh t nh sau: 1 Phn tch code, 2 Tng hp mch, 3 To vi mch tng hp cho chip FPGA.

C. Chy m phng mch

Bc 1 : Vo File -> chn New-> Vector Waveform File. Sau save li vi tn file l light.vwf.

Bc 2 : Xc nh thi gian gi lp m phng.

Bc 3 : a cc tn hiu vo m phng

Bc 4 : Thit lp gi tr cho cc tn hiu. C 2 cch. 1 - Click vo tn hiu -> chn gi tr cho n.

2 - R chut vo tn hiu v chn gi tr.

Bc 5 : Thit lp gi lp m phng chc nng cho hm f

Sau save li file m t gi lp dng sng ny. Bc 6 : Tin hnh qu trnh phn tch v tng hp. 1 - Vo Processing -> Generate Functional Simulation Netlist

2 - Sau Chn Processing -> Start Simulation. Mn hnh thng bo gi lp m phng thnh cng

Sinh vin lp li bc 4 th li vi cc gi tr gi tr input khc nhau. Kim tra kt qu ca hm f.

Bc 7: Th m phng vi gi lp c thi gian tr (Timing Simulation). Lp li bc 5 thay v chn Funtional, sinh vin chn Timing.

Nhn vo dng sng m phng, sinh vin th quan st tr bao nhiu ?

D. Cu hnh chn v thc hnh np chy trc tip ln board

c th chy c mt mch t hp trn board DE2, cn phi ni cc tn hiu mch t hp ny n cc chn vt l trn board. Cu hnh chn mc ch l nh x tn hiu

input/output n cc chn vt l ca board DE2. Gi s ta mong mun nh sau: Trn board DE2 2 cng tc gt SW0, SW1 (tham kho trang 27 DE2_UserManual.pdf) s c ni vo tng ng cho cc tn hiu x1, x2 v n led mu xanh 0 LEDG0 (trang 29 DE2_UserManual.pdf) s c ni vo ng output f. Nh vy khi gt cng tc thay i gi tr ng vo, th ta s bit c ng output s hin th ln n led. Altera Quartus II h tr cng c lm vic ny.

bit c tn hiu trn board c nh danh (ID) l bao nhiu, sinh vin tham kho ti liu DE2_UserManual.pdf hoc file Excel DE2_pin_assignments.exc.

Bc 1: Chn Assignments -> Assigment Editor.

Tng t x2 gn cho PIN_N26, f gn cho PIN_AE22.

* Trong trng hp mun xut hoc a vo mt file cu hnh chn c sn, c th chn Assigments -> Export Assigments hoc Assignments -> Import Assigments.

Bc 2: Sau khi cu hnh chn xong cn bin dch li Quartus cp nht cu hnh chn cho vi mch c thit k. Bc 3: Np v chy ln board. DE2 h tr 2 cch np ln board. l ch np l JTAG v AS. Trong ch JTAG (Joint Test Action Group) th d liu cu hnh s c np trc tip ln FPGA. Trong ch ny th thng tin cu hnh s b mt khi tt ngun. ch AS (Active Serial), th d liu cu hnh s c np ln b nh flash. Mi khi m ngun (reset) th thng tin cu hnh y s c load ln FPGA, do thng tin cu hnh FPGA s khng b mt mi khi tt ngun. chuyn i gia 2 ch np ny th trn board DE2 cung cp nt RUN/PROG. RUN tng ng vi ch np JTAG, trong khi PROG l ch AS. * Trong tt c qu trnh thc hnh, ch xi ch np l JTAG - Gt nt RUN/PROG trn board DE2 sang RUN, sau chn Tools->Programmer, ca s lp trnh cho board DE2 s xut hin nh hnh v.

- Trn ca s lp trnh, ch la chn JTAG trong khung ch lp trnh (Mode). Tip o nu USB-Blaster khng c chn nh trn hnh, th bn nhn Hardware Setup, ca s Hardware Setup s xut hin khi bn chn USB-Blaster la chn cng kt ni vi board DE2.

- Tr li ca s lp trnh bn chn vo file lp trnh (light.sof). Nu file ny cha c th bn c th nhn nt Add File thm file ny vo. Tip bn nhp vo la chn Program/configure

- Nhn nt Start bt u vic lp trnh. Trong khi lp trnh th cc n led trn board DE2 s sng m i. Trn ca s lp trnh, thanh Progess s cho thy tin trnh np ln board DE2. Sinh vin quan st kt qu hm f khi bt ln bt xung cng tc.

Bi 2: Decoder Led 7 on
Hnh di cho thy mt module decoder 7-on vi u vo 4-bit d3d2d1d0. Decoder to ra by u ra c s dng hin th mt k t trn mt n LED 7-on. Bng di lit k cc k t c hin th cho mi gi tr ca d3d2d1d0. By phn on c xc nh bi cc ch s 0 n 6 nh trong hnh. Mi on s sng khi u vo ca n c gi tr logic 0. Hy vit mt module VHDL thc hin chc nng hin th nh trn.

d3d2d1d0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111

Gi tr thp phn 0 1 2 3 4 5 6 7 8 9 A B C D E F

Thc hin cc bc sau: 1. To mt project Quartus II mi. 2. To mt module VHDL cho decoder 7-on. Kt ni u vo d3d2d1d0 cho switch SW3-0, v ni u ra ca decoder n cc HEX0 display trn DE2. Cc on HEX0 c gi l HEX00, HEX01,. . ., HEX06, tng ng vi Hnh trn. Nn khai bo cng 7bit trong code HEX0 : out std_logic_vector(6 downto 0) ;

3. Sau khi thc hin cc yu cu gn pin trn, bin dch project. 4. Download mch bin dch vo chip FPGA. Kim tra cc chc nng ca mch bng cc bt tt cc switch SW3-0 v quan st hin th 7-on.

Bi 3: Dng VHDL thit k m hnh b nh RAM 16 * 8 bit nh hnh v sau

Address Key 3 Key 2 Clock Key 1 Key 0 Reset Data iu khin d liu (Data Control) iu khin a ch (Address Control) Gii m Led 7 on Gii m Led 7 on Hex6 (6 downto 0)

RAM
Gii m Led 7 on

Hex5 (6 downto 0)

Hex4 (6 downto 0)

Key 2 l mt nt nhn dng tng a ch (address) trn RAM, Key 3 l mt nt nhn khc dng gim a ch trn RAM. Key 0 v key 1 dng thay i d liu trn RAM. Key 0 l mt nt nhn dng tng gi tr d liu ti mt a ch. Ngc li Key 1 l nt nhn dng gim gi tr d liu. a ch v d liu s c hin th ln led 7 on. Thc hin cc bc sau: 1. To mt project Quartus II mi. 2. To mt module Verilog cho decoder 7-on. 3. Sau khi thc hin cc yu cu gn pin trn, bin dch project. 4. Download mch bin dch vo chip FPGA. Kim tra cc chc nng ca mch bng cc bt tt cc switch SW3-0 tng ng cho d0, d1, d2, d3 v quan st hin th 7-on. 5. Hin thc module RAM nh on code sau:

Trong hm conv_interger s chuyn gi tr tham kho input chun std_logic_vector sang kiu interger nh ch mc trn mng RAM. 6. Thc hin m phng kim tra kt qu ca module RAM ny. 7. Hin thc module iu khin a ch, thc hin m phng v kim tra trc tip trn board bng cch xut ra led 7 on 8. Hin thc module iu khin d liu, thc hin m phng kim tra kt qu 9. Kt ni cc module li vi nhau v kim tra kt qu theo m hnh khi trn.