PLL: Study, Modeling & Simulation in

MATLAB
Mohammad A Maktoomi, PhD 1225
IIIT-D, India.

ABSTRACT
Phase-locked loop (PLL) is one of the most important building block in today's electronics
industry. PLL is a negative feedback system which ensures a constant phase relation between a
reference input and feedback signal- thereby equalizes the input and output frequency.
The first micropower CMOS PLL was introduced in early 70s, since then many advancements
have been done in this area. Many types of PLL are available: analog phase-locked loop
(APLL), digital phase-locked loop (DPLL), all digital phase-locked loop (ADPLL), and software
phase-locked loop (SPLL). Recently, a lot of attention has been on fractional-N frequency
synthesizers. They allow us to generate a clock whose frequency is a fraction of the reference
frequency.
Historically, PLL has been used in demodulation of AM and FM. It is used for clock (bit)
synchronization in state of the art communication systems. It is used for precise clock generation
in microprocessor including multiples of a reference clock ( frequency synthesizers).
This class project is aimed at :
- the study of PLL architectures including the state-of-the arts
- the study of PLL performance under noise
- the study of Non-linear operation in PLL
MATLAB will be used throughout this study as a CAD tool. Specifically, we will implement
PLL in MATLAB and study their performance to support theoretical results.