IMPORTANT GUIDELINES

 VHDL is case insensitive language.

 Either asynchronous or synchronous RESET will be asked. If nothing is mentioned its
Asynchronous RESET
 "With Enable" or "without Enable" will be asked in the exam. If nothing is mentioned you can
write your choice.
 The module size may vary from what you did in the lab
(eg. 8-bit counter instead of 4-bit / 4x16 decoder instead of 3x8 decode etc..)
 Specifically behavioral OR Data flow style will be asked for selected programs. Prepare both
styles.
 SRAM,ROM, FIFO programs will also be asked in the final exam
 Develop the habit of modularity and commenting in the programming
 Don’t forget to add the following lines at the beginning; else you will not get results.
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

 Note: This document is NOT error-free... so use with caution! REPORT ERROR TO ME
VISIT www.esnips.com/user/ttreddy for softcopy and visit regularly for many more useful
documents and links.
---------------------------------------------------------------------
Program No1(A): 3x8 Decoder DATA-FLOW style
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity V3to8dec is
port ( enable : in STD_LOGIC;
A : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC_VECTOR(0 to 7) );
end V3to8dec;

architecture arch_V3to8dec of V3to8dec is

signal Y_temp: STD_LOGIC_VECTOR(0 to 7);
begin
with A select <=
Y_temp <= "10000000" when "000",
"01000000" when "001",
"00100000" when "010",
"00010000" when "011",
"00001000" when "100",
"00000100" when "101",
"00000010" when "110",
"00000001" when "111",
"00000000" when others;
Y <= Y_temp when (enable) ='1' else "00000000";
end arch_V3to8dec;
---------------------------------------------------------------------
---------------------------------------------------------------------
Program No1(B): 3x8 Decoder BEHAVIORAL style
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity V3to8dec is
port (enable : in STD_LOGIC;
A : in STD_LOGIC_VECTOR(2 downto 0);
Y : out STD_LOGIC_VECTOR(0 to 7) );
end V3to8dec;

architecture arch_V3to8dec of V3to8dec is

signal Y_temp: STD_LOGIC_VECTOR(0 to 7);
begin
process(A, enable, Y_temp)
begin
case A is
when "000" => Y_temp <= "10000000";
when "001" => Y_temp <= "01000000";
when "010" => Y_temp <= "00100000";
when "011" => Y_temp <= "00010000";
when "100" => Y_temp <= "00001000";
when "101" => Y_temp <= "00000100";
when "110" => Y_temp <= "00000010";
when "111" => Y_temp <= "00000001";
when others => Y_temp <= "00000000";
end case;
if (enable)='1' then Y <= Y_temp ; else Y <= "00000000"; end if;
end process;
end arch_V3to8dec;
---------------------------------------------------------------------
Program No2(A): 8x1 MUX DATA-FLOW style
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity mux8x1 is
port (
S : in STD_LOGIC_VECTOR(2 downto 0);
data_in : in STD_LOGIC_VECTOR (7 downto 0); -
Y : out STD_LOGIC )
end mux8x1;

architecture arch_mux8x1 of mux8x1 is

begin
with S select Y <=
data_in(0) when "000",
data_in(1) when "001",
data_in(2) when "010",
data_in(3) when "011",
 data_in(4) when "100",
data_in(5) when "101",
data_in(6) when "110",
data_in(7) when "111",
'U' when others;
end arch_mux8x1 ;
---------------------------------------------------------------------
Program No2(B): 8x1 MUX BEH style
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity mux8x1 is
port ( S : in STD_LOGIC_VECTOR(2 downto 0);
data_in : in STD_LOGIC_VECTOR(7 downto 0); -
Y : out STD_LOGIC )
end mux8x1;

architecture arch_mux4in8 of mux4in8 is

begin
process(S, data_in)
begin
case S is
when “000” => Y <= data_in(0) ;
when “001” => Y <= data_in(1) ;
when “010” => Y <= data_in(2) ;
when “011” => Y <= data_in(3) ;
when “100” => Y <= data_in(4) ;
when “101” => Y <= data_in(5) ;
when “110” => Y <= data_in(6) ;
when “111” => Y <= data_in(7) ;
when others => Y <= ‘U’) ;
end case ;
end process;
end arch_mux4in8 ;
---------------------------------------------------------------------
Program No3: 4-bit comparator BEH style
---------------------------------------------------------------------
Library IEEE;
Use IEEE.stllogic_1164.all
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity comparator_4bit is
port( A, B : in STD_LOGIC_VECTOR(3 downto 0);
EQ, NE, GT, GE, LT, LE : out STD_LOGIC );
end comparator_4;

architecture arcg_4bitcomp of comparator_4 is

begin
process (A, B)
begin
EQ <= ' 0 ' ;
 NE <= '0';
GT <= '0';
GE <= '0';
LT <= '0';
LE <= '0';

If A=B then EQ <= ‘1’; end if ;

If A /=B then NE <= ‘1’; end if ;
If A > B then GT <= ‘1’; end if ;
If A>= B then GE <= ‘1’; end if ;
If A<B then LT < = ‘1’; end if ;
If A <= B then LE <= ‘1’; end if ;
end process;
end arch_4bitcomp
-------------------------------------------------------------------
Program 4: 1x8 DE-Multiplexer(BEH Style)
-------------------------------------------------------------------
Library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity demux1x8 is
port ( S : in STD_LOGIC_VECTOR(2 downto 0); --- sel lines
data_in : in STD_LOGIC;
Y : out STD_LOGIC_VECTOR(7 downto 0)
end mux8x1;

architecture arch_demux8x1 of demux8x1 is

begin
process(S,data_in)
begin
case S is
when “000” => Y(0) <= data_in ;
when “001” => Y(1) <= data_in ;
when “010” => Y(2) <= data_in ;
when “011” => Y(3) <= data_in ;
when “100” => Y(4) <= data_in ;
when “101” => Y(5) <= data_in ;
when “110” => Y(6) <= data_in ;
when “111” => Y(7) <= data_in ;
when others => Y(7 downto 0) <= (others =>‘U’) ;
end case ;
end process;
end arch_demux8x1 ;
---------------------------------------------------------------------
Program 5: Positive Edge Triggered D-FF with asyncronous clear (BEH Style)
---------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity PosedgeDff is
port( CLK, CLR, D : in std_logic;
 Q, QN, : out std_logic) ;
end PosedgeDff;

architecture arch_PosedgeDff of PosedgeDff is

begin
process(CLK,CLR)
begin
if (CLR='1' then Q <= '0'; QN <= '1')
elsif (CLK'event and CLK='1') then
Q <= D ;
QN <= not D ;
end if ;
end process ;
end arch_PosedgeDff;
-------------------------------------------------------------------
Program 6: 4-bit UP counter with enable signal and asynchronous RESET
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity AsynCounter4 is
port( CLK, RESET, EN : in std_logic;
count : out std_logic_vector(3 downto 0) ) ;
end AsynCounter4;

architecture arch_AsynCounter4 of AsynCounter4 is

signal count_t : std_logic_vector(3 downto 0) ;
begin
process(RESET,CLK)
begin
if (RESET = '1') then count_t <= "0000" ;
elseif (CLK'event and (CLK='1') and (EN = '1') then
count_t <= count_t + "0001" ; ------ statement number (1)
end if ;
end process ;
count <= count_t ;
end arch_AsynCounter4;
-----------------------------------------------------------------------------------
Program 7: 4-bit UP DECADE counter with enable signal and asynchronous RESET
-----------------------------------------------------------------------------------
Same as above with the addition of the following line after the statement number (1)
If (count_t = "1001") then count_t <= "1001"; end if;
-----------------------------------------------------------------------------------
Program 7-A: 4-bit DOWEN DECADE counter with enable signal and asynchronous RESET
-----------------------------------------------------------------------------------
--- THIS IS EASY IF U UNDERSTAND DOWN COUNTER
-------------------------------------------------------------------
Program 8: 8-bit shift register with Asynchronous CLEAR
-------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
entity shftreg is
port ( CLK, CLR, RIN, LIN: in STD_LOGIC;
S: in STD_LOGIC_VECTOR(2 downto 0); --function select
D: in STD_LOGIC_VECTOR(7 downto 0); --data in
Q: out STD_LOGIC_VECTOR(7 downto 0) -- data out
end Vshftreg;

architecture arch_Vshftreg of Vshftreg is

signal IQ: STD_LOGIC_VECTOR (7 downto 0);
begin
process (CLK, CLR, IQ)
begin
if (CLR='1') then IQ <= (others=>'0'); — Asynchronous clear
elsif (CLK'event and CLK='1') then
case CONV_INTEGER(S) is
when 0 => null; -- Hold
when 1 => iq<= D; -- Load
when 2 => iq<= RIN & D(7 downto 1); --Shift right
when 3 => iq<= D(6 downto 0) & LIN; -- Shift left
when 4 => iq<= D(o) & D(7 downto 1); -- Shift circular right
when 5 => iq<= D(6 downto 0) & D(7); -- Shift circular left
when 6 => iq<= D(7) & D(7 downto 1); -- Shift arithmetic right
when 7 => iq <= D(6 downto 0) & '0'; -- Shift arithmetic left
when others => null;
End case;
end if;
q <= IQ;
end process;
end Vshftreg_arch;
--------------------------------------------------------------------
Prohram 9: 8x4 SRAM Behavioral style Program with enable signal
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SRAM8x4 is
generic( width: integer:=4;
depth: integer:=8;
addr: integer:=3);
port( Clock: in std_logic;
Enable: in std_logic;
Read: in std_logic;
Write: in std_logic;
Read_Addr: in std_logic_vector(addr-1 downto 0);
 Write_Addr: in std_logic_vector(addr-1 downto 0);
Data_in: in std_logic_vector(width-1 downto 0);
Data_out: out std_logic_vector(width-1 downto 0) );
end SRAM8x4;

architecture behavRAM of SRAM8x4 is

-- use array to define the bunch of internal temparary signals
type ram_type is array (0 to depth-1) of std_logic_vector(width-1 downto 0);
signal tmp_ram: ram_type;
begin
process(Clock, Read) -- Read Functional Section
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Read='1' then
-- buildin function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
end if;
end process;
process(Clock, Write) ---- Write Functional Section
begin
if (Clock'event and Clock='1') then
if Enable='1' then
if Write='1' then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end behavRAM;
----------------------------------------------------------------
Program 10: 32*8 ROM module beh style
--------------------------------------------------------------
-- ROM model has predefined content for read only purpose
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity ROM is
port( Clock : in std_logic;
Reset : in std_logic;
Enable : in std_logic;
Read : in std_logic;
Address : in std_logic_vector(4 downto 0);
Data_out: out std_logic_vector(7 downto 0) );
end ROM;
architecture Behav of ROM is
type ROM_Array is array (0 to 31) of std_logic_vector(7 downto 0);
constant Content: ROM_Array := (
0 => "00000001", -- Suppose ROM has
1 => "00000010", -- prestored value
2 => "00000011", -- like this table
3 => "00000100",
4 => "00000101",
5 => "00000110",
6 => "00000111",
7 => "00001000",
8 => "00001001",
9 => "00001010",
OTHERS => "11111111" );
begin
process(Clock, Reset, Read, Address)
begin
if( Reset = '1' ) then Data_out <= "ZZZZZZZZ";
elsif( Clock'event and Clock = '1' ) then
if Enable = '1' then
if( Read = '1' ) then
Data_out <= Content(conv_integer(Address));
else
Data_out <= "ZZZZZZZZ";
end if;
end if;
end if;
end process;
end Behav ;
--------------------------------------------------------------
Program 11: 16 Bytes deep x 8bit FIFO BEH style
-------------------------------------------------------------
LIbrary IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
Entity fifo is
Port (
Clk : in std_logic;
Reset : in std_logic;
WriteEnable : in std_logic;
ReadEnable : in std_logic;
DataIn : in std_logic_vector(7 downto 0);
DataOut : out std_logic_vector(7 downto 0);
FifoEmpty : out std_logic;
FifoFull : out std_logic );
END fifo;-- entity declarations ends
Architecture A_fifo of fifo is
Component Rams
Port (
Writeen : in std_logic;
Wclk : in std_logic;
 Datain : in std_logic_vector(7 downto 0);
Addr : in std_logic_vector(3 downto 0);
Dataout : out std_logic_vector(7 downto 0) );
END Component;
Signal ReadPointer : std_logic_vector(3 downto 0);
Signal WritePointer : std_logic_vector(3 downto 0);
Signal ByteCounter : std_logic_vector(4 downto 0);

Signal WriteEnable_s : std_logic;

Signal Addr_s : std_logic_vector(3 downto 0);
Signal FifoFull_s : std_logic;
Signal FifoEmpty_s : std_logic;
Begin
FifoRam : Rams
Port map (
Writeen => WriteEnable_s,
Wclk => Clk,
Datain => DataIn,
Dataout => DataOut,
Addr => Addr_s
);
ReadWriteFifoOut : Process(Clk,Reset)
Begin
IF ( Reset = '1') then
ReadPointer <= "0000";
WritePointer <= "0000";
ByteCounter <= "00000";
ELSIF(Clk'event and Clk = '1') then
IF ( WriteEnable = '1' and FifoFull_s = '0' and
ReadEnable = '0') then
WritePointer <= WritePointer + 1;
ByteCounter <= ByteCounter + 1;
END IF;
IF ( ReadEnable = '1' and FifoEmpty_s = '0'
and WriteEnable = '0') then
ReadPointer <= ReadPointer + 1;
ByteCounter <= ByteCounter - 1;
END IF;
END IF;
END process; ---- ReadWriteFifo Process ends
-------------------
-- Combinatorial Logic
--------------------
FifoEmpty_s <= '1' when ( ByteCounter = "0000") else '0';
FifoFull_s <= ByteCounter(4);
FifoFull <= FifoFull_s;
FifoEmpty <= FifoEmpty_s;
WriteEnable_s <= '1' when ( WriteEnable = '1' and FifoFull_s = '0') else '0';
Addr_s <= WritePointer when ( WriteEnable = '1') else dReadPointer;
-------------
END A_fifo; --Architecture Ends
-------------------------------------------------------------------