1

IIT-Bombay, EE618, Course Assignment 1

Due date: Wednesday, 20
th
Aug. , 2014, 6pm
NOTE: There is NO late submission option.

Instructor: M. Shojaei Baghini

Technology: 180nm CMOS, Vdd=1.8V and Vss=0V.
Model file: RUN: T77A (MM_NON-EPI_THK-MTL) from TSMC, available from MOSIS website

Simulator: NGSPICE
Note: Include circuit schematics (using XCircuit) and netlists in your report. Use proper
labels (no numbers) for wires.

1.a [2 4 =8 marks]
Plot I
D
(V
DS
) with V
GS
as a parameter and I
D
(V
GS
) with V
DS
as a parameter for NMOS and PMOS
transistors, two sets each, one set for L=180nm, W=2m and one set for L=2m and
W=2m.
Plot two I
D
(V
GS
) graphs: one in linear scale and one in logarithmic scale.
1.b [2 2 =4 marks]
Derive subthreshold slope and typical output resistance of each transistor (four different
transistors given in 1.a). Show the details on each graph.
1.c [4 1 =4 marks]
Obtain f
T
of a single PMOS and a single NMO transistor with L=180nm and biased in the
saturation region with gate overdrive of 300 mV (choose W/L as per your choice). Compare
simulated value of f
T
for each transistor with the corresponding calculated value.
1.d [2 2 =4 marks]
Calculate maximum achievable voltage gain of a simple common-source amplifier. Design
such amplifier and compare its simulated gain with the calculated value.
[Total: 24 marks=8 +4 +4 +4 +4 marks (for schematics and netlists)]