--Divisor de frecuencia de 50MHz a 1Hz para parpadeo de LED

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity clk1Hz is
Port (
clk50Mhz: in STD_LOGIC;
reset : in STD_LOGIC;
giro : in STD_LOGIC;
half : in STD_LOGIC;
veloc_in : in STD_LOGIC;
salida : out STD_LOGIC;
full : out STD_LOGIC;
inversion : out STD_LOGIC;
led : out STD_LOGIC;
r : out STD_LOGIC
);
end clk1Hz;

architecture Behavioral of clk1Hz is
signal pulso: STD_LOGIC;
signal giro_s: STD_LOGIC;
signal reset_s : STD_LOGIC;
signal half_s: STD_LOGIC;
signal velocidad: integer range 0 to 999999 := 0;
signal contador: integer range 0 to 999999 := 0;--40mhz
begin
divisor_frecuencia: process (reset, clk50Mhz) begin
if (reset = '0') then
reset_s <= '0';
pulso <= '0';
contador <= 0;
elsif rising_edge(clk50Mhz) then
reset_s <= '1';
if (veloc_in = '0') then
velocidad <= 49999;
else
velocidad <= 999999;
end if;
if (contador = velocidad) then
pulso <= NOT(pulso);
contador <= 0;
else
contador <= contador+1;
end if;
end if;
end process;

process (giro) begin
if (giro = '0') then
giro_s <= '0';

else
giro_s <= '1';

end if;
end process;

process (half) begin
if (half = '0') then
half_s <= '0';

else
half_s <= '1';

end if;
end process;

led <= pulso;
salida <= pulso;
inversion <=giro_s;
full <=half_s;
r <= reset_s;

end Behavioral;



# PlanAhead Generated physical constraints

NET "clk50Mhz" LOC = C9;
NET "full" LOC = D5;
NET "giro" LOC = H18;
NET "half" LOC = L14;
NET "inversion" LOC = B4;
NET "led" LOC = F12;
NET "reset" LOC = L13;
NET "salida" LOC = A4;
NET "r" LOC = C5;
NET "veloc_in" LOC = N17;