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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity stepper is
Port ( clk : in STD_LOGIC;
sw : in STD_LOGIC;
op1 : out STD_LOGIC;
op2 : out STD_LOGIC;
op3 : out STD_LOGIC;
op4 : out STD_LOGIC);
end stepper;
architecture Behavioral of stepper is
type state1 is (ready1,b01,b02,b03);
signal ps1 : state1 := ready1;
begin
process(clk,sw)
variable i: integer := 0 ;
begin
if clk'event and clk = '1' then
if sw = '1' then
if ps1 = ready1 then
i := i + 1;
if i = 50000 then
op1 <= '0' ;
op2 <= '0' ;
op3 <= '0' ;
op4 <= '1' ;
ps1 <= b01;
i := 0;
end if;
end if;
if ps1 = b01 then
i := i + 1;
if i = 50000 then
op1 <= '0' ;
op2 <= '0' ;
op3 <= '1' ;
op4 <= '0' ;
ps1 <= b02;
i := 0;
end if;
end if;

if ps1 = b02 then


i := i + 1;
if i = 50000 then
op1 <= '0' ;
op2 <= '1' ;
op3 <= '0' ;
op4 <= '0' ;
ps1 <= b03;
i := 0;
end if;
end if;
if ps1 = b03 then
i := i + 1;
if i = 50000 then
op1 <= '1' ;
op2 <= '0' ;
op3 <= '0' ;
op4 <= '0' ;
ps1 <= ready1;
i := 0;
end if;
end if;
end if;
end if;
end process;
end Behavioral;

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY simu_steper IS
END simu_steper;
ARCHITECTURE behavior OF simu_steper IS
-- Component Declaration for the Unit Under Test (UUT)

COMPONENT stepper
PORT(
clk : IN std_logic;
sw : IN std_logic;
op1 : OUT std_logic;
op2 : OUT std_logic;
op3 : OUT std_logic;
op4 : OUT std_logic
);
END COMPONENT;
--Inputs
signal clk : std_logic := '0';
signal sw : std_logic := '0';
--Outputs
signal op1 : std_logic;
signal op2 : std_logic;
signal op3 : std_logic;
signal op4 : std_logic;
-- Clock period definitions
constant clk_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: stepper PORT MAP (
clk => clk,
sw => sw,
op1 => op1,
op2 => op2,
op3 => op3,
op4 => op4
);
-- Clock process definitions
clk_process :process
begin
clk <= '0';
wait for clk_period/2;
clk <= '1';
wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100000 ns;
wait for clk_period*10;
-- insert stimulus here
wait;
end process;
END;

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