MA

(m0...mN-1)

MAIO
(0...N-1)

FN
T3 (0...50)

NBIN bits

HSN
(0...63)

6 bits

FN
T1 (0...2047)

6 bits

FN
T2 (0...25)

11 bits
T1R =
T1 MOD 64

5 bits
Represent
in 7 bits

6 bits

7 bits

Exclusive OR
6 bits
Addition
7 bits
Look-up table
7 bits
Addition
8 bits
T=
T3 MOD 2^NBIN

M' = M MOD 2^NBIN

NBIN bits

NBIN bits
N

S = (M' + T) MOD N

M' < N

S = M'

NBIN bits
MAI = (S + MAIO) MOD N
NBIN bits
ARFCN = MA (MAI)

ARFCN

where NBIN = INTEGER((Log base 2 of N) + 1)

MOD = MODULO
^ = raised to the power of

Figure 6: Block diagram of the frequency hopping algorithm when HSN 0

Add mod 2

Add mod 2

b0

b1

Add mod 2

b2

b3

b4

b5

b6

a2

v0

b7

a0

v1

b8

b9

b10

a1

v2

b11

b12

b13

b14

b15

a3

v3

modified codeword

Add mod NF

Counter
mod NF
TFHC2

Shift register clock

Counter
mod NF TDMA frame clock
TFHC1

Add mod NF

TFHC1

Figure 6a: General structure of hopping sequence generation for CTS

NOTE:

Example with vector a = (a0, a1, a2, a3) = (5, 8, 2, 11).