TRNG I HC BCH KHOA

TP.H CH MINH
------

Thnh vin nhm:

inh Xun Tu

MSSV:
41104041

Mnh Thng
Nguyn c Bnh

41100298

Nguyn Hu Thnh

41003060

Bi 1: Th nghim vi LED n
Chp tt n p1.0 vi chu k l 500ms
Thut ton: to vng lp lin tc chp tt n vi chu k l 500ms
Lu thut ton:
ORG

CPL P1.0 ;Chp

n P1.0

DELAY 500ms

Source code:
ORG

2000H

LAP:
CPL
CALL
SJMP
DL500:
PUSH
PUSH
PUSH
MOV
L2:
MOV
L1:
MOV
DJNZ
DJNZ
DJNZ
POP

P1.0
DL500
LAP

;thay i trng thi p1.0 sang trng thi ngc li

;gi delay 500ms n sng c lu
;quay tr li chng trnh n c chp lin tc

05
06
07
R5, #10

;chng trnh delay 500s

;t ct gi tr thanh ghi r5 r6 r7 vo ngn xp

R6, #100

;gn r6 = 100

R7, #250
R7, $
R6, L1
R5, L2

;gn r7 = 250

07

;gn r5 = 10

;thc hin 10x100x250x2

; chu k my (1 chu k 1us)
;ly li gi tr r7 lu trong

;ngn xp bo tn gi tr
; ( theo quy tc ct trc th ly sau)
POP
POP
RET

06
05

END

Bi 2: Th Nghim Hin Th LED

Hin th n LED t 0 n 9 sau lp li.
Thut ton: s dng thanh ghi DPTR kt ni LED bng cch move a ch thanh
ghi DPTR vo a ch #0000H. La chn n LED no sng vo hin th gi tr s no
bng cch gn ni dng vo thanh ghi DPTR ( l @DPTR) (s dng 8 bit). 4 bit
u quy nh led no s sng 4 bit sau quy nh s s sng.
VD: chn LED s 4 th LED s 4 phi mc thp: 1110E, hin th s 0 th ni
dng @DPTR phi l #0E0H
Tng t: LED 3 hin th s 2: 1101 0010 @DPTR l #0D2H
LED 2 hin th s 1: 1011 0001 @DPTR l #0B2H
S dng vng lp tng gi tr ln. Dng delay iu chnh thi gian thi hnh chm li
c th lu nh trong mt ngi quan st. ng thi kim tra nu qu 9 s tr li v
0 (s dng CJNE)
Lu thut ton:
ORG

DPTR#0000H
A#0E0H

@DPTRA
DELAY
INC A

A>9

Source code:

AGAIN:
NEXT:

ORG
MOV
MOV
MOVX
DPTR
LCALL
INC
CJNE

SJMP

DELAY:
LAP1:

MOV
MOV
MOV
MOV
SETB
JNB
CLR
CLR
DJNZ
RET
END

2000H
DPTR,#0000H
A, #0E0H
@DPTR, A

; truy xut n LED

;gn A l 1110 0000B
;a A vo ni dung thanh ghi

;( bng cch mov vo @DPTR)

DELAY
;Gi delay c thi gian ch lu
;nh trong mt.
A
;Tng gi tr A ln m n 9
A, #0EAH, NEXT
;Kim tra xem c
;vt qu 9 khng
; nu khng vt th tip tc quay li
;hin th ri tng A
AGAIN
;tr li hin th t 0

R7,#10
;vng lp delay s dng timer 1
TMOD,#01H
TH0,#HIGH(-50000)
TL0,#LOW(-50000)
TR0
TF0,$
TR0
TF0
R7,LAP1

Bi 3:Th Nghim Hin Th LCD

Hin th ch HELLO trn mn hnh LCD
Thut ton: -S dng thanh ghi DPTR kt ni LCD bng cch move a ch thanh
ghi DPTR vo a ch #8000H
-Vit 2 chng trnh con:

+Th nht: chng trnh con nhn lnh truyn n thc hin (WRITE). nhn
lnh th ta phi setb p3.4 v clr p3.5. Chng trnh ny gip LCD nhn lnh t my
nh xa mn hnh LCD, hin th kiu no, con tr u.v..v
+Th hai: chng trnh nhn k t xut ra LCD hin th (WRITE_TEXT). nhn
chui k t ta phi setb p3.4 v c p3.5.
-Vit chng trnh con khi ng LCD (tn l LCD) vi ph bin l truyn 3
lnh sau:
+#06H: hin th tng v khng shift
+#0EH: hin th cursor nhng khng hin th blinking
+#38H: giao tip 8 bit, 2 dng vi font 5x8
-Vit chng trnh con ly k t t bng (l chui k t mun hin th) (chng
trnh con BANG).
-Vit chng trnh con delay to tr. c th xut hin tng ch mt
trn LCD.
-Chng trnh chnh:
+Khi ng LCD.
+Xa mn hnh ang hin th trn LCD bng cch truyn lnh #01H.
+To vng lp hin th tng ch mt trn LCD bng cch tra bng.

Lu thut ton:

ORG

DPTR#8000H
CALL LCD ; khi ng LCD
A#01H
CALL WRITE ;xa mn hnh
R5#5
A#0
R4#0

CALL BANG
CALL WRITE_TEXT
R4R4+1
AR4
R5R5-1

R5=0

SJMP $
; lp
ti ch chng
trnh khng kt thc

Source code:
ORG
MAIN:
MOV
CALL
MOV

2000H
DPTR , #8000H
LCD
A,#01H

CALL

WRITE

MOV

R5,#5

MOV
MOV
LAP: CALL
CALL
INC
MOV
DJNZ
SJMP

BANG:
MOV
MOVC
RET

;Truy xut n LCD

;Khi ng LCD ci t thng s cn thit
;cho A=#01H truyn lnh vo
;LCD xa mn
; hnh LCD

;To vng lp 5 ln ng vi
;ch HELLO c 5 k t
A,#0
;Khi to A bng u t k t th nht
R4,#0
;Khi to bin m tng gi tr A
; (v A d thay i trong qu trnh lm)
BANG
;Gi bng mang k t
WRITE_TEXT
;Hin th ln LCD
R4
;Tng bin m R4 gn vo A
A,R4
R5,LAP
;Gim R5 ri quay li
$
;Lp ti ch khng lm
; tip cu lnh tip theo

DPTR,#TABLE
A,@A+DPTR

;gi bng
;Gn vo A k t th A ca chui k t

MOV

A,#38H

;Khi ng LCD
;truyn lnh cho LCD giao tip 8 bit,
; 2 dng vi font 5x8

LCALL
MOV

WRITE
A,#0EH

LCALL
MOV

WRITE
A,#06H

LCALL
RET

WRITE

LCD:

WRITE_TEXT:
MOV
SETB

DPTR,#8000H
P3.4

;truyn lnh cho LCD hin th cursor nhng

;khng hin th blinking
; truyn lnh cho LCD hin
;th tng, khng shift

;hin th k t trong thanh ghi A bng LCD

;Truy xut n LCD
;Khi ng ch

SETB
MOVX

P3.5
@DPTR,A

CLR
LCALL
RET

P3.4
WAIT

WRITE:
MOV
SETB
CLR

DPTR,#8000H
P3.4
P3.5

MOVX

@DPTR,A

CLR
LCALL
RET

P3.4
WAIT

WAIT:
PUSH
PUSH
MOV
LAP1:
MOV
DJNZ
DJNZ
POP
POP
RET

;Bt ch nhn k t hin th ra LCD

;Nhn k t qua t thanh ghi A vo ni dung
; DPTR (l @DPTR)
; hin th
;Kt thc ch

07

;nhn lnh t thanh ghi A vo LCD

;Truy xut n LCD
;khi ng ch
;Bt ch nhp lnh t
;thanh ghi A vo LCD
;Nhn lnh t thanh ghi A vo
; ni dung DPTR (l @DPTR)
;Kt thc ch

;to thi gian delay nhn lnh, hay tc

; hin k t trn LCD

06
R7,#250
R6,#250
R6,$
R7,LAP1
06
07

TABLE:
DB 'HELLO'
END

;Bng cha chui k t mun hin th trn LCD

4) Giao Tip Qua Cng Ni Tip:

L thuyt c bn:
V c bn, phn cng c trong gio trnh. Phn ny ta s dng thm hin th LCD
c ni th nghim trc.
Lu : xc nh chnh xc tc baud. Trn LCD do hin th c 2 hng mi hang 16
k t, nhng thc t th
Yu Cu: Vit chng trnh nhp 1 k t t cng ni tip hin th ln CLD ng thi
pht ra cng ni tip.

Lu gii thut:

ORG

Khi to cc gi tr cho:
1. SCON
2. TMOD
3.
LCD

Gi chng trnh con nhp d

liu.

Xut d liu ln LCD v cng

ni tip.

Yes

No
Nhp k t na
hay khng.

Code:
ORG

2000H

MOV

SCON,#52H

; cng ni tip , ch 1

MOV

TMOD,#20H

; time 1 mode 2

MOV

TH1,#-3

; Tr np cho 19200 baud

SETB

TR1

; cho time 1 chy

MOV

A,#01H

; xa mn hnh LCD

CALL

WRITE

MOV

DPTR,#8000H

Nhy ti ch ch
lnh k tip.

CALL

LCD

CALL

IN

CALL

WRITE_TEXT

CALL

OUT

SJMP

LAP

SJMP

LAP:
; Gi chng trnh con nhp d liu vo.

; Gi chng trnh con xut d liu ra.

;================
;============================
;======= Cc chng trnh con.

OUT:
JNB

TI,$

; Ch pht xong byte trc

CLR

TI

;Chun b pht byte k tip.

MOV

SBUF,A

;Pht

JNB

RI,$

;Ch nhn xong 1 byte

CLR

RI

;Nhn byte k tip

MOV

A,SBUF

; Chuyn byte k tip vo trong A

RET
IN:

RET
;================================
;=====================================
;=== Di y l phn giao tip vi LCD c ni mc trc.
LCD: MOV

A,#38H

LCALL

WRITE

MOV

A,#0EH

LCALL

WRITE

MOV

A,#06H

LCALL

WRITE

RET

WRITE_TEXT:
MOV

DPTR,#8000H

SETB

P3.4

SETB

P3.5

MOVX

@DPTR,A

CLR

P3.4

LCALL

WAIT

RET

WRITE:
MOV

DPTR,#8000H

SETB

P3.4

CLR

P3.5

MOVX

@DPTR,A

CLR

P3.4

LCALL

WAIT

RET
WAIT:
MOV

R7,#4

LAP1:
MOV

R6,#250

DJNZ

R6,$

DJNZ

R7,LAP1

RET
END

5) iu Khin ADC:
L thuyt c bn:
V c bn, phn cng c trong gio trnh. Phn ny ta s dng thm hin th
LCD c ni th nghim trc. Tuy nhin lu thm v hot ng v thit k
ca ADC0809 c nu trong gio trnh.
Lu :
Lu cc lnh giao tip vi ADC.
Cch hin th s nh phn (hin ang th hin gi tr thp phn ).
Yu cu: Vit chng trnh thc hin c in p knh 0 v hin th ln LCD.
Lu gii tht:

ORG 2000H

Kt hp a ch ADC vi knh
Lnh chuyn i knh
Delay

Ly d liu t ADC ra ct vo thanh ghi

A
Nhn A vi 5.
Hin th hang n v .
Nhn gi tr hang thp phn th nht vi
10
Hin th gi tr thp phn th nht.
yes

no
Gi tr c thay
i

Nhy ti ch

Lu : Lu gii thut ca LCD c ni ti phn LCD.

CODE v ch thch:
ORG

2000H

MOV

A,#01H

CALL

WRITE

MOV

DPTR,#8000H

CALL

LCD

MOV

A,#01H

CALL

WRITE

MOV

DPTR,#4000H

LAP:
;xa man hnh LCD

;Giao tip vi ADC a ch

; ADC vi knh
;Lnh chuyn i knh tng ng

MOVX

@DPTR,A

MOV

R7,#50

DJNZ

R7,$

MOVX

A,@DPTR

MOV

B,#05H

MUL

AB

; thc hin php nhn A.B

MOV

R3,A

; bit thp vo R3

MOV

A,B

;bit cao chuyn vo A

MOV

DPTR,#TABLE

; hin th s. Giao tip vi LCD

MOVC

A,@A+DPTR

CALL

WRITE_TEXT

MOV

A,#'.'

CALL

WRITE_TEXT

MOV

B,#10

;Delay rt quan trng i gi tr ca ADC

; c ngoi vi ly gi tr

; chuyn 10 vo B

MOV

A,R3

; Ly bit thp

MUL

AB

; Hin th ch s thp phn th nht

; sau du phy

MOV

A,B

;chuyn bit cao vo A

MOV

DPTR,#TABLE

; Hin th s. Giao tip vi LCD

MOVC

A,@A+DPTR

CALL

WRITE_TEXT

CALL

WAIT

MOV

A,#'V'

CALL

WRITE_TEXT

CALL

WAIT

SJMP

LAP

SJMP

;==============================
;====================================
;===== Cc chng trnh con giao tip vi LCD ni phn trc
LCD: MOV

A,#38H

LCALL

WRITE

MOV

A,#0EH

LCALL

WRITE

MOV

A,#06H

LCALL

WRITE

RET
WRITE_TEXT:
MOV

DPTR,#8000H

SETB

P3.4

SETB

P3.5

MOVX

@DPTR,A

CLR

P3.4

LCALL

WAIT

RET

WRITE:
MOV

DPTR,#8000H

SETB

P3.4

CLR

P3.5

MOVX

@DPTR,A

CLR

P3.4

LCALL

WAIT

RET

WAIT:
PUSH

07

PUSH

06

MOV

R7,#4

LAP1: MOV

R6,#250

DJNZ

R6,$

DJNZ

R7,LAP1

POP

06

POP

07

RET
XUAT:
MOV

DPTR,#0000H

MOV

X @DPTR,A

RET
TABLE:
END

DB 030H,031H,032H,033H,034H,035H,036H,037H,038H,039H

6) Th nghim giao tip cm bin nhit

BI :Vit chng trnh o v hin th nhit ln LCD
CHUN B:
-

Cch s dng giao thc 1-Wire

Datasheet DS18S20
Cc chng trnh con lin quan ti LCD cc bi trc

Mt vi ch trc khi vit code

nh dng thanh ghi nhit .

Bit S y ng vai tr l bit du.

Tuy nhin bi ton ca chng ta l o nhit phng. Nn mnh xin php b qua bit
du lun cho n l 0 ( tc nhit lun dng). Ta ch xt 8 bit thp qui nh gi tr
ca nhit phng. M im lu na l v nhit phng nn b qua vic so snh
vi gi tr TH,TL v nhit phng ta th nghim lun nm trong khong m 55 C
ti dng 85 C
Bi ny ta s truy xut vi DS18S20 thng qua port P3.2

S nh th khi ng DS1820. Dng chng trnh con RESET _DS1820

Theo s th ta s to 1 xung reset 50% chu k khong 1ms bng cch.
ban u CLR P3.2 sau delay khong 500 s. Set bit P3.2 delay tng ng 500 s

S nh th khe thi gian c/ghi

Hnh 1 dng nh th thi gian ghi. Dng cho chng trnh con WRITE_TIME
SLOT.theo s thi gian clear P3.2 l khong 60 s. thi gian set l khong 2 s

Hnh 2 dng nh th thi gian c. Dng cho chng trnh con READ_TIME
SLOT. Theo s thi gian clear P3.2 khong 15 s. set l 45 s. nhng thc t khi
vit code n khng chy ng tham kho ti liu m mnh t my m dnh th li th
mnh nh th nh trong chng trnh con th li chy n.
cc lnh NOP y gip to thi gian delay hon tt vic nhn bit. S lnh NOP
do ta t nh th. Vic nh th l cng vic kh khn nht y !
Vi c th kit ch c 1 cm bin nhit nn ta ch s dung 1 s lnh RO M v chc
nng sau
lnh ROM:
- SKIP ROM (CCh)
Lnh ny cho php thit b iu khin truy nhp thng n cc lnh b nh ca
DS1820 m khng cn gi chui m 64 bit ROM. Nh vy s tit kim c thi gian
ch i nhng ch mang hiu qu khi trn bus ch c mt cm bin.
Lnh chc nng DS1820
- CONVERT T (44h)
Lnh ny khi ng mt qu trnh o v chuyn i gi tr nhit thnh s (nh
phn). Sau khi chuyn i gi tr kt qu o nhit c lu tr trn thanh ghi nhit
2 byte trong b nh nhp Thi gian chuyn i khng qu 200 ms, trong thi gian
ang chuyn i nu thc hin lnh c th cc gi tr c ra u bng 0.
- READ SCRATCHPAD (BEh)
Lnh ny cho php thit b ch c ni dung b nh nhp. Qu trnh c bt u t bit
c ngha nht ca byte 0 v tip tc cho n byte rh 9 (byte 8 CRC). Thit b ch
c th xut ra mt xung reset lm dng qu trnh c bt k lc no nu nh ch c
mt phn ca d liu trn b nh nhp cn c c.

ORG
2000

To xung reset xc nhn s c

mt ca cm bin

Gi lnh SKIP ROM

Truy xut thng ti DS1820

Cu trc 1 ln truy xut

DS18S20 gm 3 lnh.
To 1 xung reset

Gi lnh CONVERT T
Ra lnh bt u chuyn i
nhit

To xung reset

Gi lnh SKIP ROM

Gi lnh READ SCRATCHPAD

c ni dung b nh nhp cha gi tr
nhit

Gi chng trnh READ BYTE

c gi tr nhit khi cm bin v
lu trn thanh ghi A

Xut gi tr ra
LCD

1 lnh ROM
1 lnh chc nng

V d : gi s mun thao tc lnh SKIP ROM vi DS18S20.

Thanh ghi A cha gi tr 44H
Nhim v ca write_time _slot:

P3.2

Chuyn 1 bit d liu t C vo P3.2. khi mun truy xut lnh SKIPROM th ta s
chuyn dn tng bit m lnh ca SKIPROM l 44H vo P3.2 thng qua c C

Nhim v ca Read_time_slot:

P3.2

c 1 bit d liu t P3.2 ra C . khi c d liu ra thanh ghi A. ta cng thc hin tng
t c dn tng bit thng qua c C.

SOURCE CODE
ORG 2000H
; gn dng R2 nh l thanh ghi m

DEM

EQU R2

JMP

CHUONG_TRINH_CHINH

WRITE_TIME_SLOT:
CLR

P3.2

; chng trnh ghi tng bit vo DS18S20

; thng qua cng P3.2

NOP
NOP
MOV

P3.2, C

MOV

R5, #30

LCALL

DELAY

SETB

P3.2

NOP
NOP
RET
READ_TIME_SLOT:
CLR
NOP
NOP

P3.2

; chng trnh c tng bit t DS1820 ra c C

; thng qua bit P3.2

SETB

P3.2

NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
MOV

C,P3.2

MOV

R5,#50

LCALL

DELAY

RET
RESET_DS1820:

; to xung reset pht hin s c

; mt ca slave(DS18S20)

CLR

P3.2

MOV

R5,#255

LCALL

DELAY

SETB

P3.2

MOV

R5,#255

LCALL

DELAY

RET
; chng trnh gi lnh iu

WRITE_BYTE:

; khin DS1820
MOV

DEM,#8

; gn gi tr m l 8.
;Tc l ta dch 8 bit

WRITE_LAI:
RRC

LCALL

WRITE_TIME_SLOT

DJNZ

DEM, WRITE_LAI

SETB

P3.2

MOV

R5,#50

LCALL

DELAY

RET
;chng trnh gi lnh c

READ_BYTE:

; tng bit d liu

DEM,#8

; cha gi tr nhit

LCALL

READ_TIME_SLOT

; c 1 bit lu vo c C

RRC A

MOV
READ_LAI:

DJNZ

DEM,READ_LAI

dch bit t c C vo A
; thc hin ln lt 8 ln ng
;vi 8 bit

MOV

R5,#50

;delay 100s dm bo
;hon tt vic dch bit

LCALL

DELAY
; kt thc chng trnh con gi

RET

; tr nh phn nhit lu A
;chng trnh delay R5*2 micro giy

DELAY:
DJNZ

R5,$

RET
DELAY_LONG:

; delay di delay 2*255*R5

;micro giy

MOV

R6,#0FFH

DELAY_LAI:
LCALL

DELAY

DJNZ

R6, DELAY_LAI

RET

CHUONG_TRINH_CHINH:
;=======xa mn hnh LCD========
MOV

DPTR,#8000H

CALL

LCD

LAP: MOV

A,#01H

;===========================
CALL

WRITE

SETB

P3.2

;set bit P3.2 bt u thao

; tc vi DS18S20

AGAIN:
LCALL

RESET_DS1820

;gi chng trnh to xung reset

MOV

A,#0CCH

; gi lnh SKIP ROM.

; Truy xut thng

LCALL

WRITE_BYTE

; ti DS1820 v y
;ch c 1 cm bin

MOV

A,#44H

; lnh CONVERT T

LCALL

WRITE_BYTE

; bt u chuyn i nhit
; sang nh phn

LCALL

RESET_DS1820

; xong 1 ln truy xut

;phi reset i ln k
; tng t trn gi SKIP ROM

MOV

A,#0CCH

LCALL

WRITE_BYTE

MOV

A,#0BEH

;lnh READ SCRATCHPAD

LCALL

WRITE_BYTE

; c dn nh nhp cha
;gi tr nhit

LCALL

READ_BYTE

; c dn

CLR C

;xa c C v dng c C lu bit 0

RRC A

; dch phi A c c C
; lu bit vo c C

MOV

P1.0,C

; A ang cha 7 bit

; phn nguyn ca nhit

MOV

B,#10

DIV

AB

; chia A cho 10 v gi tr
; nhit gm 2 ch s

MOV

DPTR,#TABLE

MOVC

A,@A+DPTR

; A cha s hng chc

CALL

WRITE_TEXT

; xut s hng chc ln LCD

MOV

A,B

;B cha hng n v

MOV

DPTR,#TABLE

;chuyn B vo A xut ra LCD

MOVC

A,@A+DPTR

CALL

WRITE_TEXT

; xut s hng n v ra LCD

MOV

A,#'.'

; xut du . ln LCD

CALL

WRITE_TEXT

MOV

C, P1.0

;xt bit 0 tc l c C xem nhit

JC

DOLE

; c phn thp phn hay khng

SJMP

DOCHAN

DOLE:
MOV

A,#'5'

; nu bit 0 l 1 th nhit
; l xut xx.5 C

CALL

WRITE_TEXT

SJMP

NHAY

DOCHAN:
MOV

A,#'0'

;nu bit 0 l 0 th nhit

;chn xut xx.0 C

CALL

WRITE_TEXT

SJMP

NHAY

NHAY:
CALL

WAIT

MOV

A,#'C'

; xut ch C ln LCD

CALL

WRITE_TEXT

CALL

WAIT

;delay i hin xong gi tr ln LCD

LCALL

RESET_DS1820

; to xung reset kt thc giao tip

LCALL

DELAY_LONG

; delay

SJMP

LAP

SJMP

MOV

A,#38H

; chng trnh thit lp cho LCD

LCALL

WRITE

; coi li bi LCD

MOV

A,#0EH

LCALL

WRITE

MOV

A,#06H

LCALL

WRITE

; quay li Main chnh c lin tc nhit

LCD:

RET
; chng trnh con xut k t ra LCD

WRITE_TEXT:
MOV

DPTR,#8000H

SETB

P3.4

SETB

P3.5

MOVX

@DPTR,A

CLR

P3.4

LCALL

WAIT

; coi li code bi LCD

RET
WRITE:
MOV

DPTR,#8000H

; chng trnh con gip LCD nhn lnh

SETB

P3.4

;hay l chng trnh WRITE_COMAND

CLR

P3.5

; theo ti liu tham kho

MOVX

@DPTR,A ; coi li bi LCD

CLR

P3.4

LCALL

WAIT

RET
WAIT:
PUSH

07

; chng trnh con Delay 2ms

PUSH

06

;coi li bi LCD

MOV

R7,#4

MOV

R6,#250

DJNZ

R6,$

DJNZ

R7,LAP1

POP

06

POP

07

LAP1:

RET
TABLE:

DB 030H,031H,032H,033H,034H,035H,036H,037H,038H,039H
END

7) Th nghim vi vi mch DAC MCP4922

BI: Vit chng trnh xut mc in p bt k ra ng ra MCP4922. Ng ra DAC
s ni ti knh 1 ca ADC. Gi tr c c ADC s hin th ln LCD kim tra
CHUN B:
-Coi li kin thc cc bi LCD,ADC. Nm r cc chng trnh con trong cc bi
d s dng thun tin
- c k s kt ni phn cng ca MCP4922 vi b kit. c thm datasheet ca
MCP49922 hiu r cch thc thao tc.

S dnh th giao tip SDI. Da vo Datasheet MCP4922 th khi mun dch bit vo
chn SDI th ta phi CS mc thp. cho LDAC mc. khi dch bit phi to xung
clock SCK lm tn hiu dch bit. Kt thc dch bit th CS set ln mc 1. LDAC set
xung 0 trong khong 2 chu k my ri set li ln 1
S dch bit t thanh ghi A vo c C ri t c C vo SDI
C

khi gp mi xung clock SCK th bit t c C s c MOV vo SDI

SDI

theo trnh t ny ln lt lu trn 2 thanh ghi R4 v R2 s c a vo MCP 4922

qua chn SDI

s 16 bit:
8 bit cao lu thanh ghi R4

8 bit thp lu tahnh ghi R2

Bit 15 : A/B 0 chn ng ra l knh A,

1:chn ng ra l knh B . mnh chn knh B. chn khc cng ok
Bit 14: BUF, 0: chn buffered
1: unbuffered. bi ny ta chn BUF =1 ( thng l vy)
Bit 13 :Gain. Chn nhn i ng ra.
0: p ng ra c nhn i
1: p ng ra c gi nguyn
Bit 12: chn bit ngh cho DAC. y ta chn bit ny bng 1.
Vy l 4 bit cao Bit 15-bit12 l 4 bit config thit lp cho DAC . theo code ny mnh
chn bng 1111.
Bit 11-bit 0 : 12 bit d liu . ta c th tahy i gi tr 12 bit ny c p ng ra nh
mong mun.
Gi tr in p cao nht l 5V ng vi 12 bit d liu l FFFH
Vd code ca mnh 12 bit d liu l 0FFH.
Ng in p ra l s l : (0FF/FFF)*5= 0.3Volt
LU THUT TON:

ORG

Khi ng DAC
MAIN

SETB nCS
CLR nLDAC

Chn gi tr lu vo R4
MOV R1,#8
Cho R1 l gi tr m

Dch tng bit t A vo c C

Dch t c C vo chn SDI
R1<8

Chn gi tr lu vo R2
R1>8

MOV R1,#8
Cho R1 l gi tr m

Dch tng bit t A vo c C

Dch t c C vo chn SDI
R1<8

Xut gi tr t ADC ln LCD

R1>8
Tt DAC
CLR nCS
SETB nLDAC
CLR nLDAC

Delay hin ln
LCD

Nhy v Main chnh

CODE:
ORG

2000H

NCS

BIT P1.0

; gn tn cho cc bit P1.0,P1.1,P1.2

SCK

BIT P1.1

; chng ta d nh d thao tc

SDI

BIT P1.2

NLD

BIT P1.3

; bit NLD y l bit nLDAC trong ti liu

NCS

,2 lnh clear bit chip select v

MAIN:
CLR

; set bit NLD l hai

SETB

NLD

; lnh khi ng DAC.

; Xem thm datasheet

MOV
dn

R4,#0F0H

; mnh s dng thanh ghi R4,R2 chuyn

;16 bit d liu vo chn SDI ca MCP4922.
;Cch dch mnh s ni r pha trc ^^

MOV

A,R4

CALL

DICH

;gi chng trnh dch tng bit t thanh ghi vo SDI

CALL

WAIT

:gi chng trnh con delay khong 2ms

MOV

R2,#0FFH

; dch tng t thanh ghi R4 vi thanh ghi R2

MOV

A,R2

CALL

DICH

CALL

WAIT

CALL

XUAT0

;gi chng trnh xut gi tr in p ln LCD

SETB

NCS

; kt thc thao tc vi DAC

NOP

; phi Set bit chip select v clear bit nLDAC

NOP

;gia cc lnh ny c vi lnh NOP l gip

CLR

NLD

; MCP4922 c thi gian ch thc

; hin xong tc

NOP

;lnh

NOP
SETB

NLD

CALL

DELAY2S

SJMP

MAIN

;gi chng trnh delay 2s hin ln LCD

XUAT0:
MOV

A,#01H

;=====xa mn hnh LCD====

CALL

WRITE

MOV

DPTR,#8000H

CALL

LCD

MOV

A,#01H

CALL

WRITE

;==============================

MOV

DPTR,#4001H

;tr con tr DPTR ti a ch truy

; cc bn xem li phn LCD r hn

LAP:

;xut ADC knh 1

MOVX

@DPTR,A

; ra lnh chuyn i knh tng ng

CALL

DELAY0

; delay 100 micro giy

MOVX

A,@DPTR

; c gi tr in p t ADC lu vo A

MOV

B,#05H

;===============================

MUL

AB

; cch chuyn i in p t gai tr nh phn

MOV

R3,A

; sang thp phn thang o 0 -5V

MOV

A,B

; tng t nh bi ADC. Mnh ko nhc li

; cc bn coi li ADC r hn ^^

MOV

DPTR,#TABLE

MOVC

A,@A+DPTR

CALL

WRITE_TEXT

MOV

A,#'.'

CALL

WRITE_TEXT

MOV

B,#10

MOV

A,R3

MUL

AB

MOV

A,B

MOV

DPTR,#TABLE

MOVC

A,@A+DPTR

CALL

WRITE_TEXT

CALL

WAIT

MOV

A,#'V'

CALL

WRITE_TEXT

CALL

WAIT

SJMP

LAP

RET

;========================================
;=====CHNG TRNH CON DCH BIT VO SDI====

DICH:
R1,#8

; dng R1 kim ta s bit dch vo SDI 8 cha

RLC

; dch tri bit vo c C

CLR

SCK

;to xung clock

SDI,C

;dch t c C vo SDI

MOV
QUAY:

NOP
NOP
MOV
NOP
NOP

; nh th tao thi gian ch dch xong bit

SETB

SCK

NOP
NOP
DJNZ

; quay li ti khi dch 8 bit mi thi

R1,QUAY

RET
DELAY0:
PUSH

07

MOV

R7,#50

DJNZ

R7,$

POP

07

; chng trnh delay 100micro giy

RET
DELAY2S:

; delay 2s dng timer 0

DELAY:

MOV

R7,#50

LAP100:

MOV

TMOD,#01H

MOV

TH0,#HIGH(-50000)

MOV

TL0,#LOW(-50000)

SETB

TR0

JNB

TF0,$

CLR

TR0

CLR

TF0

DJNZ

R7,LAP100

RET

LCD:
MOV

A,#38H

;chng trnh khi ng LCD

LCALL

WRITE

;coi li bi LCD ^^

MOV

A,#0EH

LCALL

WRITE

MOV

A,#06H

LCALL

WRITE

RET
WRITE_TEXT:

;coi li bi LCD

MOV

DPTR,#8000H

SETB

P3.4

SETB

P3.5

MOVX

@DPTR,A

CLR

P3.4

LCALL

WAIT

RET
WRITE:
MOV

DPTR,#8000H

SETB

P3.4

CLR

P3.5

MOVX

@DPTR,A

CLR

P3.4

LCALL

WAIT

;coi li bi LCD

RET
WAIT:
PUSH

07

PUSH

06

MOV

R7,#4

LAP11:
MOV

R6,#250

DJNZ

R6,$

DJNZ

R7,LAP11

POP

06

POP

07

RET

; chng trnh delay 2ms

TABLE:

DB 030H,031H,032H,033H,034H,035H,036H,037H,038H,039H
; bng tra m k t ln LCD t 0-9

END

Bi 8 : Th Nghim Vi Led Ma Trn

Th nghim 1 : Vit chng trnh hin th k t A ln led ma trn.
Lu thut ton :
ORG

A #01
R2 #8
R1 #0

COT:
CHN COT COT:
CHN COT HIEN
TH
HIEN TH
HANG :
RL A
PUSH A
LY K T CN HIN TH TRN HNG
V XUT RA HNG
DELAY 1ms
POP A

R2 R2 1
IF R2 = 0

CODE v ch thch :
ORG

2000H

MOV

A,#01H

; thanh ghi A cha d liu cn xut ra

; trn ct tc l chn ct hin th

MAIN:
LAP2:
MOV

; do c 8 ct nn gn r2=8

R2,#8

;thc hin vng lp qut ct

MOV

; r1 dng cha v tr k t trong bng tra

R1,#0

LOOP:
CALL

COT

CALL

HANG

DJNZ

R2,LOOP

; sau mi ln xut c d liu ra 1

hng th gim r2 i 1 cho n khi
; 8 hng th quay li qut t u

SJMP

MAIN

MOV

DPTR,#0C000H

; ly a ch ct khi led matrix

MOVX

@DPTR,A

; chn ct cn c hin th

; xoay tri A chn ct tip theo hin th

COT:

RL
cho ln lp sau
RET

HANG:
PUSH

ACC

; gi li d liu cn xut ra trn

;ct cho vng lp sau

CALL

DU_LIEU

; ly d liu cn xut ra trn hng

MOV

DPTR,#0A000H

; ly a ch hng ca khi led matrix

MOVX

@DPTR,A

; xut d liu ra trn hng

LCALL

DELAY

POP

ACC

; ly li d liu xut ra trn ct

INC

R1

; tng v tr k t trong bng tra ln 1

RET
DU_LIEU:
MOV

A,R1

; ly v tr ca k t trong bng

MOV

DPTR,#CHAR

; ly a ch u bng

MOVC

A,@A+DPTR

; ly k t cn xut ra hng

RET
DELAY:
PUSH
07
;=================================================
PUSH

06

; chng trnh con DELAY

; dng to tr 1ms gia 2 ln

MOV

R7,#2

MOV

R6,#250

DJNZ

R6,$

DJNZ

R7,LAP

POP

06

POP

07

; xut d liu trn hng

LAP:

RET
;==================================================
CHAR:
END

DB 03H,0EDH,0EEH,0EEH,0EDH,03H,0FFH,0FFH

BI 9 : TH NGHIM VI NG C DC
Th nghim 1 : vit chng trnh cho php ng c chy theo chiu thun trong vng
2s , ngng 2s , quay chiu nghch 2s , ngng 2s v lp li .
Lu thut ton :
ORG

DPTRE000

THUAN :
ACC.01 ; ACC.10
DELAY 2S

NGHI :
ACC.0 0 ; ACC.1 0
DELAY 2S

NGHICH :
ACC.0 0 ; ACC.1 1
DELAY 2S

NGHI :
ACC.0 0 ; ACC.1 0
DELAY 2S

CODE v ch thch :
ORG 2000H
LOOP;
; ly a ch ca ngoi vi ng c dc

MOV

DPTR,#0E000H

CALL

THUAN

MOVX

@DPTR,A

; bt u cho ng c quay thun

CALL

DELAY2S

; cho ng c quay 2s

MOV

DPTR,#0E000H

CALL

NGHI

MOVX

@DPTR,A

; bt u cho ng c ngh

CALL

DELAY2S

; ng c ngh 2s

MOV

DPTR,#0E000H

CALL

NGHICH

MOVX

@DPTR,A

CALL

DELAY2S

MOV

DPTR,#0E000H

CALL

NGHI

MOVX

@DPTR,A

CALL

DELAY2S

SJMP

LOOP

; bt u cho ng c quay nghch

; ng c quay nghch 2s

; quay li ban u

THUAN:
SETB
ACC.0
;=====================================================
CLR

ACC.1

ci t ch quay thun

RET
;=====================================================
NGHICH:
CLR
ACC.0
;====================================================
SETB

ACC.1

; ci t ch quay nghch

RET
;====================================================
NGHI:
CLR
ACC.0
;========================================================
CLR

ACC.1

; ci t ch ngh

RET
;========================================================
DELAY2S:
MOV
R7,#20
;========================================================
LAP2: MOV

R6,#200

LAP1: MOV

R5,#250

DJNZ

R5,$

DJNZ

R6,LAP1

DJNZ

R7,LAP2

; chng trnh con delay to tr 2s

RET
;========================================================
END