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AIM:
To design a multiplexer, decoder and comparator using VHDL and verilog.
SOFTWARE REQUIRED:
Xilinx ISE 9.1i.
ALGORITHM:
STEP 1: Open Xilinx ISE 9.1i software.
STEP 2: Create a new project using File New project.
STEP 3: Type the program and save the project.
STEP 4: In synthesis/implementation double click synthesize-XST to check syntax.
STEP 5: Choose behavioral simulation.
STEP 6: In create new sourceTest bench waveform and save the test bench waveform.
STEP 7: In Xilinx ISE SimulatorSimulate Behavioral Model.
STEP 8: Verify the output waveform.
i4 : in STD_LOGIC;
i5 : in STD_LOGIC;
i6 : in STD_LOGIC;
i7 : in STD_LOGIC;
i8 : in STD_LOGIC;
i9 : in STD_LOGIC;
i10 : in STD_LOGIC;
i11 : in STD_LOGIC;
i12 : in STD_LOGIC;
i13 : in STD_LOGIC;
i14 : in STD_LOGIC;
i15 : in STD_LOGIC;
s : in STD_LOGIC_VECTOR (3 downto 0);
y : out STD_LOGIC);
end multiplexer;
architecture behavioral of multiplexer is
begin
process(i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,s)
begin
case s is
when "0000"=>
y<=i0;
when "0001"=>
y<=i1;
when "0010"=>
y<=i2;
when "0011"=>
y<=i3;
when "0100"=>
y<=i4;
when "0101"=>
y<=i5;
when "0110"=>
y<=i6;
when "0111"=>
y<= i7;
when "1000"=>
y<= i8;
when "1001"=>
y<= i9;
when "1010"=>
y<= i10;
when "1011"=>
y<= i11;
when "1100"=>
y<= i12;
when "1101"=>
y<= i13;
when "1110"=>
y<= i14;
when "1111"=>
y<= i15;
when others=>null;
end case;
end process;
end Behavioral;
oup<="0000000000100000";
when "0110"=>
oup<="0000000001000000";
when "0111"=>
oup<= "0000000010000000";
when "1000"=>
oup <= "0000000100000000";
when "1001"=>
oup<= "0000001000000000";
when "1010"=>
oup <= "0000010000000000";
when "1011"=>
oup <= "0000100000000000";
when "1100"=>
oup <= "0001000000000000";
when "1101"=>
oup <= "0010000000000000";
when "1110"=>
oup <= "0100000000000000";
when "1111"=>
oup <= "1000000000000000";
when others=>
oup<="----------------";
end case;
end process; end Behavioral;
(d8,x,ybar,zbar,wbar),(d9,x,ybar,zbar,w),(d10,x,ybar,z,wbar),(d11,x,ybar,z,w),
(d12,x,y,zbar,wbar),(d13,x,y,zbar,w),(d14,x,y,z,wbar),(d15,x,y,z,w);
not
(xbar,x),
(ybar,y),
(zbar,z),
(wbar,w);
endmodule
end if;
end process;
end Behavioral;
RESULT:
Multiplexers, Decoders and Comparators are designed using VHDL and Verilog and the output
Waveforms are verified.