40.2 Gascaded PSeUdo-nMUS Inverters A sinple timing noel of th pseudo-1MOS inver nrodaced in Chapter 2is shown in Fig. 4.32 This uses the 3:1 trait ais determined in ta chapter. The approximate delay fora ait of inverters is | iav-pair = TRC, where Cg C+ 2p Note that this speed may be improved by sacrificing noise margin (Le ‘making the pull-up strongen) 4.8.3 Stago Ratio Often it is desired to drive large load capacitances such as long buses, VO buffers, or, uimately, pads and off-chip capacitive loads. This is achieved by using a chain of inverters (or perhaps other logic gates) where each suc cessive inverter is made larger than the previous one until the ‘ast inverter in ‘the chain can drive the large loadin the time required. The optimization ta be achieved here is to minimize the delay between input and output while min. izing the area and power dissipation. The ratio by which each stage is increased in size is called the stage ratio. Following the derivation given in Mead and Conway.” consider the cir cuit shown in Fig. 4.33. Itconsists of n-cascaded inverters with stage-ratio a, driving a capacitance Cp. Thus inverter iny-1 is a minimum-sized inverter mBR(C, +26) +R(C,#2C,) (462) FIQURE 4.52 Pseudo- ‘AMOS inverter pair timing responsecy FIGURE 4.33. Stage rao ae {) circu; (0) graph driving inverter inv-2, which is a times the size of a minimum inverter. Sim- ilarly, inverter inv-2 drives inverter inv-3, which is a” the size of a minimum inverter. The delay through each stage is ety, where tis the average delay of a minimum-sized inverter driving another minimum-sized iaverter (actually the delay through any inverter driving an identically sized inverter). Hence the delay through w stages is nary. If the ratio of the load capacitance to the capacitance of a minimum inverter, Cp/Cy. is R, then ef”= R. Hence In(R) nina), Thos the total delay is a Toval Delay = nary = mR Tasty (4.63) Tn this equation 4, is a constant and Jn(R depends on the ratio of internal to external load and is constant for a given load and process. The variable part of Eq. (4.63) is graphed in Fig, 4.33(b) for various values of a from | to- 100. The y scale is normalized to ¢, The graph shows that for this simple analysis the stage ratio minimizes the total delay when the stage ratio equals (~2.7), More detailed analysis that accounts for the contribution of the intrinsic output capacitance of the inverter illustrates that this ratio varies from 3 to $ depending on the process.** The optimum stage ratio may be determined from bhi ago (4.64) where & is the intrinsic output load capacitance and input gate capacitance of an inverter. For the 1{t process capacitances given in Section 4.3.4 kx Stein _ 0043 Cc. 02 ‘ete = 215, (4.65)Age = 293. In the fest eto ofthis book, for a 2.5 process f= 357, which results in doy, = $32. Ths illustrates ow 4 design parameter can vary as processes advance. In practice, stage ratios from 2 10 are quite common in practical circuits depending on speed, area, and power constraints. Avariable-stage- ratio approach has been suggested as a means of reducing the area of| ccaded inverters ata slight penalty in delay.”? In this technique, the stage ratio is vated depending on the position of the inverter in the overall bute. 47 POWERDISSIPATION 253 Although we have considered the delay through easeaded inverters, the ‘concept of maintaining # good stage ratio is also of importance for a cas- caded path through any logic gates where high-speed designs are involved. A variety of software packages have been developed toad in the optimization of transistor sizesin cascaded CMOS gates.”