11/05/2015

fpga4fun.comHDMI

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HDMI
HDMIisadigitalvideointerface,soiseasytodrivefrommodernFPGAs.
Let'sseehowitworks.

Theconnector
ThestandardHDMIconnectoriscalled"typeA"andhas19pins.Outofthe19pins,12areofparticularinterestastheyform4
shieldedTMDSdifferentialpairsthattransporttheactualhighspeedvideoinfo.
1.
2.
3.
4.

TMDSdata2+,data2anddata2shield.
TMDSdata1+,data1anddata1shield.
TMDSdata0+,data0anddata0shield.
TMDSclock+,clockandclockshield.

OurconnectionfromanFPGAtoanHDMIconnectorcanhardlybesimpler...weuse8FPGApinstodrivetheTMDSdata+/and
clock+/pins,configuredas4differentialTMDSoutputs.

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Videosignal
Let'screatea640x480RGB24bpp@60Hzvideosignal.That's307200pixelsperframe,andsinceeachpixelhas24bits(8bits
forred,greenandblue),at60Hz,theHDMIlinktransports0.44Gbpsof"useful"data.
Butvideosignalsusuallyalsohavean"offscreen"area,whichisusedbytheHDMIreceiver(TVormonitor)forsome
housekeeping.Our640x480frameisactuallysentasan800x525frame.

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Withthatinmind,weneeda24.5MHzpixelclocktoachieve60framesperseconds,butHDMIspecifiesa25MHzminimumpixel
clock,sothat'sweuse(whichgetsusa61Hzframerate).

TMDSsignals
TheFPGAhas4TMDSdifferentialpairstodrive.
First,theTMDSclockissimplythepixelclock,soitrunsat25MHz.Theother3pairstransmitthered,greenandbluesignals,so
wegetsomethinglikethat.

Thingsareinfactjustabitmorecomplicated.HDMIrequiresthatweactually"massage"thedatawitha"TMDSencoder",which
scramblesthedataandadd2bitspercolorlane,sowehave10bitsinsteadof8perlaneandthelinkendsuptransporting30bits
perpixel.ThescramblingandextrabitsareneededbytheHDMIreceivertoproperlysynchronizetoandacquireeachlanemode
detailsintheDVIandHDMIspecifications.

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Sourcecode
Firstavideogenerator.Weuseacoupleofcountersthatgothroughan800x525pixelarea...
reg [9:0] CounterX; // counts from 0 to 799
always @(posedge pixclk) CounterX <= (CounterX==799) ? 0 : CounterX+1;
reg [9:0] CounterY; // counts from 0 to 524
always @(posedge pixclk) if(CounterX==799) CounterY <= (CounterY==524) ? 0 : CounterY+1;
andcreatethehsyncandvsyncsignals...
wire hSync = (CounterX>=656) && (CounterX<752);
wire vSync = (CounterY>=490) && (CounterY<492);
wire DrawArea = (CounterX<640) && (CounterY<480);
andgeneratesomered,greenandbluesignals(8bitseach)...
wire [7:0] red = {CounterX[5:0] & {6{CounterY[4:3]==~CounterX[4:3]}}, 2'b00};
wire [7:0] green = CounterX[7:0] & {8{CounterY[6]}};
wire [7:0] blue = CounterY[7:0];
whichareexpandedto10bitseachthroughthree"TMDS_encoder"instances.
wire [9:0] TMDS_red, TMDS_green, TMDS_blue;
TMDS_encoder encode_R(.clk(pixclk), .VD(red ), .TMDS(TMDS_red) , .CD(2'b00)
, .VDE(DrawArea));
TMDS_encoder encode_G(.clk(pixclk), .VD(green), .TMDS(TMDS_green), .CD(2'b00)
, .VDE(DrawArea));
TMDS_encoder encode_B(.clk(pixclk), .VD(blue ), .TMDS(TMDS_blue) , .CD({vSync,hSync}), .VDE(DrawArea));
Now,wehavethree10bitsvaluestobesentforeverypixelclockperiod.Wemultiplythe25MHzclockby10togeneratea
250MHzclock...
wire clk_TMDS, DCM_TMDS_CLKFX;
DCM_SP #(.CLKFX_MULTIPLY(10)) DCM_TMDS_inst(.CLKIN(pixclk), .CLKFX(DCM_TMDS_CLKFX), .RST(1'b0));
BUFG BUFG_TMDSp(.I(DCM_TMDS_CLKFX), .O(clk_TMDS));

// 250 MHz

andusethreeshiftregistersclockedat250MHz...
reg [3:0] TMDS_mod10; // modulus 10 counter
always @(posedge clk_TMDS) TMDS_mod10 <= (TMDS_mod10==9) ? 0 : TMDS_mod10+1;
reg TMDS_shift_load;
always @(posedge clk_TMDS) TMDS_shift_load <= (TMDS_mod10==9);
reg [9:0] TMDS_shift_red, TMDS_shift_green, TMDS_shift_blue;
always @(posedge clk_TMDS)
begin
TMDS_shift_red
<= TMDS_shift_load ? TMDS_red
: TMDS_shift_red [9:1];
TMDS_shift_green <= TMDS_shift_load ? TMDS_green : TMDS_shift_green[9:1];
TMDS_shift_blue <= TMDS_shift_load ? TMDS_blue : TMDS_shift_blue [9:1];
end
tosendtheTMDSdataoutsidetheFPGA.
OBUFDS
OBUFDS
OBUFDS
OBUFDS

OBUFDS_red (.I(TMDS_shift_red [0]), .O(TMDSp[2]), .OB(TMDSn[2]));

OBUFDS_green(.I(TMDS_shift_green[0]), .O(TMDSp[1]), .OB(TMDSn[1]));
OBUFDS_blue (.I(TMDS_shift_blue [0]), .O(TMDSp[0]), .OB(TMDSn[0]));
OBUFDS_clock(.I(pixclk), .O(TMDSp_clock), .OB(TMDSn_clock));

Thecompletesourceisavailablehere.

Higherresolutions
With640x480,weused250MHzclockedserializers,butforhigherresolutions,weneedhigherfrequencies,whichcanquicklygo
abovetheabilityofFPGAs.TheworkaroundistousesomespecialFPGAIOfeatures,likeDDRoutputsandIOserializers.
Anotherproblemathigherfrequenciesishowtoreliablytransferdatafromthepixelclockdomaintotheserializerdomain.One
possibletechniqueistouseashallowFIFO.ChecktheXilinxXAPP460(forSpartan3A)andXAPP495(forSpartan6)
applicationnotestogetsomeideas.

Screenshots
HereareafewshotsmadeusingadigitalcamerashootinganLCDmonitordrivenbyPlutoIIxHDMI.
Wehavetheponggame...

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andforfun,theclassicPacManarcadegame...whichusedtobeavailablefromfpgaarcade.com,butthesitewasredesigned
recently.Youcanstillgettheoriginalsourceusingthewaybackmachine.

Here'sapicofourtestboard(PlutoIIxHDMIloadedwithanoptionalHDMIadaptersoweactuallyhavetwoHDMIoutputsto
playwith...).

Links
ADVIandTMDSwhitepaperfromSiliconImage.
AnintroductiontoTMDSfromBICSI.
HDMI1.3demystifiedfromaudioquest.
TheDVI1.0specification(HDMIisbasedonDVI).

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TheHDMI1.3aspecification.

ThispagewaslastupdatedonJanuary232015.

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