An FPGA Spectrum Sensing

Accelerator for Cognitive Radio

George Eichinger
Miriam Leeser
Kaushik Chowdhury
HPEC 2011
21 Sept 2011

This work is sponsored by the Department of the Air Force under Air Force Contract
FA8721-05-C-0002. The opinions, interpretations, conclusions, and recommendations are
those of the authors and are not necessarily endorsed by the United States Government

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Cognitive Radio Overview

Fre

que

ncy

Spectrum Holes

Time
Cognitive radios allow you to operate in unused portions of spectrum
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Cognitive Cycle
Transmitted
Signal

Radio
Environment
RF
Stimuli

Spectrum
Mobility
Decision
Request

Spectrum
Sharing

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Primary User
Detection

Spectrum
Characterization

Spectrum
Sensing

Spectrum
Hole

Spectrum
Decision

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Cognitive Cycle
Transmitted
Signal

Radio
Environment
RF
Stimuli

Spectrum
Mobility
Decision
Request

Spectrum
Sharing

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Primary User
Detection

Spectrum
Characterization

Spectrum
Sensing

Spectrum
Hole

Focus of
This Talk

Spectrum
Decision

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Outline

Cognitive Radio overview

Project motivation and goals
Hardware platform
Spectrum sensing algorithm
Results of implementation
Summary

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Motivation
Existing Software Defined Radio (SDR) systems take too long
to perform spectrum sensing
Software spectrum sensing involves transmitting data to and
from the host computer which adds latency and processing time
Moving spectrum sensing closer to the receiver reduces
latency and makes real time spectrum sensing feasible

ts

Sensing Cycle: Ts = ts + T

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Project Goals

Create platform for hardware level Cognitive Radio (CR) research

Perform spectrum sensing as close to the receiver and as fast
as possible
Report results to host indicating whether or not a channel is free
Design system with reconfigurable, parameterized hardware and
programmable software

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Outline

Cognitive Radio overview

Project motivation and goals
Hardware platform
Cognitive Radio Universal Software
Hardware (CRUSH)

Spectrum sensing algorithm

Results of implementation
Summary

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Introducing CRUSH
Cognitive Radio Universal Software Hardware (CRUSH)
Xilinx ML605
FPGA Board

Ettus USRP
N210
Custom
Interface
Board

Standard software defined radio and FPGA development board

Custom interface board to connect the two boards
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Ettus Research USRP N210

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Agile front end

Low cost
Xilinx Spartan 3A DSP FPGA for RX/TX
Minor changes for CRUSH
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Xilinx ML605 FPGA Development Board

Standard FPGA development board

Ability to communicate at full ADC and DAC rate with the USRP
Versatile external IO/memory
Increases from USRP FPGA: 6.6 more RAM, 4.5 more LUTs, 2.5 faster

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Custom Interface Board

Only custom part of CRUSH

Allows full 100 MSPS IQ
transmit and receive data
Able to communicate with
two USRPs at once
Compatible with FMC boards
such as Xilinx ML605 and
SP605

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Outline

Cognitive Radio overview

Project motivation and goals
Hardware platform
Spectrum sensing algorithm
Results of implementation
Summary

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Spectrum Sensing Algorithm

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Frequency

Report
Data

Boolean

Amplitude

Time

Apply
Threshold

Amplitude (dB)

Perform
FFT

Amplitude (dB)

Receive
RF Data

Frequency

Frequency

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Host

Digital Up
Converter
(DUC)

Host
Control Logic

Frequency Selection

IF

IF

Digital Down
Converter
(DDC)

USRP

RF

RF

System Diagram
Spectrum Sensing without CRUSH

ADC

Radio

DAC Data

Transmitter

Receiver

FFT

All processing occurs on the host

No real-time guarantee

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USRP

Digital Up
Converter
(DUC)

Host
Control Logic

Frequency Selection

IF

IF

Digital Down
Converter
(DDC)

Host

RF

RF

System Diagram
Spectrum Sensing with CRUSH

Radio

DAC Data

Transmitter

Receiver

FFT

ADC Data

ADC

FIFO

Samples

FFT

Freq Bins

Threshold
Detector

Freq Bins

Frequency
Status
Accumulator

ML605
Control Logic

ML605

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Advantages of CRUSH
Ability to process received data in real time
FPGA: Parallel clock driven data bus
Host: Serial packetized data

Higher throughput datalink

FPGA: 100 MHz 32 bit DDR interface (800 MB/s)
Host: Gigabit Ethernet (125 MB/s)

Less processing load on the host

More time for high level policy/protocol execution

Reconfigurable hardware allows for parameters

such as FFT size to be changed in real time
New protocols with functionality partly residing
on host and partly on the radio are now possible
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Outline

Cognitive Radio overview

Project motivation and goals
Hardware platform
Spectrum sensing algorithm
Results of implementation
Summary

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Test Setup Functional Verification

Signal Generators

USRP

ML605

Host

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Results Functionality Verification

Lab measurement with one tone at 31 MHz
and a center frequency of 25 MHz
256-point FFT Processed by FPGA
0

FFT of USRP data Processed in Matlab

0

X: 3.086e+007
Y: 0

-10

-10
-20

-30

Amplitude (dBc)

Amplitude (dBc)

-20

-40
-50

-30
-40
-50

-60

-60

-70

-70

-80

X: 3.1e+007
Y: 0

10

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20

30

Frequency in MHz

40

50

-80

15

20

25

30

Frequency in MHz

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35

ADC Data

ADC

FIFO

Host

Digital Up
Converter
(DUC)
USRP
Control Logic

Two Way Status

IF

Digital Down
Converter
(DDC)

RF

USRP

Radio

DAC Data

ML605
Control Logic

Samples

Host
Control Logic

Frequency Selection

IF

RF

Test Setup Runtime Analysis

Transmitter

Receiver

FFT

Two Way Status

FFT

Timers

ML605

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ADC Data

ADC

Host

Digital Up
Converter
(DUC)
USRP
Control Logic

Two Way Status

IF

Digital Down
Converter
(DDC)

RF

USRP

Host
Control Logic

Frequency Selection

Radio

1. Host -> FPGA (start test)

2. FPGA (reset timers)

IF

RF

Test Setup Runtime Analysis

DAC Data

Transmitter

Receiver

3. FPGA -> USRP (start test)

FFT

4. USRP -> Host/FPGA

(test pattern)
5. FPGA FFT Done (stops timer)

ML605
Control Logic

6. Host -> FPGA (FFT Done)

Two Way Status

7. Host FFT Done (stops timer)

FIFO

Samples

FFT

Timers

ML605

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ADC Data

ADC

Host

Digital Up
Converter
(DUC)
USRP
Control Logic

Two Way Status

IF

Digital Down
Converter
(DDC)

RF

USRP

Host
Control Logic

Frequency Selection

Radio

1. Host -> FPGA (start test)

2. FPGA (reset timers)

IF

RF

Test Setup Runtime Analysis

DAC Data

Transmitter

Receiver

3. FPGA -> USRP (start test)

FFT

4. USRP -> Host/FPGA

(test pattern)
5. FPGA FFT Done (stops timer)

ML605
Control Logic

6. Host -> FPGA (FFT Done)

Two Way Status

7. Host FFT Done (stops timer)

FIFO

Samples

FFT

Timers

ML605

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ADC Data

ADC

Host

Digital Up
Converter
(DUC)
USRP
Control Logic

Two Way Status

IF

Digital Down
Converter
(DDC)

RF

USRP

Host
Control Logic

Frequency Selection

Radio

1. Host -> FPGA (start test)

2. FPGA (reset timers)

IF

RF

Test Setup Runtime Analysis

DAC Data

Transmitter

Receiver

3. FPGA -> USRP (start test)

FFT

4. USRP -> Host/FPGA

(test pattern)
5. FPGA FFT Done (stops timer)

ML605
Control Logic

6. Host -> FPGA (FFT Done)

Two Way Status

7. Host FFT Done (stops timer)

FIFO

Samples

FFT

Timers

ML605

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ADC Data

ADC

Host

Digital Up
Converter
(DUC)
USRP
Control Logic

Two Way Status

IF

Digital Down
Converter
(DDC)

RF

USRP

Host
Control Logic

Frequency Selection

Radio

1. Host -> FPGA (start test)

2. FPGA (reset timers)

IF

RF

Test Setup Runtime Analysis

DAC Data

Transmitter

Receiver

3. FPGA -> USRP (start test)

FFT

4. USRP -> Host/FPGA

(test pattern)
5. FPGA FFT Done (stops timer)

ML605
Control Logic

6. Host -> FPGA (FFT Done)

Two Way Status

7. Host FFT Done (stops timer)

FIFO

Samples

FFT

Timers

ML605

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ADC Data

ADC

Host

Digital Up
Converter
(DUC)
USRP
Control Logic

Two Way Status

IF

Digital Down
Converter
(DDC)

RF

USRP

Host
Control Logic

Frequency Selection

Radio

1. Host -> FPGA (start test)

2. FPGA (reset timers)

IF

RF

Test Setup Runtime Analysis

DAC Data

Transmitter

Receiver

3. FPGA -> USRP (start test)

FFT

4. USRP -> Host/FPGA

(test pattern)
5. FPGA FFT Done (stops timer)

ML605
Control Logic

6. Host -> FPGA (FFT Done)

Two Way Status

7. Host FFT Done (stops timer)

FIFO

Samples

FFT

Timers

ML605

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ADC Data

ADC

Host

Digital Up
Converter
(DUC)
USRP
Control Logic

Two Way Status

IF

Digital Down
Converter
(DDC)

RF

USRP

Host
Control Logic

Frequency Selection

Radio

1. Host -> FPGA (start test)

2. FPGA (reset timers)

IF

RF

Test Setup Runtime Analysis

DAC Data

Transmitter

Receiver

3. FPGA -> USRP (start test)

FFT

4. USRP -> Host/FPGA

(test pattern)
5. FPGA FFT Done (stops timer)

ML605
Control Logic

6. Host -> FPGA (FFT Done)

Two Way Status

7. Host FFT Done (stops timer)

FIFO

Samples

FFT

Timers

ML605

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ADC Data

ADC

Host

Digital Up
Converter
(DUC)
USRP
Control Logic

Two Way Status

IF

Digital Down
Converter
(DDC)

RF

USRP

Host
Control Logic

Frequency Selection

Radio

1. Host -> FPGA (start test)

2. FPGA (reset timers)

IF

RF

Test Setup Runtime Analysis

DAC Data

Transmitter

Receiver

3. FPGA -> USRP (start test)

FFT

4. USRP -> Host/FPGA

(test pattern)
5. FPGA FFT Done (stops timer)

ML605
Control Logic

6. Host -> FPGA (FFT Done)

Two Way Status

7. Host FFT Done (stops timer)

FIFO

Samples

FFT

Timers

ML605

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256-point FPGA FFT Timing Analysis

270 ns
2560 ns

Clocks

Time (s)

Start Test

Data enters FPGA Clock Domain

27

0.27

0.27

FFT Starts
All Data inside FPGA

27
256

0.27
2.56

0
2.83

FFT Complete

941

9.41

6.58

Total

941

9.41

9.41

Action

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9410 ns

Incremental (s)

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Results Runtime Analysis

FFT Size

FPGA
Average (s)

Host
Average (s)

Speed-up ()

1.17

907.72

774

16

1.91

915.89

479

32
64

2.38
3.56

920.07
925.47

386
259

128
256

5.47
9.56
17.23

916.54

167

1198.19
1003.83

125
58

32.84
63.55

955.30
995.26

29
15

125.24

1071.79

512
1024
2048
4096

Speed-up between 8 and 774

FPGA timing scales log linear with FFT size
Host timing driven by packet transmit time
and internal buffering

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Results Runtime Analysis

FFT Size

FPGA
Average (s)

Host
Average (s)

Speed-up ()

1.17

907.72

774

16

1.91

915.89

479

32
64

2.38
3.56

920.07
925.47

386
259

128
256

5.47
9.56
17.23

916.54

167

1198.19
1003.83

125
58

32.84
63.55

955.30
995.26

29
15

125.24

1071.79

512
1024
2048
4096

Speed-up between 8 and 774

FPGA timing scales log linear with FFT size
Host timing driven by packet transmit time
and internal buffering

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Conclusion

Created CRUSH platform

Combined powerful FPGA with versatile RF front end
Produced custom interface board to allow high speed data transfer
Moved processing closer to receiver

Implemented spectrum sensing on CRUSH

Achieved more than 100 performance for FFT sizes of interest
Reduced load on host computer
Fully configurable

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Future Work

Integrate the spectrum sensing module into research

on Cognitve Radio at Northeastern University
Explore other methods of performing hardware accelerated
spectrum sensing such as wavelet analysis
Utilize the CRUSH platform to migrate additional software
radio functions into reconfigurable hardware
Perform non-radio research with the CRUSH platform
utilizing its RF front end and FPGA back end

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Questions?
Questions?

Miriam Leeser
mel@coe.neu.edu

Kaushik Chowdhury
krc@ece.neu.edu

http://www.coe.neu.edu/Research/rcl/index.php

http://indigo.ece.neu.edu/~krc/#research

George Eichinger
eichinger.g@husky.neu.edu

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