// DESCRIPTION:

//
// This example sets up the PLL in x10/2 mode.
//
// For 150 MHz devices (default)
// divides SYSCLKOUT by six to reach a 25.0Mhz HSPCLK
// (assuming a 30Mhz XCLKIN).
//
// For 100 MHz devices:
// divides SYSCLKOUT by four to reach a 25.0Mhz HSPCLK
// (assuming a 20Mhz XCLKIN).
//
// Interrupts are enabled and the ePWM1 is setup to generate a periodic
// ADC SOC on SEQ1. Two channels are converted, ADCINA3 and ADCINA2.
//
// Watch Variables:
//
//
Voltage1[10]
Last 10 ADCRESULT0 values
//
Voltage2[10]
Last 10 ADCRESULT1 values
//
ConversionCount Current result number 0-9
//
LoopCount
Idle loop counter
//###########################################################################
#include "DSP28x_Project.h"

// Device Headerfile and Examples Include File

void InitEPwm1Example(void);
// Prototype statements for functions found within this file.
interrupt void adc_isr(void);
interrupt void cpu_timer0_isr(void);
interrupt void epwm1_isr(void);
#define
#define
#define
#define

EPWM1_MAX_DB
EPWM1_MIN_DB
DB_UP 1
DB_DOWN 0

0x03FF
0

Uint32 PWM_CYCLE = 4650;

float duty_cycle = 0.5;
Uint32 anchoA = 4650;
//Uint32 anchoB = 4650;
//Uint32 anchoC = 4650;
// Global variables used in this example:
Uint16 LoopCount;
Uint16 ConversionCount;
Uint16 Voltage1;
Uint16 Voltage2;
Uint16 Voltage3;
Uint16 Voltage4;
Uint32 EPwm1TimerIntCount;
Uint16 EPwm1_DB_Direction;
void main(){
// Step 1. Initialize System Control:
// PLL, WatchDog, enable Peripheral Clocks
// This example function is found in the DSP2833x_SysCtrl.c file.
InitSysCtrl();

InitEPwm1Gpio();
/* EALLOW;
// Default - 150 MHz SYSCLKOUT
#define ADC_MODCLK 0x3 // HSPCLK = SYSCLKOUT/2*ADC_MODCLK2 = 150/(2*3)
25.0 MHz

EDIS;*/
//EALLOW;
//
SysCtrlRegs.WDCR= 0x00AF;
// Re-enable the watchdog
//EDIS;
// 0x00AF to NOT disable the Watchdog, Prescale
r = 64
//
//
//
//

Step 2. Initialize GPIO:

This example function is found in the DSP2833x_Gpio.c file and
illustrates how to set the GPIO to it's default state.
InitGpio(); // Skipped for this example

// Step 3. Clear all interrupts and initialize PIE vector table:

// Disable CPU interrupts
DINT;
//
//
//
//

Initialize the PIE control registers to their default state.

The default state is all PIE interrupts disabled and flags
are cleared.
This function is found in the DSP2833x_PieCtrl.c file.
InitPieCtrl();

// Disable CPU interrupts and clear all CPU interrupt flags:

IER = 0x0000;
IFR = 0x0000;
//
//
//
//
//
//

Initialize the PIE vector table with pointers to the shell Interrupt
Service Routines (ISR).
This will populate the entire table, even if the interrupt
is not used in this example. This is useful for debug purposes.
The shell ISR routines are found in DSP2833x_DefaultIsr.c.
This function is found in DSP2833x_PieVect.c.
InitPieVectTable();
InitAdc();
/////////////////////////////////////////////////////////////////////////
AdcRegs.ADCTRL1.all = 0;
AdcRegs.ADCTRL1.bit.ACQ_PS = 7;
// 7 = 8 x ADCCLK
AdcRegs.ADCTRL1.bit.SEQ_CASC =1;
// 1=cascaded sequencer
AdcRegs.ADCTRL1.bit.CPS = 0;
// divide by 1
AdcRegs.ADCTRL1.bit.CONT_RUN = 0;
// single run mode
AdcRegs.ADCTRL2.all = 0;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; // 1=enable SEQ1 interrupt
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 =1; // 1=SEQ1 start from ePWM_SOCA t

rigger
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1 = 0;
of sequence

// 0= interrupt after every end

AdcRegs.ADCTRL3.bit.ADCCLKPS = 3;
* ADCCLKPS

// ADC clock: FCLK = HSPCLK / 2

// HSPCLK = 75MHz (see DSP2833x_SysCtrl.c)

// FCLK = 12.5 MHz

AdcRegs.ADCMAXCONV.all = 0x0004;

// 2 conversions from Sequencer 1

AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0; // Setup ADCINA0 as

AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 1; // Setup ADCINA1 as 2nd
AdcRegs.ADCCHSELSEQ1.bit.CONV02 = 2; // Setup ADCINA1 as 2nd
AdcRegs.ADCCHSELSEQ1.bit.CONV03 = 3; // Setup ADCINA1 as 2nd

1st SEQ1 conv.

SEQ1 conv.
SEQ1 conv.
SEQ1 conv.

EPwm2Regs.TBCTL.all = 0xC030; // Configure timer control register

/*
bit 15-14
11:
FREE/SOFT, 11 = ignore emulation suspend
bit 13
0:
PHSDIR, 0 = count down after sync event
bit 12-10
000:
CLKDIV, 000 => TBCLK = HSPCLK/1
bit 9-7
000:
HSPCLKDIV, 000 => HSPCLK = SYSCLKOUT/1
bit 6
0:
SWFSYNC, 0 = no software sync produced
bit 5-4
11:
SYNCOSEL, 11 = sync-out disabled
bit 3
0:
PRDLD, 0 = reload PRD on counter=0
bit 2
0:
PHSEN, 0 = phase control disabled
bit 1-0
00:
CTRMODE, 00 = count up mode
*/
EPwm2Regs.TBPRD = 2999; // TPPRD +1 = TPWM / (HSPCLKDIV * CLKDIV * TSY
SCLK)
//

= 20 s

/ 6.667 ns
EPwm2Regs.ETPS.all = 0x0100;

// Configure ADC start b

y ePWM2
/*
bit
bit
bit
bit
bit
bit
bit
*/

15-14
13-12
11-10
9-8
7-4
3-2
1-0

00:
00:
00:
01:
0000:
00:
00:

EPWMxSOCB, read-only
SOCBPRD, don't care
EPWMxSOCA, read-only
SOCAPRD, 01 = generate SOCA on first event
reserved
INTCNT, don't care
INTPRD, don't care

EPwm2Regs.ETSEL.all = 0x0A00;
// Enable SOCA to ADC
/*
bit 15
0:
SOCBEN, 0 = disable SOCB
bit 14-12
000:
SOCBSEL, don't care
bit 11
1:
SOCAEN, 1 = enable SOCA
bit 10-8
010:
SOCASEL, 010 = SOCA on PRD event
bit 7-4
0000: reserved
bit 3
0:
INTEN, 0 = disable interrupt
bit 2-0
000:
INTSEL, don't care
*/
/////////////////////////////////////////////////////////////////////////
// Interrupts that are used in this example are re-mapped to
// ISR functions found within this file.
EALLOW; // This is needed to write to EALLOW protected register
//PieVectTable.TINT0 = &cpu_timer0_isr;
PieVectTable.EPWM1_INT = &epwm1_isr;
PieVectTable.ADCINT = &adc_isr;
EDIS;
// This is needed to disable write to EALLOW protected registers
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 0;

EDIS;
InitEPwm1Example();
EALLOW;
SysCtrlRegs.PCLKCR0.bit.TBCLKSYNC = 1;
EDIS;
EPwm1TimerIntCount = 0;
// Step 4. Initialize all the Device Peripherals:
// This function is found in DSP2833x_InitPeripherals.c
// InitPeripherals(); // Not required for this example
// InitAdc(); // For this example, init the ADC
//InitCpuTimers();
// Step 5. User specific code, enable interrupts:
/*
// Enable ADCINT in PIE
PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
IER |= M_INT1; // Enable CPU Interrupt 1
EINT;
// Enable Global interrupt INTM
ERTM;
// Enable Global realtime interrupt DBGM
LoopCount = 0;
ConversionCount = 0;
// Configure ADC
AdcRegs.ADCMAXCONV.all = 0x0001;
//
AdcRegs.ADCCHSELSEQ1.bit.CONV00 = 0x0; //
AdcRegs.ADCCHSELSEQ1.bit.CONV01 = 0x1; //
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1 = 1;//
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1 = 1; //
// Assumes ePWM1 clock is already enabled
EPwm1Regs.ETSEL.bit.SOCAEN = 1;
EPwm1Regs.ETSEL.bit.SOCASEL = 4;
t
EPwm1Regs.ETPS.bit.SOCAPRD = 1;
EPwm1Regs.CMPA.half.CMPA = 0x0080;
EPwm1Regs.TBPRD = 0xFFFF;
EPwm1Regs.TBCTL.bit.CTRMODE = 0;

Setup 2 conv's on SEQ1

Setup ADCINA3 as 1st SEQ1 conv.
Setup ADCINA2 as 2nd SEQ1 conv.
Enable SOCA from ePWM to start SEQ1
Enable SEQ1 interrupt (every EOS)

in InitSysCtrl();
// Enable SOC on A group
// Select SOC from from CPMA on upcoun
// Generate pulse on 1st event
// Set compare A value
// Set period for ePWM1
// count up and start

// Wait for ADC interrupt

for(;;LoopCount++){
if(LoopCount==10000){
LoopCount=0;
}
}*/
//ConfigCpuTimer(&CpuTimer0,150,100000);
PieCtrlRegs.PIEIER3.bit.INTx1 = 1;
// PieCtrlRegs.PIEIER1.bit.INTx7 = 1;
PieCtrlRegs.PIEIER1.bit.INTx6 = 1;
IER |=1;
IER |= M_INT3;
EINT;
ERTM;
//CpuTimer0Regs.TCR.bit.TSS = 0;
while(1)

// CPU Timer 0
// ADC

// start timer0

{
//
//

asm("
NOP");
while(CpuTimer0.InterruptCount <5)
{
// wait for 500 ms
//EALLOW;
//SysCtrlRegs.WDKEY = 0x55;

// Servi

ce watchdog #1
//EDIS;
//}
// Display VR1 voltage
//while(CpuTimer0.InterruptCount <10)

// wait for 1000

ms
//

{
//EALLOW;
//SysCtrlRegs.WDKEY = 0x55;

ce watchdog #1
//

//EDIS;
}
// Display VR2 voltage
//CpuTimer0.InterruptCount = 0;

}
}
interrupt void epwm1_isr(void)
{
EPwm1Regs.TBPRD = PWM_CYCLE;
if(EPwm1_DB_Direction == DB_UP)
{
if(EPwm1Regs.DBFED < EPWM1_MAX_DB)
{
//EPwm1Regs.DBFED++;
//EPwm1Regs.DBRED++;
}
else
{
//EPwm1_DB_Direction = DB_DOWN;
//EPwm1Regs.DBFED--;
//EPwm1Regs.DBRED--;
}
}
else
{
if(EPwm1Regs.DBFED == EPWM1_MIN_DB)
{
//EPwm1_DB_Direction = DB_UP;
//EPwm1Regs.DBFED++;
//EPwm1Regs.DBRED++;
}
else
{
//EPwm1Regs.DBFED--;
//EPwm1Regs.DBRED--;
}
}
EPwm1TimerIntCount++;

// Servi

// Clear INT flag for this timer

EPwm1Regs.ETCLR.bit.INT = 1;
// Acknowledge this interrupt to receive more interrupts from group 3
PieCtrlRegs.PIEACK.all = PIEACK_GROUP3;
}
void InitEPwm1Example()
{
EPwm1Regs.TBPRD = anchoA;
EPwm1Regs.TBPHS.half.TBPHS = 0x0000;
EPwm1Regs.TBCTR = 0x0000;

// Set timer period

// Phase is 0
// Clear counter

// Setup TBCLK
EPwm1Regs.TBCTL.bit.CTRMODE = TB_COUNT_UPDOWN; // Count up
EPwm1Regs.TBCTL.bit.PHSEN = TB_DISABLE;
// Disable phase loading
EPwm1Regs.TBCTL.bit.HSPCLKDIV = TB_DIV4;
// Clock ratio to SYSCLKOUT
EPwm1Regs.TBCTL.bit.CLKDIV = TB_DIV4;
EPwm1Regs.CMPCTL.bit.SHDWAMODE
EPwm1Regs.CMPCTL.bit.SHDWBMODE
EPwm1Regs.CMPCTL.bit.LOADAMODE
EPwm1Regs.CMPCTL.bit.LOADBMODE

=
=
=
=

CC_SHADOW;
// Load registers every ZERO
CC_SHADOW;
CC_CTR_ZERO;
CC_CTR_ZERO;

// Setup compare
//EPwm1Regs.CMPA.half.CMPA = (Uint32)(duty_cycle * PWM_CYCLE);
// Set actions
EPwm1Regs.AQCTLA.bit.CAU = AQ_SET;
EPwm1Regs.AQCTLA.bit.CAD = AQ_CLEAR;

// Set PWM1A on Zero

EPwm1Regs.AQCTLB.bit.CAU = AQ_CLEAR;
EPwm1Regs.AQCTLB.bit.CAD = AQ_SET;

// Set PWM1A on Zero

// Active Low PWMs - Setup Deadband

EPwm1Regs.DBCTL.bit.OUT_MODE = DB_FULL_ENABLE;
EPwm1Regs.DBCTL.bit.POLSEL = DB_ACTV_LO;
EPwm1Regs.DBCTL.bit.IN_MODE = DBA_ALL;
EPwm1Regs.DBRED = EPWM1_MIN_DB;
EPwm1Regs.DBFED = EPWM1_MIN_DB;
EPwm1_DB_Direction = DB_UP;
// Interrupt where we will change the Deadband
EPwm1Regs.ETSEL.bit.INTSEL = ET_CTR_ZERO;
// Select INT on Zero event
EPwm1Regs.ETSEL.bit.INTEN = 1;
// Enable INT
EPwm1Regs.ETPS.bit.INTPRD = ET_3RD;
// Generate INT on 3rd event
}
interrupt void cpu_timer0_isr(void)
{
CpuTimer0.InterruptCount++;
//EALLOW;
//SysCtrlRegs.WDKEY = 0xAA;
//EDIS;

// service WD #2

PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
}
interrupt void adc_isr(void){
Voltage1 = AdcMirror.ADCRESULT0;
//Voltage2 = AdcMirror.ADCRESULT1;
//Voltage3 = AdcMirror.ADCRESULT2;
//Voltage4 = AdcMirror.ADCRESULT3;
// If 40 conversions have been logged, start over
/*if(ConversionCount == 9){
ConversionCount = 0;
}
else ConversionCount++;*/
// Reinitialize for next ADC sequence
AdcRegs.ADCTRL2.bit.RST_SEQ1 = 1;
AdcRegs.ADCST.bit.INT_SEQ1_CLR = 1;
PieCtrlRegs.PIEACK.all = PIEACK_GROUP1;
return;
}

// Reset SEQ1
// Clear INT SEQ1 bit
// Acknowledge interrupt to PIE