VLSI

VLSI Testing
Testing
Introduction
Introduction

Virendra Singh
Indian Institute of Science
Bangalore
virendra@computer.org

E0 286: Test & Verification of SoC Design

Lecture - 1

Reading
Reading Material
Material
Text Book:
M.L. Bushnell and V.D. Agrawal, Essentials of

1.
2.
3.

Electronic Testing for Digital, Memory and Mixed-Signal

VLSI Circuits, Springer, 2005
Reference Books:
H. Fujiwara, Logic Testing and Design for Testability,
MIT Press, 1985
M. Abramovici, M. Breuer, and A.D. Friedman, Digital
System Testing and Testable Design, Jayco Pub., 2002
S. Mourad and Y. Zorian, Principles of Testing
Electronic Systems, John Wiley, 2000
Journals:
IEEE TC, TCAD, and TVLSI
ACM TODAES

Jan 16, 2008

E0-286@SERC

Acknowledgement
Acknowledgement
Prof. Hideo Fujiwara, NAIST, Japan
Prof. Kewal K. Saluja, Univ. of Wisconsin, USA
Prof. Michiko Inoue, NAIST, Japan
Prof. Vishwani D. Agrawal, Auburn Univ., USA
Prof. Samiha Mourad, Santa Clara Univ., USA
Prof. Erik Larsson, Linkoping Univ., Sweden
Dr. Rubin Parekhji, TI, Bangalore
Dr. Subir Roy, TI, Bangalore

Jan 16, 2008

E0-286@SERC

VLSI
VLSI Realization
Realization Process
Process
Customers need
Determine requirements
Write specifications
Design synthesis and Verification
Test development
Fabrication
Manufacturing test
Chips to customer
Jan 16, 2008

E0-286@SERC

Definitions
Definitions
Design synthesis: Given an I/O function, develop a

procedure to manufacture a device using known

materials and processes.
Verification: Predictive analysis to ensure that the

synthesized design, when manufactured, will perform

the given I/O function.
Test: A manufacturing step that ensures that the

physical device, manufactured from the synthesized

design, has no manufacturing defect.

Jan 16, 2008

E0-286@SERC

Verification
Verification vs.
vs. Test
Test
Verification
Verifies correctness of
design.
Performed by simulation,
hardware emulation, or
formal methods.

Performed once prior to

manufacturing.
Responsible for quality of
design.
Jan 16, 2008

Test
Verifies correctness of
manufactured hardware.
Two-part process:
1. Test generation: software
process executed once
during design
2. Test application: electrical
tests applied to hardware
Test application performed on
every manufactured device.
Responsible for quality of
devices.
E0-286@SERC

Problems
Problems of
of Ideal
Ideal Tests
Tests

Ideal tests detect all defects produced in the

manufacturing process.
Ideal tests pass all functionally good devices.
Very large numbers and varieties of possible
defects need to be tested.
Difficult to generate tests for some real defects.
Defect-oriented testing is an open problem.

Jan 16, 2008

E0-286@SERC

Real
Real Tests
Tests

Based on analyzable fault models, which may not

map on real defects.
Incomplete coverage of modeled faults due to
high complexity.
Some good chips are rejected. The fraction (or
percentage) of such chips is called the yield loss.
Some bad chips pass tests. The fraction (or
percentage) of bad chips among all passing chips
is called the defect level.

Jan 16, 2008

E0-286@SERC

Testing
Testing as
as Filter
Filter Process
Process
Good chips
Prob(good) = y

Prob(pass test) = high

Pr
ob
( fa
il

Fabricated
chips
Pr

s
s
pa
(
ob

=
)
st

te
te
st
)

w
lo

=l
ow

Defective chips
Prob(bad) = 1- y

Jan 16, 2008

Prob(fail test) = high

E0-286@SERC

Mostly
good
chips
Tested
chips
Mostly
bad
chips

Roles
Roles of
of Testing
Testing

Detection: Determination whether or not the device

under test (DUT) has some fault.
Diagnosis: Identification of a specific fault that is
present on DUT.
Device characterization: Determination and
correction of errors in design and/or test
procedure.
Failure mode analysis (FMA): Determination of
manufacturing process errors that may have
caused defects on the DUT.

Jan 16, 2008

E0-286@SERC

10

Costs
Costs of
of Testing
Testing

Design for testability (DFT)

Chip area overhead and yield reduction
Performance overhead
Software processes of test
Test generation and fault simulation
Test programming and debugging
Manufacturing test
Automatic test equipment (ATE) capital cost
Test center operational cost

Jan 16, 2008

E0-286@SERC

11

Design
Design for
for Testability
Testability (DFT)
(DFT)
DFT refers to hardware design styles or added hardware
that reduces test generation complexity.
Motivation: Test generation complexity increases
exponentially with the size of the circuit.
Example: Test hardware applies tests to blocks A
and B and to internal bus; avoids test generation
for combined A and B blocks.
Int.
Primary
Primary
bus
Logic
Logic
outputs
inputs
block A
block B
(PO)
(PI)
Test
input
Jan 16, 2008

Test
output
E0-286@SERC

12

Testing
Testing Principle
Principle

Jan 16, 2008

E0-286@SERC

13

ADVANTEST
ADVANTEST Model
Model
T6682
T6682 ATE
ATE

Jan 16, 2008

E0-286@SERC

14

Cost
Cost of
of Manufacturing
Manufacturing
Testing
Testing

0.5-1.0GHz; analog instruments; 1,024 digital pins:

ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M
Running cost (five-year linear depreciation)
= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/year
Test cost (24 hour ATE operation)
= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second

Jan 16, 2008

E0-286@SERC

15

40,000

100

al
t
To st
co

Fixed cost

25,000
20,000

50

Va

l
b
ria

Average cost

t
s
co

50k

100k

150k

Average Cost (cents)

Fixed, Total and Variable

Costs ($)

Cost
Cost Analysis
Analysis Graph
Graph

0
200k

Miles Driven
Jan 16, 2008

E0-286@SERC

16

A
A Modern
Modern VLSI
VLSI Device
Device
System-on-a-chip
System-on-a-chip (SOC)
(SOC)

Data
terminal

Jan 16, 2008

DSP
core

RAM
ROM

Interface
logic

Mixedsignal
Codec

E0-286@SERC

Transmission
medium

17