A

ZZZ0

PCB
MB

Compal Confidential
PICASSO M Schematics Document

Nvdia(T30S) + LPDDRII
QAJA0-LA-8511P

REV: 1.0

2012-01-18

The content in this document contains confidential information of Compal Electronics, Inc.
that is protected under all applicable trade secrets laws and regulations.
If you are not the intended recipient or otherwise authorized to receive such information,
please do not copy, distribute or otherwise use the information contained herein and please
destroy this communication accordingly.

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Cover Page
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Wednesday, January 18, 2012
E

Sheet

of

38

Compal Confidential
Model Name : NVIDIA T30S System Block Diagram
26MHz
32KHz
LPDDR2
512MB/1GB

Power ON

P.9

PMIC
CORE_PWR_REQ
TPS659110
CPU_PWR_REQ

JTAG

SYS_RESET_N

VIN

Debug
Test Point

P.7

I2S

PMU_32K_IN
P.31~P.33

Audience
eS305

UART4

Audio Codec
WM8903

P.14

PWR_I2C

P.15

GPS Antenna
UART2

HDMI_DDC
Micro HDMI

P.19

HDMI Switch
(1.8V/3.3V)

Nvidia
UART3
SDIO
DAP

Signal Switch

P.15

AzureWave
AW-AH660
P.22

3G Modem Antenna

P.12

P.20

MIC & Audio Jack

LVDS Transmitter
(V105A)

Micro USB

P.15

BT/WLAN Antenna

P.13

P.15

P.21

Touch Panel
Control
10.1" LCD
1920*1200

Speaker x 2
(1W)

Broadcom
BCM47511

T30S

P.13

Audio AMP
APA2010

USB2

3G Modem Module

SIM Card

P.18

Client
Host

P.20

P.18

P-Senser
IQS12800100TSR
Dock/B

CAMERA
CIS(MIPI)
5M(CJAA525)
2M(CBFA152) CAM_I2C

I2C

P.17

CAM_I2C
SDIO4
(1.8V)

EEPROM

SDIO1
(3.3V)

GYRO Sensor
MPU-3050

P.10

eMMC

P.11

CAM_I2C

Micro SD slot

P.16

CAM_I2C

Light Sensor
STK2203

E-Compass
AKM8975

Func/B

Dock/B

P.20

IME
G-Sensor
KXTF9-4100

P.16

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

SYSTEM BLOCK
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Wednesday, January 18, 2012
E

Sheet

of

38

Board ID

Voltage Rails

Power Plane

Description

VIN

Adapter power supply (19V)

B+

AC or battery power rail for power circuit.

+VDD_1V2_RTC_TEGRA

Power for RTC and always-on core logic.

VDD_1V2_SOC

Power for remainder of core logic

+AVDD_1V1_PLL_TEGRA

AVDD_PLL power rail

+VDD_1V8_PMU_VRTC

RTC power rail

+VDD_1V8_SYS_TEGRA

System power rail

+AVDD_3V3_USB_TEGRA

USB power rail

+VDD_2V85_EMMC

Core voltage for EMMC

+VDD_1V8_CAM_TEGRA

Core voltage for CAMERA

+AVDD_3V3_HDMI_S

HDMI power rail

VDD_1V8_GEN

1.8V switched power rail for standby mode

+VDD_3V3_DDR_RX_TEGRA

DDR RX power rail

+3VS

3.3V switched power rail for standby mode

+5VS

5V switched power rail for standby mode

+VDD_LED_BL

LED power rail

+VDD_3V3_SDMMC1_TEGRA

Micro SD power rail

+VDD_VCM_3V3

CAMERA power rail

+VDD_1V2_DDR_MEM

DDR power rail

PICASSO 2

GEN1_I2C <+VDD_1V8_SENSOR >

Address<Write,Read>

Device

Gyro
E Compass
Light Senser

0xD0 , 0xD1
0x18 , 0x19
0x38 , 0x39

PICASSO M
LPDDR2

GEN2_I2C / TS_I2C
Device

< +VDD_3V3_GMI_TEGRA >

Address<Write,Read>

Touch Screen

0x98 , 0x99

CAM_I2C < +VDD_1V8_CAM_TEGRA >

Device

Address<Write,Read>

Camera 5M
Camera 2M
Flash LED

LVDS strap pin

0x78 , 0x79
0x20 , 0x21
0x66 , 0x67

PWR_I2C < +VDD_1V8_SYS_TEGRA>

Device

Address<Write,Read>

Thermal Senser
ES305
Codec
PMU
TPS62361
BATT Conn
EEPROM (Low level)
EEPROM (High level)

0x98 , 0x99
0x3E
0x34 , 0x35
0x2D
0x60
0xAA , 0xAB
0xA0 , 0xA1
0xA2 , 0xA3

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Notes List
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

of

38

R453
2
1
47_0402_5%

NV_LCD_PCLK

L49
LCD_PCLK_R 1
1

+VDD_3V3_GMI_TEGRA

+VDD_3V3_GMI_TEGRA

27NH_LQG15HS27NJ02D_5%_0402
2
1
C165
C164

LCD_PCLK

U1E

<12>

4/21 GMI

12P_0201_50V8J

(1.8/3.3V)

2
C147

8/21 LCD

LCD_D00
LCD_D01
LCD_D02
LCD_D03
LCD_D04
LCD_D05
LCD_D06
LCD_D07
LCD_D08
LCD_D09
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_D18
LCD_D19
LCD_D20
LCD_D21
LCD_D22
LCD_D23

LCD_M1
LCD_PWR0
LCD_PWR1
LCD_PWR2

LCD_SCK
LCD_CS0*
LCD_CS1*
LCD_SDOUT
LCD_SDIN
LCD_DC0
LCD_DC1

CRT_HSYNC
CRT_VSYNC
DDC_SCL
DDC_SDA

AN21

PD

AK24
AR19
AK20
AL17

PU
PD
PU
PU

AR17
AP26
AM18
AN19
AJ23
AR23
AK16
AK22
AU21
AM26
AR21
AU27
AT18
AJ17
AH18
AL21
AM22
AJ19
AT20
AT24
AN27
AU23
AR27
AM24

PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD
PD

AM20

NV_LCD_PCLK

LCD_DE <12>
LCD_HSYNC <12>
LCD_VSYNC <12>
LCD_D00
LCD_D01
LCD_D02
LCD_D03
LCD_D04
LCD_D05
LCD_D06
LCD_D07
LCD_D08
LCD_D09
LCD_D10
LCD_D11
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D16
LCD_D17
LCD_D18
LCD_D19
LCD_D20
LCD_D21
LCD_D22
LCD_D23

<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>
<12>

GMI_CS0*
GMI_CS1*
GMI_CS2*
GMI_CS3*
GMI_CS4*
GMI_CS6*
GMI_CS7*
GMI_ADV*
GMI_CLK
GMI_RST*
GMI_WAIT
GMI_WP*
GMI_IORDY

PD

AN17
AP20
AN25

PD
PD
PD

AK26
AL23
AP18
AM28
AR25

PU
PU
PU
PU
PU

AL27
AP24

PD
PD

AK18
AJ21

PU
PU

AH20
AT26

Z
Z

AN23

LCD_PWM_OUT <13>
DISPOFF# <13,31>
EN_T30S_FUSE_3V3 <23>
LCD_DCR <13>

PCB_ID0
PCB_ID1
PCB_ID2

EN_SENSOR_3V3

GMI_OE*
GMI_WR*

P8
M8
N9
R9
R11
P10
G5
K8
H4
M10
L9

VIB_EN_T30S <20>
TS_PWR_EN <13>
EN_VDDLCD_T30S <13>
EN_WIFI_VDD <22>
PU
PU
1
1
PU
PU
PU

BOARD_ID0 R158
BOARD_ID1 2

TS_INT# <13>
CHARGER_STAT <27>
0_0201_5%
1 EN_P_SENSOR

EN_P_SENSOR

<20>

LVDS_SHTDN#

<12>

GMI_DQS

1 100K_0201_5%

NAND_D4

R38

X76_SAM_1GB@
2
1 100K_0201_5%

NAND_D5

R43

1 100K_0201_5%

NAND_D6

R84

1 100K_0201_5%

NAND_D7

R85

1 100K_0201_5%

NAND_D4

R5

X76_ELP_1GB@
2
1 100K_0201_5%

NAND_D5

R6

1 100K_0201_5%

NAND_D6

R7

1 100K_0201_5%

NAND_D7

R8

1 100K_0201_5%

8/22 Change BOM structure

R18
100K_0201_5%

PCB_ID0

R63

PCB_ID1

R87

PCB_ID2

R100 2

+VDD_3V3_GMI_TEGRA

1 100K_0201_5%
QAJ70@

BOOT_PD

1 100K_0201_5%
NH660@

L1 0

1 100K_0201_5%
LTE@

L5 0
N5 PU
L3 PU

EN_HDMI_5V0 <19>
3G_DISABLE# <18>
3G_WAKE# <18>

R7 PU

POUT_3G <20>

M2 1
M6 1

EN_SENSOR_3V3

POUT_3G_1 <20>
TEMP_ALERT# <7>
POUT_WIFI <16>

M4 1

R2

<23>

11/6 Add for COMPAL EMI request.

GMI_A16
GMI_A17
GMI_A18
GMI_A19

BOOT_PD

+VDD_3V3_GMI_TEGRA

NAND_D4
NAND_D5
NAND_D6
NAND_D7

LCD_WR*
LCD_DE
LCD_HSYNC
LCD_VSYNC

1 100K_0201_5%

8/22 Change BOM structure to LPDDR2 & EMMC

C2

LCD_PCLK

NAND_D0
BOOT_PD

TS_PWR_EN

R12
100K_0201_5%

FORCE_RECOVERY#
NOR_BOOT

L7 Z

BOARD_ID0

R78

1 100K_0201_5%

BOARD_ID1

R88

1 100K_0201_5%

PCB_ID0

R152 2

PCB_ID1

R153 2

1 100K_0201_5%
QAJ50@
1 100K_0201_5%
AH663@

0.1U_0201_10V6K

C1
2

2
4.7U_0402_6.3V6M

VDDIO_LCD_1
VDDIO_LCD_2

2
C4

J7 Z
K6 Z
J3 Z
H2 Z
P4 Z
P6 Z
N3 Z
R3 Z
G3 PD
E1 PD
J5 PD
J1 PD
F2 Z
F4 Z
P2 Z
R5 Z

TS_RST# <13>

PCB_ID2

R154 2

BOARD_ID0

R79

BOARD_ID1

R89

1 100K_0201_5%
NONLTE@
2
1 100K_0201_5%
@
2
1 100K_0201_5%
@

EN_WIFI_VDD
1

(1.8/3.3V)
AG23
AH24

GMI_AD00
GMI_AD01
GMI_AD02
GMI_AD03
GMI_AD04
GMI_AD05
GMI_AD06
GMI_AD07
GMI_AD08
GMI_AD09
GMI_AD10
GMI_AD11
GMI_AD12
GMI_AD13
GMI_AD14
GMI_AD15

U1I

VDDIO_GMI_1
VDDIO_GMI_2

R1

GEN2_I2C_SCL
GEN2_I2C_SDA

DDC_SCL_R
DDC_SDA_R

+VDD_3V3_GMI_TEGRA

R17
100K_0201_5%

D2 Z
E3 Z

NOR_BOOT

GEN2_I2C_SCL <13>
GEN2_I2C_SDA <13>

R22

1 100K_0201_5%

+VDD_3V3_LCD_TEGRA

0.1U_0201_10V6K

P12
T12

RF

C3

4.7U_0402_6.3V6M

12P_0201_50V8J

3300P_0201_16V6K

NAND_D0

9/15 Modify R23 from 100K to 47K.

9/15 Add R90 for FORCE_RECOVERY issue
9/19 Modify Q44 part number to SB00000J500 .

<19>
<19>

+VDD_3V3_GMI_TEGRA
T30S-R-A3-1.4G_FCCSP681

HDMI_DET_T30S

<19>

HDMI_INT

AP8

AVDD_HDMI

HDMI_TXCN
HDMI_TXCP

(3.3V)

2
C7
0.1U_0201_10V6K

HDMI_TXD0N
HDMI_TXD0P
1
HDMI_TXD1N
HDMI_TXD1P

VDD_1V8_GEN

HDMI_TXD2N
HDMI_TXD2P

L2
1
2
MPZ1005S300CT_2P

AVDD_HDMI_PLL

AT8

AVDD_HDMI_PLL

(1.8V)

HDMI_PROBE
HDMI_RSET

AR9
AN9

HDMI_TXCN <19>
HDMI_TXCP <19>

AP12
AN13

HDMI_TXD0N <19>
HDMI_TXD0P <19>

AR13
AP14

HDMI_TXD1N <19>
HDMI_TXD1P <19>

AU11
AT12
HDMI_PROBE

AM8

HDMI_RSET

+VDD_1V8_SDMMC4_TEGRA

@ PAD T1

VDDIO_SDMMC4

SDMMC4_DAT0
SDMMC4_DAT1
SDMMC4_DAT2
SDMMC4_DAT3
SDMMC4_DAT4
SDMMC4_DAT5
SDMMC4_DAT6
SDMMC4_DAT7

C6
2

0.1U_0201_10V6K

C5
4.7U_0402_6.3V6M

SDMMC4_CLK
SDMMC4_CMD

(2.8V)
AD2

AVDD_VDAC

VDAC_R
VDAC_G
VDAC_B

2
1

Q44
S TR DMN3150LW-7 1N SOT-323-3

2
G
R54
1M_0201_1%

Vth=1.4V
B

SDMMC4 : eMMC

(1.2/1.8V)

9/21 VDAC

AO3413_SOT23-3

U1F

E7
R26
1K_0201_1%

U1J

Q6

2
G

5/21 SDMM4

SB93413000000 and SB000009O00

+3VS

U55

08/16 Change U55 footprint

08/16 Delete U56 footprint
Add

10/03 Co-lay SOT-23 and SC-70

HDMI_TXD2N <19>
HDMI_TXD2P <19>

AR11

T30S-R-A3-1.4G_FCCSP681

74AUP1G02GW_TSSOP5

C8
0.1U_0201_10V6K

AVDD_HDMI_R

<7,20> VOL_DOWN#

47K_0201_1%
2 FORCE_RECOVERY#

1
2
MPZ1005S300CT_2P

<7,20> VOL_UP#

R90
1

10/21 HDMI

L1
B

2.2K_0201_1%
2

GEN2_I2C_SCL
GEN2_I2C_SDA

2.2K_0201_1%

U1K
+AVDD_3V3_HDMI_S

T21 PAD
@

R10 @

R11

Modify R10&R11 from mount to unmount

G Vcc

9/29 Leakage Issue

T30S-R-A3-1.4G_FCCSP681

R23
47K_0201_1%
+VDD_1V8_SYS_TEGRA

+VDD_3V3_GMI_TEGRA

AH14
AJ13
AH12

SDMMC4_RST*

B6
G9
C5
B4
A5
D6
C7
D8

Z
Z
Z
Z
Z
Z
Z
Z

F8 PU
H10 PU
B8

EMMC_DA0
EMMC_DA1
EMMC_DA2
EMMC_DA3
EMMC_DA4
EMMC_DA5
EMMC_DA6
EMMC_DA7

<11>
<11>
<11>
<11>
<11>
<11>
<11>
<11>

EMMC_CLK <11>
EMMC_CMD <11>
EMMC_RST# <11>

+AVDD_3V3_HDMI_S

Q2

@
NTS4101PT1G_SC70-3
3
10MIL
0.1A 3.3V

VDAC_VREF

2
G

R27
1M_0201_1%
EN_HDMI_3V3#

AN11

VDAC_RSET

AM12

T30S-R-A3-1.4G_FCCSP681
T30S-R-A3-1.4G_FCCSP681

VDD_1V8_GEN

Q3
BSS138W-7-F_SOT323-3

2
G

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

T30S(1/5)LCD/CRT/HDMI/NAND
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

of

38

Acer request

C13

C12
2

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

SDMMC1 : SD card

C11

C10
2

4.7U_0402_6.3V6M

1
D

4.7U_0402_6.3V6M

VDD_1V2_MEM

U1D

VDD_1V2_MEM

3/21 DDR MEMORY

U1P

+VDD_3V3_SDMMC1_TEGRA

SDMMC_CLK <20>
SDMMC_CMD <20>

C16

0.1U_0201_10V6K

+VDD_3V3_SDMMC1_TEGRA

C110

K12
L23

+VDD_1V0_DDR_HS_TEGRA

1
C24

0.1U_0201_10V6K

9/22
Add U1.U3 GPIO to control Power CP function.

C109

T30S-R-A3-1.4G_FCCSP681

1
6/21 SDMMC3

VDDIO_SDMMC3

(1.8/2.8~3.3V)
C26 1

4.7U_0402_6.3V6M

C25

0.1U_0201_10V6K

M36

SDMMC3_DAT0
SDMMC3_DAT1
SDMMC3_DAT2
SDMMC3_DAT3
SDMMC3_DAT4
SDMMC3_DAT5
SDMMC3_DAT6
SDMMC3_DAT7
SDMMC3_CLK
SDMMC3_CMD

N33
L37
M34
P34
J37
N29
M32
M28

PU
PU
PU
PU
PU
PU
PU
PU

WFMMC_DAT0
WFMMC_DAT1
WFMMC_DAT2
WFMMC_DAT3
@ PAD T17

<22>
<22>
<22>
<22>

SDMMC3_COMP_PU
SDMMC3_COMP_PD

DDR_DM0
DDR_DM1
DDR_DM2
DDR_DM3

(1.05V)
VDD_DDR_HS_1
VDD_DDR_HS_2

DDR_DQS0N
DDR_DQS0P
DDR_DQS1N
DDR_DQS1P
DDR_DQS2N
DDR_DQS2P
DDR_DQS3N
DDR_DQS3P
DDR_A00
DDR_A01
DDR_A02
DDR_A03
DDR_A04
DDR_A05
DDR_A06
DDR_A07
DDR_A08
DDR_A09
DDR_A10
DDR_A11
DDR_A12
DDR_A13
DDR_A14

9/26 Modify BOARD_ID3 from U1.J37 to U1.R37

J35 PU
M30 PU

WFMMC_CLK <22>
WFMMC_CMD <22>

DDR_RAS*
DDR_CAS*

+VDD_1V8_SDMMC3_TEGRA

<BOM Structure>
<BOM Structure>

C215

U1O

+VDD_1V8_SDMMC3_TEGRA

VDD_DDR_RX

33P 50V J NPO 0201

C205

: WIFI

33P 50V J NPO 0201

SDMMC3

(2.8/3.3V)

<27>
0.1U_0201_10V6K

CP_GPIO

C108

PD
Z

0.1U_0201_10V6K

Y6 Z
W9 Z
U3
U5

C30

GPIO_PV2
GPIO_PV3
CLK2_OUT
CLK2_REQ

A15

1
C23

4.7U_0402_6.3V6M

2 33.2_0402_1%

C21

0.1U_0201_10V6K

R30

C20

SDMMC1_COMP_PD

0.1U_0201_10V6K

U9

DDR_DQ00
DDR_DQ01
DDR_DQ02
DDR_DQ03
DDR_DQ04
DDR_DQ05
DDR_DQ06
DDR_DQ07
DDR_DQ08
DDR_DQ09
DDR_DQ10
DDR_DQ11
DDR_DQ12
DDR_DQ13
DDR_DQ14
DDR_DQ15
DDR_DQ16
DDR_DQ17
DDR_DQ18
DDR_DQ19
DDR_DQ20
DDR_DQ21
DDR_DQ22
DDR_DQ23
DDR_DQ24
DDR_DQ25
DDR_DQ26
DDR_DQ27
DDR_DQ28
DDR_DQ29
DDR_DQ30
DDR_DQ31

+VDD_3V3_DDR_RX_TEGRA
1

C19

2 33.2_0402_1%

0.1U_0201_10V6K

C18

R29

0.1U_0201_10V6K

SDMMC1_COMP_PD

SDMMC1_COMP_PU

0.1U_0201_10V6K

SDMMC1_COMP_PU

AF10

VDDIO_DDR_01
VDDIO_DDR_02
VDDIO_DDR_03
VDDIO_DDR_04
VDDIO_DDR_05
VDDIO_DDR_06
VDDIO_DDR_07
VDDIO_DDR_08
VDDIO_DDR_09
VDDIO_DDR_10
VDDIO_DDR_11
VDDIO_DDR_12
VDDIO_DDR_13
VDDIO_DDR_14

4.7U_0402_6.3V6M

PU
PU

<20>
<20>
<20>
<20>

C15

T6
T8

SDMMC_DAT0
SDMMC_DAT1
SDMMC_DAT2
SDMMC_DAT3

C22

PU
PU
PU
PU

0.1U_0201_10V6K

SDMMC1_CLK
SDMMC1_CMD

U7
W11
U1
Y10

0.1U_0201_10V6K

4.7U_0402_6.3V6M

SDMMC1_DAT0
SDMMC1_DAT1
SDMMC1_DAT2
SDMMC1_DAT3

C14

(1.8/2.8~3.3V)
VDDIO_SDMMC1

0.1U_0201_10V6K

17/21 SDMMC1

R1
C17 1

(1.2/1.25/1.35/1.5V)
M14
M16
M18
M20
M22
M24
N15
N17
N19
N21
N23
P26
R25
T26

L35

SDMMC3_COMP_PU

R31

2 33.2_0402_1%

N35

SDMMC3_COMP_PD

R32

2 33.2_0402_1%

DDR_WE*
DDR_BA0
DDR_BA1
DDR_BA2

T30S-R-A3-1.4G_FCCSP681

DDR_CS0*
DDR_CS1*

<BOM Structure>

DDR_ODT0
DDR_ODT1
DDR_CKE0
DDR_CKE1

U1M
15/21 HSIC

Y2

(1.2V)
VDDIO_HSIC

HSIC_DATA
HSIC_STROBE

DDR_CLK*
DDR_CLK

AC5
AD6

DDR_RESET
HSIC_REXT

AD10

DDR_QUSE0
DDR_QUSE1
DDR_QUSE2
DDR_QUSE3

T30S-R-A3-1.4G_FCCSP681

E29
F28
B30
E25
A29
C25
D24
F24
F14
C15
D14
H14
C13
C11
D12
A9
D30
K24
G27
H24
E27
G29
H28
J25
K14
F10
L15
J15
H12
G11
C9
E9
F26
E13
C29
J13
B26
A27

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31

<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>

DDR_A_DM0
DDR_A_DM1
DDR_A_DM2
DDR_A_DM3

<9>
<9>
<9>
<9>

DDR_A_DQS#0 <9>
DDR_A_DQS0 <9>

A11
B12

DDR_A_DQS#1 <9>
DDR_A_DQS1 <9>

K26
H26

DDR_A_DQS#2 <9>
DDR_A_DQS2 <9>

E11
F12

DDR_A_DQS#3 <9>
DDR_A_DQS3 <9>

J23
C23
E21
A23
E23
B18
A17
F18
B14
C17
F16
G17
J17
H18
J19

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9

<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>
<9>

J21
H20
H22
B

F20
G21
F22
C21
D20

M_CS#0 <9>
M_CS#1 <9>

G23
L19
B20
E19

M_CKE0 <9>
M_CKE1 <9>

D18
C19

M_CLK_DDR#0 <9>
M_CLK_DDR0 <9>

K20

DDR_RESET

C27
D26
G15
H16

QUSE0
QUSE1
QUSE2
QUSE3

@ PAD T3
R33

2 0_0201_5%

R34

2 0_0201_5%
VDD_1V2_MEM

DDR_COMP_PU
U1N

DDR_COMP_PD

E17

DDR_COMP_PU

R35

2 49.9_0402_1%

E15

DDR_COMP_PD

R36

2 49.9_0402_1%

16/21 IC_USB

AB8

AVDD_IC_USB

(1.8/3.0V)

IC_USB_DN
IC_USB_DP

AD4
AE3

T30S-R-A3-1.4G_FCCSP681

IC_USB_REXT

AD8

T30S-R-A3-1.4G_FCCSP681

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

T30S(2/5)OSC/PLL/SYS/DDR
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

of

38

U1L
11/21 USB

U1Q is not place on grid , need check connection

+AVDD_3V3_USB_TEGRA

AVDD_USB

C27

U1Q

RF note

13/21 AUDIO

CLK1_OUT

DAP1_SCLK
DAP1_FS
DAP1_DOUT
DAP1_DIN

AUDIO_CLK

E35

R37

L29 PD
B34 PD
D32 PD
A33 PD

2 0_0201_5%

AUDIO_SEL <14>
AUDIO_RST# <14>
ES305_INT_R <14>
ENABLE_USB_HOST

AUDIO_CLK_R

<15>

AUDIO_SCLK2 <14>
AUDIO_FS2 <14>
AUDIO_DOUT2 <14>
AUDIO_DIN2 <14>

2
SPDIF_IN
SPDIF_OUT

SPI1_SCK
SPI1_CS0*
SPI1_MOSI
SPI1_MISO

L31 PU
J31 PU

G35
H36
L33
F36

PU
PU
PU
PD

<20>

AVDD_USB_PLL

AH6

USB2_VBUS

AG3
AG1

USB2_DN
USB2_DP

10/24 Add BATT_LEARN GPIO to Power request.

10/03 Add D18 on +T30S_USB1 to protect CPU.
10/19 Modify D18 from +T30S_USB1 to VBUS_USB
BATT_LEARN <27>
12/2 Modify D18 from moun to @,Add Zener on samll board.
COMPASS_DRDY

USB1_ID

(1.8V)
V2

C29

DAP2_SCLK
DAP2_FS
DAP2_DOUT
DAP2_DIN

PD
PD
PD
PD

<20>
<20>

+AVDD_1V8_USB_PLL_TEGRA
<20,27>

8/24 Modify Off-Page type.

H34
K30
F34
C33

AU5

USB1_ID

0.1U_0201_10V6K

C28

VDDIO_AUDIO

0.1U_0201_10V6K

G33

(1.8/3.3V)

USB1_DN
USB1_DP

4.7U_0402_6.3V6M

+VDD_1V8_AUDIO_TEGRA

+T30S_USB1

AL5
AM4

USB1_DN
USB1_DP

AF8

USB1_VBUS

(3.3V)
AB6

3G_USB_DN
3G_USB_DP

<18>
<18>

AJ7

USB2_ID

<20>

SC400003Z00
2

10MIL
0.1A 3.3V

3
D18 @

R42
1M_0201_1%
2

+T30S_USB1

AF4
AE5

USB3_DN
USB3_DP

EN_T30S_USB1
T30S-R-A3-1.4G_FCCSP681

AR5

USB3_VBUS

BZT52-B5V6S_SOD323-2
2

LIGHT_INT <20>
HP_DET# <20>
CDC_IRQ# <15>
EN_ES305_OSC <14>
GYRO_INT_R <16>

VBUS_USB

Q18
AO3413_SOT23-3

+T30S_USB1

PU
PU
PU
PU
PD
PD

K32
J33
B32
F30
D36
E37

2
G

SPI2_SCK
SPI2_CS0*
SPI2_CS1*
SPI2_CS2*
SPI2_MOSI
SPI2_MISO

USB_HOST_DN
USB_HOST_DP

<20>
<20>

+AVDD_3V3_USB_TEGRA

AK12

USB3_ID
Q5
BSS138W-7-F_SOT323-3

2
G

R39
AE9

USB_REXT

USB_REXT

1
1K_0201_1%

T30S-R-A3-1.4G_FCCSP681
+AVDD_1V2_DSI_CSI_TEGRA

USB VBUS overvoltage protection

U1H
7/21 DSI/CSI

(1.2V)
5M_CAM_CLK#_R <17>
5M_CAM_CLK_R <17>

+VDD_1V8_CAM_TEGRA
CAM_I2C_SCL

5M_CAM_DA1#_R <17>
5M_CAM_DA1_R <17>

R40
2.2K_0201_1%

U1G

+VDD_1V8_CAM_TEGRA

2M_CAM_DA1#_R <17>
2M_CAM_DA1_R <17>

AT6
AP6

2M_CAM_DA2#_R <17>
2M_CAM_DA2_R <17>

C35

AK4
AL3

CAM_I2C_SCL
CAM_I2C_SDA

0.1U_0201_10V6K

CSI_D2BN
CSI_D2BP

2M_CAM_CLK#_R <17>
2M_CAM_CLK_R <17>
C34

CSI_D1BN
CSI_D1BP

AR7
AN7

4.7U_0402_6.3V6M

CSI_CLKBN
CSI_CLKBP

(1.8/2.8 ~ 3.3V)
VDDIO_CAM

CAM_MCLK

AK14
AN15

Z
Z

AG15

Z R72

AM10
AM14
AL15
AJ15
AM16
AT14

Z
Z
Z
Z
Z
Z

AU15
AR15

PU
PU

CAM_I2C_SCL
CAM_I2C_SDA
1

<17,26,35>
<17,26,35>

2 0_0201_5%
C372

GPIO_PBB0
GPIO_PBB3
GPIO_PBB4
GPIO_PBB5
GPIO_PBB6
GPIO_PBB7
GPIO_PCC1
GPIO_PCC2

C187

1
3

R41
2.2K_0201_1%

18/21 CAM

AL11

2M_CAM_RST# <17>
5M_CAM_PWDN <17>
5M_CAM_RST# <17>
2M_CAM_PWDN <17>
DOCK_DET# <20>

RF note

39P_0201_50V8J

5M_CAM_DA2#_R <17>
5M_CAM_DA2_R <17>

10P_0201_50V8J

AL9
AK10

CAM_I2C_SDA
C186
39P_0201_50V8J

AJ5
AJ3

CSI_D2AN
CSI_D2AP

AP2
AN3

CSI_D1AN
CSI_D1AP

CSI_CLKAN
CSI_CLKAP

AVDD_DSI_CSI

0.1U_0201_10V6K

4.7U_0402_6.3V6M

C31

C32

AF2

CAM_MCLK <17>

9/26 Swap U1.AM16 to U1.AM10 for WAKE UP issue

T30S-R-A3-1.4G_FCCSP681
DSI_CLKAN
DSI_CLKAP

+AVDD_1V2_DSI_CSI_TEGRA

AN1
AM2
1

DSI_D1AN
DSI_D1AP

AJ1
AK2

DSI_D2AN
DSI_D2AP

AH8
AG9

R44
453_0402_1%
4

DSI_CSI_RUP

DSI_CSI_RUP

AT4

DSI_CSI_RDN
1

DSI_CSI_RDN

AG7

R45
49.9_0402_1%

T30S-R-A3-1.4G_FCCSP681

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

T30S(3/5)USB/SDIO/UART/AUDIO
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
E

of

38

GPS_RESET#

AF34
AG35
AF28
AL35

PD
PD
PD
PD

AH32
AF32

0
Z

BT_RST# <22>

9/22
Change EN_3V3_MODEM from AE35 to AF36.
9/26
Change BT_PD# from Y36 to AJ33

<20>

AN29

P36

(1.05V)

09/15

T30S_XTAL_IN

R33

Add for Acer request.

+VDD_1V8_SYS_TEGRA

AVDD_PEXB

PEX_L5_TXN
PEX_L5_TXP

AT30
AU29

Deep Sleep : OFF

XTAL_OUT

T30S_XTAL_OUT

R35

R91
100K_0201_5%

+AVDD_1V1_PLL_TEGRA

(1.05V)

LINE_OUT_DET#

VDD_PEXB

(1.05V)
AN31

XTAL_IN

B24

<14>

AVDD_OSC

(1.8V)

BT_PCM_IN <22>
BT_PCM_OUT <22>
BT_PCM_SYNC <22>
BT_PCM_CLK <22>

AVDD_PEX_PLL

PEX_L5_RXN
PEX_L5_RXP

AP30
AR29

+VDD_1V8_BB_TEGRA

K18
A21
AG5

AVDD_PLLA_P_C_S (1.1V)
AVDD_PLLX

(1.1V)

AVDD_PLLM

(1.1V)

AVDD_PLLU_D

(1.1V)

PLL_S_PLL_LF

PLL_S_PLL_LF

R27

10/19 Modify R51 and R52 to 1K ohm

+VDD_1V8_SYS_TEGRA

T30S-R-A3-1.4G_FCCSP681

1
2/21 OSC, PLL & SYS

AVDD_OSC

1
2
MPZ1005S300CT_2P

19/21 PEX

AM30
CLK3_OUT
CLK3_REQ

U1C

L3

U1T
DEBUG_UART1_RX
BT_PD# <22>

CLK_12M_ES305

VDD_1V8_GEN

<18,30>

<21>
<18,21>

1 R149
2
0_0201_5%

10P_0201_50V8J

EN_3V3_MODEM
GPS_PWRON
GPS_RESET#

C37
T30S_XTAL_OUT

CPU_PWR_REQ

0.1U_0201_10V6K

Z
Z
Z
Z
Z
Z DEBUG_UART1_RX_R
Z

CORE_PWR_REQ

Y10
26MHZ_10PF_7M26000039

AK34
AF36
AN37
AG33
AM36
AG37
AJ33

BT_UART_TXD <22>
BT_UART_RXD <22>
BT_UART_RTS# <22>
BT_UART_CTS# <22>

2M_0201_5%
100K_0201_5%

PU
PU
PU
PU

<16,20>
<16,20>

R50
R49

4 G

AE33
AJ35
AK36
AJ37

GEN1_I2C_SCL
GEN1_I2C_SDA
GPS_UART_TXD <21>
GPS_UART_RXD <21>
GPS_UART_RTS# <21>
GPS_UART_CTS# <21>

R48
100K_0201_5%

C40

DAP4_DIN
DAP4_DOUT
DAP4_FS
DAP4_SCLK

PU
PU
PU
PU

C39

GPIO_PU0
GPIO_PU1
GPIO_PU2
GPIO_PU3
GPIO_PU4
GPIO_PU5
GPIO_PU6

Z
Z

AN35
AG29
AG31
AJ31

4.7U_0402_6.3V6M

UART3_TXD
UART3_RXD
UART3_RTS*
UART3_CTS*

AH30
AE29

C42

UART2_TXD
UART2_RXD
UART2_RTS*
UART2_CTS*

0.1U_0201_10V6K

GEN1_I2C_SCL
GEN1_I2C_SDA

C41

VDDIO_UART

2
10P_0201_50V8J

HW.

For PMU RTCCLK , Load BOM

0.1U_0201_10V6K

C38

0.1U_0201_10V6K

AC37
1

2.2K_0201_1%

32.768KHZ_12.5P_1TJF125DP1A000D

2.2K_0201_1%

Open Drain

(1.8/3.3V)

U1R
14/21 UART

100K_0201_5%

T30S_XTAL_IN

<32>

100K_0201_5%

PMU_OSC32KOUT

R47

R46

C36

+VDD_1V8_SYS_TEGRA

Y1
1

<32> PMU_OSC32KIN

R75

R56

+VDD_1V8_UART_TEGRA

BT_RST#

8/25 Modify C36&C37 from 12P to 8P.

10/11 Modify C36&C37 from 8P to 10P.

+VDD_1V8_SENSOR

AT34
AR33

U1S

PD
PD
PD
PD

CAM_LED_EN_NV <35>
WF_RST# <22>
BT_WAKEUP <22>
EN_SENSOR_3V3_2
<23>

(1.8V)
Y32

(3.3V)

U1U

PWR_INT*

VDDIO_SYS

WAKE_UP_VBUS

AP36

Deep Sleep : ON

SYS_CLK_REQ
CLK_32K_IN
CLK_32K_OUT
KB_COL00
KB_COL01
KB_COL02
KB_COL03
KB_COL04
KB_COL05
KB_COL06
KB_COL07

T30S-R-A3-1.4G_FCCSP681

20/21 SPARE

9/27
ADD EN_SENSOR_3V3_2 to U1.AA3

Y8 Z ON_KEY#
AA5 Z

SPARE_1
SPARE_2
SPARE_3
SPARE_4
SPARE_5

<27>

AC27
AD28
AG19
AL33
AM34

JDBUG1

D20
RB751V-40_SOD323-2
2
1

ON_KEY#

ONKEY#

<20,32>

JTAG_TRST#
JTAG_TDI
JTAG_TMS
JTAG_TCK
JTAG_RTCK
JTAG_TDO

T30S-R-A3-1.4G_FCCSP681
<20>

HOT_RST#

ONKEY#

THERM_DN
THERM_DP

VDD_1V8_PMU_VRTC
+VDD_1V8_SYS_TEGRA
+3VS

<10,14,15,26,32,34>
<10,14,15,26,32,34>

PWR_I2C_SCL
PWR_I2C_SDA

8
7

JTAG_TCK

GND

4
6

HDMI_CEC

2
10K_0201_5%
2
10K_0201_5%
R160
1
2
10K_0201_5%
R161 2
1 100K_0201_5%

TEST_MODE_EN

100K_0201_5%

U37 PU
U29 PU
AD32 PU
AD36 PU
AC31 PU
Y30 PU
AD30 PU
W35 PU

R162 2

+VDD_1V8_SYS_TEGRA

9/22 Swap AD36 & W29 GPIO function.

Default pull up& pull down swap

AA31
AC35
Y28
AA33
W33
AD34

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST#
JTAG_RTCK

E31
C31

NV_THERM_DN
NV_THERM_DP

@ PAD T4
@ PAD T5
@ PAD T6
@ PAD T7
@ PAD T8
@ PAD T9

V32 Z

HDMI_CEC

<19>

V28 TEST_MODE_EN

9/26 Change from J37 to R37.

4

PICASSO_M

PICASSO_2

PCB_ID3

AP_OVERHEAT# <32>
TEMP_ALERT# <4>

9/28 Change Net name from Board_ID3 to PCB_ID3

Thermal

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

T30S(4/5) UART/OSC/PLL
Size
C
Date:

R29

1 100K_0201_5%

NCT1008CMT3R2G_WDFN8_2X2

PMU_CLK_32K <32>
CLK_32K_OUT <22>
SC_LOCK# <20>
VOL_UP# <4,20>
VOL_DOWN# <4,20>
EN_CAM_2V8 <17>
BOARD_ID_WP <10>

AC33 PD
WAKEUP_LED <27>
PD
PCB_ID3
R37
W29 PD
EN_CAM_1V8# <23>
PD
R31
we
not
use
Audio
LDO
PD
U35
PD
V34
UART_SW <20>
PD
U33
9/22 Change EN_3V3_MODEM to AF36
AE35 PD
@ PAD T10
AA35 PD
SHORT_DET <15>
PD
AA37
08/12 Delete EN_ACER_USB_CHARGE
AA29 PD
WF_WAKE# <22>
PD
Y36
@ PAD T14 9/26 Change BT_PD# to AJ33
PD
P30
SD_DET# <20>
AC29 PD
G_ACC_INT <16>
PD
P32
LINE_OUT_DET# <20>
AB30 PD
BT_IRQ# <22>

T30S-R-A3-1.4G_FCCSP681
JTAG_TRST#

VDD
THERM#
ALERT#

SCL
SDA

R159

JTAG_RTCK

100K_0201_5%

1
THERMD_F_N
PWR_I2C_SCL
PWR_I2C_SDA

D+
D-

R155

JTAG_TMS
R60

U4
2
3

C46
1000P_0201_16V7K
100_0201_1%
1

R61
2

R58
THERMD_F_P

100_0201_1%
1

JTAG_TDI

OWR

@ PAD T2

R62

NV_THERM_DN

R59
2

+3VS_TH

SYS_CLK_REQ

0_0201_5%

NV_THERM_DP

JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
JTAG_TRST*
JTAG_RTCK

W27 Z
T30
AB32 0

C45

max current is 350uA

VR1 =17mV

0.1U_0201_10V6K

49.9_0402_1%

1
2
3
4
5
6
7
8
9
10
GND
GND
ACES_87036-1001-CP
CONN@

R57
1

+3VS

1
2
3
4
5
6
7
8
9
10
11
12

<32>

CORE_PWR_REQ
<27,32>
CPU_PWR_REQ <32>

PICASSO_2@
R163

+VDD_1V8_SYS_TEGRA

R164
100K_0201_5%

PMU_INT#

T32
Y34

10K_0201_5%

KB_ROW00
KB_ROW01
KB_ROW02
KB_ROW03
KB_ROW04
KB_ROW05
KB_ROW06
KB_ROW07
KB_ROW08
KB_ROW09
KB_ROW10
KB_ROW11
KB_ROW12
KB_ROW13
KB_ROW14
KB_ROW15

+VDD_1V8_BB_TEGRA

T30S-R-A3-1.4G_FCCSP681

P28

<10,14,15,26,32,34>
<10,14,15,26,32,34>

<32>

+VDD_1V8_SYS_TEGRA

VDDIO_PEX_CTL
PEX_TERMP

PMU_RESET_OUT_1V8#

AK28

AUDIO_UART4_TX <14>
AUDIO_UART4_RX <14>
EN_VDD_GPS <21>
EN_SENSOR_1V8# <23>

PWR_I2C_SCL
PWR_I2C_SDA

U31

PICASSO_M@
R195

GPIO_PV0
GPIO_PV1

CORE_PWR_REQ
CPU_PWR_REQ

AC1
W3 Z
AC9 Z
V10 Z

AA1
W5
Y4
AA3

PEX_WAKE*

AP32

SYS_RESET*

10K_0201_5%

DAP3_DIN
DAP3_DOUT
DAP3_FS
DAP3_SCLK

<20>
<20>
<27>

Z
Z
Z

ULPI_CLK
ULPI_DIR
ULPI_NXT
ULPI_STP

WAKE_UP_ACIN
SIM_DET <18>

AR31
AT32
AU33

C43

0.1U_0201_10V6K

DEBUG_UART1_TX
DEBUG_UART1_RX

PEX_L2_CLKREQ*
PEX_L2_PRSNT*
PEX_L2_RST*

0.1U_0201_10V6K

ULPI_DATA0
ULPI_DATA1
ULPI_DATA2
ULPI_DATA3
ULPI_DATA4
ULPI_DATA5
ULPI_DATA6
ULPI_DATA7

PWR_I2C_SCL
PWR_I2C_SDA

(3.3V)
HVDD_PEX

C44

VDDIO_BB

(1.8/3.3V)

AA7 PU
AC7 PU
V8 PU
AC3 PU
V4 PU
AC11 PU
AF6 PU
AA9 PU

V36 Z
V30 Z

AL29

12/21 BB

R52
1K_0201_1%
2

0_0201_5%

V6

R51
1K_0201_1%

R53

EN_SENSOR_1V8#

PEX_CLK3N
PEX_CLK3P

(1.05V)

+VDD_1V8_BB_TEGRA

AVDD_PLLE

AF30

R77
100K_0201_5%

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
E

of

38

21/21 GND

(1.0 ~ 1.2V)

C103

0.1U_0201_10V6K

C102

0.1U_0201_10V6K

C101

0.1U_0201_10V6K

C107

0.1U_0201_10V6K

0.1U_0201_10V6K

C106

C105

Acer request 07/04

0.1U_0201_10V6K

0.1U_0201_10V6K

4.7U_0402_6.3V6M

1
C63

C62

C61
2

1
4.7U_0402_6.3V6M

1
4.7U_0402_6.3V6M

C64

VDD_1V2_SOC

0.1U_0201_10V6K

C88
2

0.1U_0201_10V6K

C58

C57

C56
2

C104

4.7U_0402_6.3V6M

C48

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

C52

4.7U_0402_6.3V6M

C51

4.7U_0402_6.3V6M

4.7U_0402_6.3V6M

C55

C50
1

4.7U_0402_6.3V6M

AB22
AB24
AB26
AD20
AD22
AD24
AD26
AF18
AF20
AF22
AF24
P14
P16
P18
P20
P22
T14
T16
T18
T22
T24
V12
V14
V16
V22
V24
V26
W25
Y12
Y14
Y16
Y22
Y24
Y26

C54

C49
1

1
4.7U_0402_6.3V6M

C60

4.7U_0402_6.3V6M

VDD_CORE_01
VDD_CORE_02
VDD_CORE_03
VDD_CORE_04
VDD_CORE_05
VDD_CORE_06
VDD_CORE_07
VDD_CORE_08
VDD_CORE_09
VDD_CORE_10
VDD_CORE_11
VDD_CORE_12
VDD_CORE_13
VDD_CORE_14
VDD_CORE_15
VDD_CORE_16
VDD_CORE_17
VDD_CORE_18
VDD_CORE_19
VDD_CORE_20
VDD_CORE_21
VDD_CORE_22
VDD_CORE_23
VDD_CORE_24
VDD_CORE_25
VDD_CORE_26
VDD_CORE_27
VDD_CORE_28
VDD_CORE_29
VDD_CORE_30
VDD_CORE_31
VDD_CORE_32
VDD_CORE_33
VDD_CORE_34

Acer request 07/04

4.7U_0402_6.3V6M

(1.0 ~ 1.2V)

AB12
AB14
AB16
AB18
AB20
AD12
AD14
AD16
AD18
AF14
AF16
T20
V18
V20
Y18
Y20

C53

VDD_CPU_01
VDD_CPU_02
VDD_CPU_03
VDD_CPU_04
VDD_CPU_05
VDD_CPU_06
VDD_CPU_07
VDD_CPU_08
VDD_CPU_09
VDD_CPU_10
VDD_CPU_11
VDD_CPU_12
VDD_CPU_13
VDD_CPU_14
VDD_CPU_15
VDD_CPU_16

C59

(0.9 ~ 1.0V)

VDD_1V0_GEN

4.7U_0402_6.3V6M

2
D

0.1U_0201_10V6K

C47

0.1U_0201_10V6K

AH26
AJ25

0.1U_0201_10V6K

VDD_RTC_1
VDD_RTC_2

+VDD_3V3_FUSE_TEGRA

C65

R64
B

10K_0201_5%

2
1

T30S-R-A3-1.4G_FCCSP681

VPP_KFUSE

R65
10K_0201_5%
2

AU17
AU9

0.1U_0201_10V6K

VPP_FUSE
VPP_KFUSE

(3.3V)
(3.3V)

U1B

+VDD_1V2_RTC_TEGRA

U1A
1/21 CORE POWER

12/12 Modify R65 from @ to mount.

AU7
B10
B16
B2
B22
B28
B36
C1
C3
C35
C37
D10
D16
D22
D28
D34
D4
E33
E5
F32
F6
G1
G13
G19
G25
G31
G37
G7
H30
H32
H6
H8
J11
J27
J29
J9
K10
K16
K2
K22
K28
K34
K36
K4
L11
L13
L17
L21
L25
L27
M12
M26
N1
N11
N13
N25
N27
N31
N37
N7
P24
R13
R15
R17
R19
R21
R23
T10
T2
T28
T34
T36
T4
U11
U13
U15
U17
U19
U21
U23
U25
U27
W1
W13
W15
W17
W19
W21
W23
W31
W37
W7

GND_100
GND_101
GND_102
GND_103
GND_104
GND_105
GND_106
GND_107
GND_108
GND_109
GND_110
GND_111
GND_112
GND_113
GND_114
GND_115
GND_116
GND_117
GND_118
GND_119
GND_120
GND_121
GND_122
GND_123
GND_124
GND_125
GND_126
GND_127
GND_128
GND_129
GND_130
GND_131
GND_132
GND_133
GND_134
GND_135
GND_136
GND_137
GND_138
GND_139
GND_140
GND_141
GND_142
GND_143
GND_144
GND_145
GND_146
GND_147
GND_148
GND_149
GND_150
GND_151
GND_152
GND_153
GND_154
GND_155
GND_156
GND_157
GND_158
GND_159
GND_160
GND_161
GND_162
GND_163
GND_164
GND_165
GND_166
GND_167
GND_168
GND_169
GND_170
GND_171
GND_172
GND_173
GND_174
GND_175
GND_176
GND_177
GND_178
GND_179
GND_180
GND_181
GND_182
GND_183
GND_184
GND_185
GND_186
GND_187
GND_188
GND_189
GND_190
GND_191

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8
GND_9
GND_10
GND_11
GND_12
GND_13
GND_14
GND_15
GND_16
GND_17
GND_18
GND_19
GND_20
GND_21
GND_22
GND_23
GND_24
GND_25
GND_26
GND_27
GND_28
GND_29
GND_30
GND_31
GND_32
GND_33
GND_34
GND_35
GND_36
GND_37
GND_38
GND_39
GND_40
GND_41
GND_42
GND_43
GND_44
GND_45
GND_46
GND_47
GND_48
GND_49
GND_50
GND_51
GND_52
GND_53
GND_54
GND_55
GND_56
GND_57
GND_58
GND_59
GND_60
GND_61
GND_62
GND_63
GND_64
GND_65
GND_66
GND_67
GND_68
GND_69
GND_70
GND_71
GND_72
GND_73
GND_74
GND_75
GND_76
GND_77
GND_78
GND_79
GND_80
GND_81
GND_82
GND_83
GND_84
GND_85
GND_86
GND_87
GND_88
GND_89
GND_90
GND_91
GND_92
GND_93
GND_94
GND_95
GND_96
GND_97
GND_98
GND_99

A13
A19
A25
A3
A31
A35
A7
AA11
AA13
AA15
AA17
AA19
AA21
AA23
AA25
AA27
AB10
AB2
AB28
AB34
AB36
AB4
AC13
AC15
AC17
AC19
AC21
AC23
AC25
AE1
AE11
AE13
AE15
AE17
AE19
AE21
AE23
AE25
AE27
AE31
AE37
AE7
AF12
AF26
AG11
AG13
AG17
AG21
AG25
AG27
AH10
AH16
AH2
AH22
AH28
AH34
AH36
AH4
AJ11
AJ27
AJ29
AJ9
AK30
AK32
AK6
AK8
AL1
AL13
AL19
AL25
AL31
AL37
AL7
AM32
AM6
AN33
AN5
AP10
AP16
AP22
AP28
AP34
AP4
AR1
AR3
AR35
AR37
AT10
AT16
AT2
AT22
AT28
AT36
AU13
AU19
AU25
AU3
AU31
AU35

T30S-R-A3-1.4G_FCCSP681

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

T30S(5/5)PWR_GND_NC
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

of

38

1
R66
100K_0201_5%

+VDD_1V2_DDR_MEM
+VRAM_VREDQ

DM1
VDDQ
VSS
NC

J5

1
2

NU
NU

J7

1
C76

1
C75

1
C74

1
C72
0.1U_0201_10V6K

4.7U_0402_6.3V6M

<5>

<5>
<5>

+VDD_1V8_DDR_MEM

T10
U1

0.1U_0201_10V6K
1

C78
2

1
C79

2
1U_0402_6.3V4Z

C80
0.1U_0201_10V6K

U10

CK

U2
U9

+VDD_1V8_DDR_MEM

VSS
C85 1

J6

1
C71

2
1U_0402_6.3V4Z

C84

DDR_A_D16
DDR_A_D21

C70
2

0.1U_0201_10V6K

DDR_A_D20

T8
T9

0.1U_0201_10V6K
1

4.7U_0402_6.3V6M

C77 1
NU
NU

NU
J3

<5> M_CLK_DDR0

R9
R10
T1
T2
T3
T5
T6
T7

<5>

C91

H5
H6
J1
J2

<5> DDR_A_DM1

C69 1
DDR_A_D22

0.1U_0201_10V6K

<5> M_CLK_DDR#0

VSS
NC
VSS
/CK

+VDD_1V2_DDR_MEM
+VDD_1V8_DDR_MEM

VDDQ
2
VDD2

0.1U_0201_10V6K
1
1
C86
2

1
C92

2
1U_0402_6.3V4Z

C87
0.1U_0201_10V6K

EDB8132B2MA-6D-F_FBGA134
X76_ELP_512M@

C100

G10
H1
H2
H3

DQS1
DQ10
DQ9
DQ8

Acer request

DDR_A_D23 <5>
DDR_A_D18 <5>
DDR_A_DQS2 <5>
DDR_A_DQS#2 <5>

0.1U_0201_10V6K

G6
G7
G8
G9

<5> DDR_A_DQS1
<5> DDR_A_D8
<5> DDR_A_D9
<5> DDR_A_D13

DQ18
DQ21

<5>

C83

VREFCA
/DQS1

C68
0.1U_0201_10V6K

DDR_A_MA0

0.1U_0201_10V6K

CA5

<5>
<5>

C90

VDD2

DDR_A_DM2
DDR_A_D1

0.1U_0201_10V6K

2
1
2

G3
G5

<5> DDR_A_DQS#1

R69
100K_0201_5%

G2

<5> DDR_A_MA5

VDDQ

N7
N8
N9
N10
P1
P2
P3
P5
P6
P7
P8
P9
P10
R1
R2
R3
R5
R6
R7
R8

C99

G1

+VRAM_VREFA

DDR_A_MA1 <5>
DDR_A_D19 <5>
DDR_A_D17 <5>

0.1U_0201_10V6K

R68
100K_0201_5%

VSS
VDDQ
NU
NC
NC
VDD2
VDD1
DQ16

<5>
<5>

4.7U_0402_6.3V6M

DQ12

DDR_A_D2
DDR_A_D0

C82

F10

<5>
<5>

0.1U_0201_10V6K

DQ14

DDR_A_D7
DDR_A_D3

C89

<5> DDR_A_D11

F9

M8
M9
M10
N1
N2
N3
N5
N6

<5>
<5>
<5>

0.1U_0201_10V6K

F8

DDR_A_MA4
DDR_A_MA3
DDR_A_MA2

C98

<5> DDR_A_D14

+VDD_1V2_DDR_MEM

DM2
DQ0
VDDQ
VSS
VSS
VDD2
CA0
VDDQ
DQ17
DQ20
DQS2
/DQS2
VSS
VDD1
VSS
NC
VSS
VSS
VDDQ
DQ22

DDR_A_DQS#0 <5>
DDR_A_DQS0 <5>
DDR_A_D5 <5>
DDR_A_D6 <5>
DDR_A_D4 <5>

0.1U_0201_10V6K

<5> DDR_A_D12
<5> DDR_A_D10

DQ28
DQ24
DM3
DQ15
VDDQ
VSS
NC
CA6
CA7
VSS
DQ11
DQ13

F1,H1,N2 are the NC pins which assembled/embedded

the interconnection into ELP Vdd sources already.
due to co-layout the LPDDR2,
it is need to apply 1.2 volt on F1, H1 and N2 pins.

C73

E5
E6
E7
E8
E9
E10
F1
F2
F3
F5
F6
F7

DDR_A_D26
DDR_A_D27
DDR_A_DM3
DDR_A_D15

R67
100K_0201_5%

4.7U_0402_6.3V6M

<5>
<5>
<5>
<5>

C81

<5> DDR_A_MA9
<5> DDR_A_MA8

VSS
CA9
CA8

M_CS#0 <5>
M_CS#1 <5>

0.1U_0201_10V6K

E1
E2
E3

DQ1
DQ3
VDDQ
VSS
NC
CA1
DQ19
DQ23

<5>

C178

<5> DDR_A_D24
<5> DDR_A_D28
<5> DDR_A_DQS3
<5> DDR_A_DQS#3

M_CKE0 <5>
M_CKE1 <5>
DDR_A_DM0

0.1U_0201_10V6K

1 R71
2
240_0402_1%

J8
J9
K1
K2
K3
K5
K6
L1
L2
L3
L5
L6
L7
L8
L9
L10
M1
M2
M3
M5
M6
M7

C97

<5> DDR_A_D30

VSS
VREFDQ
CKE0
CKE1
NC
DM0
VDDQ
/CS0
/CS1
NC
/DQS0
DQS0
DQ5
DQ6
DQ7
VSS
CA4
CA3
CA2
VSS
DQ4
DQ2

0.1U_0201_10V6K

1 R70
2
240_0402_1%

NU
NU
NU
NU
NU
NC
NC
VDD2
VDD1
DQ31
DQ29
DQ26
NU
VDD1
VSS
ZQ1
Vss
VSS
VDDQ
DQ25
VSS
VDDQ
VSS
VDD2
ZQ0
VDDQ
DQ30
DQ27
DQS3
/DQS3
VSS

0.01U_0201_16V7

<5> DDR_A_D29
<5> DDR_A_D25
<5> DDR_A_D31

A1
A2
A9
A10
B1
B2
B3
B5
B6
B7
B8
B9
B10
C1
C2
C3
C5
C6
C7
C8
C9
C10
D1
D2
D3
D5
D6
D7
D8
D9
D10

C66

U7

0.01U_0201_16V7

+VDD_1V8_DDR_MEM

+VDD_1V2_DDR_MEM

<5> DDR_A_MA6
<5> DDR_A_MA7

N7
E7
T8
N6
P7
N5
T7
T9
R8
P6
D6
B8
E5
E6
D7
B7
C8
B9
P8
P9
D8
D9

+VDD_1V2_DDR_MEM
+VDD_1V8_DDR_MEM

Layer 2
DM2
DM3
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQS2
DQS2#
DQS3
DQS3#

0.01U_0201_16V7

Follow NV design
NET NAME BALL NAME
A0
P3
A1
N3
A2
M3
A3
M2
A4
M1
A5
G2
A6
F2
A7
F3
A8
E3
A9
E2
CKE0
K1
CKE1
K2
CLK
J3
CLK#
H3
CS0
L1
CS1
L2
DM0
K5
DM1
H5
DQ0
M9
DQ1
N8
DQ10
F7
DQ11
F9
DQ12
F6
DQ13
G9
DQ14
F8
DQ15
E8
DQ2
M8
DQ3
M7
DQ4
L9
DQ5
L7
DQ6
L8
DQ7
M6
DQ8
G7
DQ9
G8
DQS0
L6
DQS0#
L5
DQS1
G6
DQS1#
G5

0.1U_0201_10V6K

U7

U7

X76_ELP_1GB@
A

( 1GB Elpida )

C94
2

1
C95

2
1U_0402_6.3V4Z

C96
0.1U_0201_10V6K

SA000050Z10

Issued Date

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Title

LPDDRII-DEVICE DOWN
Size
C
Date:

Compal Electronics, Inc.

Compal Secret Data

Security Classification

C252

0.1U_0201_10V6K
1

33P 50V J NPO 0201

C93 1

C260

+VDD_1V8_DDR_MEM

( 1GB Samsung )

33P 50V J NPO 0201

SA00004YY20

0.01U_0201_16V7

X76_SAM_1GB@

Document Number

Rev
1.0

Picasso 2 R04
Wednesday, January 18, 2012
1

Sheet

of

38

Remove EC
2
C115

U54
1
2
3
4

A0
A1
A2
GND

1
VCC
WP
SCL
SDA

8
7
6
5

BOARD_ID_WP
PWR_I2C_SCL
PWR_I2C_SDA

0.1U_0201_10V6K

+VDD_1V8_SYS_TEGRA

PN:SA00004KS00
2k bit

need check with WC of GPIO

<7>
<7,14,15,26,32,34>
<7,14,15,26,32,34>

AT24C02C-XHM-T_TSSOP8

need check with SW Roger

08/04 Change U54 and C115 to @
08/12 Change U54 to SA000056G00
08/12 Change U54 footprint to AT24C64A-10TQ-2P7_TSSOP8
08/12 Change U54 footprint to AT24C64A-10TQ-2P7_TSSOP9
08/20 Change U54 to SA00004KS00

11/30 Change U54 to SA00005GV00

12/16 Change U54 to SA00004KS00(2K).

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

EC(Reserved)
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

10

of

38

+VDDIO_1V8_EMMC
+VDD_2V85_EMMC
EMMC_CLK_R
@ C148

C117

C118

K6
W4
Y4
AA3
AA5

11/23 Reserver C148,C149 and C150 for Acer HW request.

11/23 Modify C117 from 2.2U 0402 to 10U 0402.
12/7 Modify C148,C149,C150 from @ to mount
12/16 Modify C148 and c150 from mount to @ for LDO solution.
+VDDIO_1V8_EMMC
EMMC_CMD_R

W6

EMMC_CLK_R

R103 1

2 0_0201_5%

H3
H4
H5
J2
J3
J4
J5
J6

EMMC_DAT0_R
EMMC_DAT1_R
EMMC_DAT2_R
EMMC_DAT3_R
EMMC_DAT4_R
EMMC_DAT5_R
EMMC_DAT6_R
EMMC_DAT7_R

R104
R105
R106
R107
R108
R109
R110
R111

2
2
2
2
2
2
2
2

K2

C123 1

U1
U2
U3
U5
U6
U7
U10
U12
U13
U14
V1
V2
V3
V12
V13
V14
W1
W2
W3
W7
W8
W9
W10
W11
W12
W13
W14
Y1
Y3
Y6
Y7
Y8
Y9
Y10
Y11
Y12
Y13
Y14
AA1
AA2
AA7
AA8
AA9
AA10
AA11
AA12
AA13
AA14
AE1
AE14
AG2
AG13
AH4
AH6
AH9
AH11

0.1U_0201_10V6K

1
R102

2
33_0201_1%

EMMC_CMD

<4>

DAT0
DAT1
DAT2
DAT3
DAT4
DAT5
DAT6
DAT7
VDDi
NC
NC
NC
RSTN
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

1
1
1
1
1
1
1
1

33_0201_1%
33_0201_1%
33_0201_1%
33_0201_1%
33_0201_1%
33_0201_1%
33_0201_1%
33_0201_1%

EMMC_DA0
EMMC_DA1
EMMC_DA2
EMMC_DA3
EMMC_DA4
EMMC_DA5
EMMC_DA6
EMMC_DA7

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

R114

EMMC_CLK <4>

4.7K_0201_5%

R113
CLK

W5

CMD

4.7K_0201_5%

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

VCCQ
VCCQ
VCCQ
VCCQ
VCCQ

M6
N5
T10
U9
VCC
VCC
VCC
VCC

U13

C121
0.1U_0201_10V6K

0.1U_0201_10V6K

C120
0.1U_0201_10V6K

10U_0402_6.3V6M

10U_0402_6.3V6M

+VDD_2V85_EMMC

A4
A6
A9
A11
B2
B13
D1
D14
H1
H2
H6
H7
H8
H9
H10
H11
H12
H13
H14
J1
J7
J8
J9
J10
J11
J12
J13
J14
K1
K3
K5
K7
K8
K9
K10
K11
K12
K13
K14
L1
L2
L3
L4
L12
L13
L14
M1
M2
M3
M5
M8
M9
M10
M12
M13
M14
N1
N2
N3
N10
N12
N13
N14
P1
P2
P3
P10
P12
P13
P14
R1
R2
R3
R5
R12
R13
R14
T1
T2
T3
T5
T12
T13
T14

+VDDIO_1V8_EMMC

close U13

10U_0402_6.3V6M

2.2U_0402_6.3VM

12P_0201_50V8J

C119
2

@ C150

C122
22U_0603_6.3V6M

C149

EMMC_CMD_R
MMC_RST#
C

U13

KING16GB@

SA00004O610
MMC_RST#

R112 1

2 0_0201_5%

EMMC_RST# <4>
U13

SAND16GB@

SA00004XA00
U13

SAM16GB@

SA00004FN20

U13

KING32GB@
B

SA00004TD00
U13

SAM32GB@

SA00004FO40
U13

SAND32GB@

SA000052910

U13

SAND432GB@

SA000042X20
U13

AA6
AA4
Y5
Y2
K4

SAND64GB@

SAND64GB@

1
2
3
4
5
6
7
8
9
10
11
12

SA00004XQ10

8/26 ADD for SKU control.

A

VSS
VSS
VSS
VSS

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ

NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC

U8
R10
P5
M7

13
14
15
16
17
18
19
20
21
22
23
24

SDIN5F1-64G_TFBGA169

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

eMMC
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Wednesday, January 18, 2012
1

Sheet

11

of

38

10/03 Modify C125,C126,C128,C129,C132,C139,C140,C141 and C142 from +VDD_LVDS to LB_VCC power domain.
08/09 Add C139-C140 for +VDD_LVDS
LB_VCC

C131

C134

C124

C125

C126

C128

C129

C132

C139

C140

C141

C142

C127

C130

C133

10U_0402_6.3V6M

0.1U_0201_10V6K

0.01U_0201_16V7

1
2

33P_0201_50V8J

1
2

33P_0201_50V8J

1
2

33P_0201_50V8J

33P_0201_50V8J

10U_0402_6.3V6M

0.1U_0201_10V6K

0.01U_0201_16V7

0.1U_0201_10V6K

0.01U_0201_16V7

0.01U_0201_16V7

10U_0402_6.3V6M

0.1U_0201_10V6K

PLLVCC
1

+VDD_LVDS

10/19 Modify U20 PN from SA000050500 to SA000059A00

09/21 swap LCD_D00~LCD_D23 for colay.

+VDD_LVDS

PICASSO_M@
LVDS_MAP

R139
10K_0201_5%

<4> LCD_PCLK

B7
LVDS_MAP
LVDS_CTRL0
LVDS_CTRL1
LVDS_CTRL2
LVDS_RF

B10

LVDS_RS

A12
B14

TXA1+
TXA1TXB1+
TXB1TXC1+
TXC1-

LVDS CH1

TXD1+
TXD1TXE1+
TXE1TXA2+
TXA2TXB2+
TXB2TXC2+
TXC2-

LVDS CH2

TXD2+
TXD2-

CH 2 Input

TXE2+
TXE2TCLK1+
TCLK1TCLK2+
TCLK2-

TEST

NC_1
NC_2
NC_3
NC_4
NC_5
NC_6
NC_7
NC_8
NC_9
NC_10
NC_11
NC_12

Input control

R/F

1 R189
2
0_0402_5%
R125 1

B33
A39

LVDS_A0
LVDS_A0#

B32
A38

LVDS_A1
LVDS_A1#

2 0_0201_5%

LVDS_ACLK2_R

B30
A36

LVDS_A2
LVDS_A2#

A32
B28

LVDS_A3
LVDS_A3#

LVDS_A4

SM070002I00

R127 1

2
R73

LVDS_ACLK2#_R

2 0_0201_5%

LVDS_A4_R

@
4

1
100_0201_1%

A29
B25

LVDS_A4
LVDS_A4#

A28
B24

LVDS_A5
LVDS_A5#

B22
A26

LVDS_A6
LVDS_A6#

B19
A23

LVDS_A7
LVDS_A7#

1
LVDS_A4#

LVDS_A5

<13>

<13>

LVDS_ACLK1#
LVDS_A0

R131 1

A34
A35

LVDS_ACLK1
LVDS_ACLK1#

B21
A25

LVDS_ACLK2
LVDS_ACLK2#

LVDS_A6

A17

B5
A6
B6
A9
B11
B13
A16
B15
A18
A60
A61
A80

SM070002I00

LVDS_A4#_R

2 0_0201_5%

LVDS_A0_R

LVDS_A5_R

<13>

<13>

LVDS_A0#

LVDS_A1

2
LVDS_A6#

LVDS_A7

SM070002I00

LVDS_A6_R

2 0_0201_5%

<13>

<13>

SM070002I00

LVDS_A1_R

2 0_0201_5%

<13>

<13>
<13>

LVDS_A1#
LVDS_A2

<13>

SM070002I00

S COM FI_ ICT ICMF112P900MFR

R134 1
2 0_0201_5%
@

LVDS_A1#_R

R136 1

LVDS_A2_R

2 0_0201_5%
@

<13>
<13>

L12

SM070002I00

S COM FI_ ICT ICMF112P900MFR

R137 1
2 0_0201_5%
@

LVDS_A6#_R

R249 1

LVDS_A7_R

2 0_0201_5%
@

LVDS_A0#_R

<13>

<13>

LVDS_A2#

LVDS_A3

SM070002I00

S COM FI_ ICT ICMF112P900MFR

R138 1
2 0_0201_5%
@

LVDS_A2#_R

R247 1

LVDS_A3_R

2 0_0201_5%
@

L45

LVDS_A7#

R132 1
4

LVDS_A5#_R

R135 1

2 0_0201_5%

S COM FI_ ICT ICMF112P900MFR

R130 1
2 0_0201_5%
@

L11
1

SM070002I00

L9

LVDS_ACLK1#_R

S COM FI_ ICT ICMF112P900MFR

R133 1
2 0_0201_5%
@

4
1

1
100_0201_1%

R74

R128 1

L10

B18
A22

<13>

L7

S COM FI_ ICT ICMF112P900MFR

R129 1
2 0_0201_5%
@

LVDS_ACLK1_R

S COM FI_ ICT ICMF112P900MFR

R124 1
2 0_0201_5%
@

L8
A31
B27

2 0_0201_5%
@

L6

<13>

<13>

L46

SM070002I00
2

S COM FI_ ICT ICMF112P900MFR

R252 1
2 0_0201_5%
@

LVDS_A7#_R

<13>

SM070002I00
2

S COM FI_ ICT ICMF112P900MFR

R250 1
2 0_0201_5%
@

LVDS_A3#

LVDS_A3#_R

<13>

11/11 Add C328,C338,C360 and C364 for Acer RF request.

08/05 Change L5-L12,L45,L46 to mount

1RLP105ANQG8_QFN148_11X11

08/12 Change L5-L12,L45,L46 to SM070002N00

10/17 Chanfe Bead P/N from SM070002N00 to SM070002I00

Close LVDS Transmitter (U20)

08/12 Add R148 PD LVDS_SHTDN# to GND

LVDS_CTRL0

LVDS_CTRL1

R147
PICASSO_M@
10K_0201_5%

+VDD_LVDS
R141
PICASSO_2@
10K_0201_5%

RS Input Voltage

+VDD_LVDS

R143
10K_0201_5%
1

R126 1

LVDS_CTRL2

LVDS_ACLK1

+VDD_LVDS

R140
10K_0201_5%

R144
@
10K_0201_5%

<13>

S COM FI_ ICT ICMF112P900MFR

LVDS_ACLK2# R123 1
2 0_0201_5%
@

LVDS_A5#

MAP
CTRL0
CTRL1
CTRL2

PD#

09/26
Change R122 & R156 package from 0201 to 0402

+VDD_LVDS

R148
10K_0201_5%

+3VS

CLKIN

RS

+LCDVDD

1 0_0402_5%

L5

B2
A8
A46
A52
A58
B54
A70
B65

<4> LVDS_SHTDN#

need check for single in single out

+VDD_LVDS

A13
A14
B12
A15

VSYNC
HSYNC
DE

1 0_0402_5%

C364

B4
A4
A5

09/21 Isolated LB_VCC and PLLVCC.

PLLVCC

10P_0201_50V8J
C360

<4> LCD_VSYNC
<4> LCD_HSYNC
<4>
LCD_DE

A19
B35

10P_0201_50V8J
C338

LVDS_MAP configuration:
High: Picasso M
Low: Picasso 2

R122 2

A24
B23
B26
B29
A37

10P_0201_50V8J
C328

09/21 Add R165 select pin for Picasso M.

TA20
TA21
TA22
TA23
TA24
TA25
TA26
TA27
TA28
TA29
TB20
TB21
TB22
TB23
TB24
TB25
TB26
TB27
TB28
TB29
TC20
TC21
TC22
TC23
TC24
TC25
TC26
TC27
TC28
TC29
RES21
RES22

1 R192
2
0_0402_5%

R156 2

10P_0201_50V8J

R193
10K_0201_5%
PICASSO_2@

A64
B55
A65
B56
A66
A67
B57
A68
B58
A69
B60
A71
B61
A72
B62
A73
B63
A74
A75
B64
A77
B66
A78
B67
A79
B68
A1
B1
A3
B3
B9
A11

LB_VCC

LVDS_ACLK2

GND_PAD

B0
B1
B2
B3
B4
B5
B6
B7

PVCC_1
PVCC_2

A2
A7
B39
B44
B49
A63
B59
A76

Z1

LCD_D18
LCD_D19
LCD_D00
LCD_D01
LCD_D02
LCD_D03
LCD_D04
LCD_D05

CH 1 Input

LGND_1
LGND_2
LGND_3
LGND_4
LGND_5
LGND_6
LGND_7
LGND_8

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

G0
G1
G2
G3
G4
G5
G6
G7

LVCC_1
LVCC_2
LVCC_3
LVCC_4
LVCC_5

A21
B20
A27
A30
A33
B31
B34
A40

LCD_D20
LCD_D21
LCD_D06
LCD_D07
LCD_D08
LCD_D09
LCD_D10
LCD_D11

VCC_1
VCC_2
VCC_3
VCC_4
VCC_5
VCC_6
VCC_7
VCC_8

(3.3V)

PGND_1
PGND_2
PGND_3
PGND_4
PGND_5

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

TA10
TA11
TA12
TA13
TA14
TA15
TA16
TA17
TA18
TA19
TB10
TB11
TB12
TB13
TB14
TB15
TB16
TB17
TB18
TB19
TC10
TC11
TC12
TC13
TC14
TC15
TC16
TC17
TC18
TC19
RES11
RES12

A42
A41
A20
B17
B16

LCD_D22
LCD_D23
LCD_D12
LCD_D13
LCD_D14
LCD_D15
LCD_D16
LCD_D17

GND_1
GND_2
GND_3
GND_4
GND_5
GND_6
GND_7
GND_8

<4>
<4>
<4>
<4>
<4>
<4>
<4>
<4>

U20
B36
A43
B37
A44
B38
A45
B40
A47
A48
B41
A49
B42
A50
B43
A51
B45
A53
B46
A54
A55
B47
A56
B48
A57
B50
A59
B51
B52
A62
B53
B8
A10

R0
R1
R2
R3
R4
R5
R6
R7

R146
200K _0201_1%

CMOS/TTL Input Configuration ( Input Voltage Swing

VCC

350 mV

Standard Input and Output Configuration

0.6 ~ 1.4 V

350 mV

Small Input Swing, Standard Output Swing Configuration

GND

200 mV

Standard Input Swing, Reduced Output Swing Configuration

R188
10K_0201_5%

LVDS
Output Swing

Single-In, Dual-Out (DDR Off)

LVDS_RF

LVDS_RS

C135

CTRL[2:0] = LHH

Single-In, Single-Out (Distribution Off)

CTRL[2:0] = HHH

Single-In, Single-Out (Distribution On)

R142

100K_0201_5%
2

Single-In, Dual-Out (DDR On)

1

CTRL[2:0] = HHL

R145 @
0_0201_5%

0.1U_0201_10V6K

CTRL[2:0] = LHL

10/14 Modify LVDS_RS from pull up to pull down to reduce power consumption.
11/1 Modify LVDS_RS from pull down to pull up to meet SPEC
Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

LVDS Transmitter
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

12

of

38

08/01 Change L13 to SM010031680

08/01 Change L13 footprint to
KC_FBMA-L11-160808-121LMT_2P

2 0_0201_5%

EN
OCB

2
C180
3

+LCDVDD
1

APL3511CBI-TRG_SOT23-5
R150

C181

C188

C182

3300P_0201_16V6K

GND
R279 1

<4> EN_VDDLCD_T30S

39P_0201_50V8J

VIN

+LCDVDD

L13
+LCDVDD_L
1
2
FBMA-L11-160808-301LMA20T_0603~D

0.1U_0201_10V6K

VOUT
5

+3VS

4.7U_0402_6.3V6M

U21

100K_0201_5%
1

C185
1U_0402_6.3V4Z

2
D

C179
0.1U_0201_10V6K

11/06 Add for COMPAL EMI request.

LCD POWER CIRCUIT

JLVDS1

38
39
40

DCR_EN (CABC_EN) Dynamic backlight control

PWM_IN System PWM signal input for dimming
PWM_OUT Panel PWM signal output to system

43
44
45
46
47

LED_CA5
LED_CA4
LED_CA3
LED_CA2
LED_CA1

49
50

VLED Output
VLED Output

LED
LED
LED
LED
LED

Cathode
Cathode
Cathode
Cathode
Cathode

5
4
3
2
1

LED Backlight power

LED Backlight power

51
52
53
54
B

GND
GND
GND
GND

Remove LVDS I2C

10/19 Add for Discharge +5VS

LVDS_A0#_R <12>
LVDS_A0_R <12>

B+

+5VS

+3.3V
+3.3V
+3.3V

+LCDVDD

LVDS_A1#_R <12>
LVDS_A1_R <12>

LVDS_A2#_R <12>
LVDS_A2_R <12>

R95
100K_0201_5%

LVDS_ACLK1#_R <12>
LVDS_ACLK1_R <12>

Q48
5

LVDS_A3#_R <12>
LVDS_A3_R <12>

LVDS_A5#_R <12>
LVDS_A5_R <12>
LVDS_A6#_R <12>
LVDS_A6_R <12>

<28,32> EN_5V0_BUCKBOOST

LVDS_A4#_R <12>
LVDS_A4_R <12>

G1
G2

R96
1K_0201_1%

S1
D1
D2
S2

VDD Power Supply

VDD Power Supply
VDDEDID EDID

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

2
3
4

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50

Panel SPEC

4
3
6
1

DMN2004DWK-7_SOT363-6

8/25 Acer request

Add R86,R83&R82 to panel back light.

LVDS_ACLK2#_R <12>
LVDS_ACLK2_R <12>
LVDS_A7#_R <12>
LVDS_A7_R <12>
R83
R82

2
2

@
@

1 0_0201_5%
1 0_0201_5%

LCD_DCR

<4>

LCD_PWM_OUT <4>
INVTPWM <31>
DISPOFF# <4,31>
FB5
<31>
FB4
<31>
FB3
<31>
FB2
<31>
FB1
<31>

LCD_PWM_OUT

R86

INVTPWM

1 0_0201_5%

40 . to LED power IC
41 . For Picasso 1 Pannel backlight

+5VS

L14
1
2
MPZ1005S300CT_2P

+VDD_LED_BL

STARC_300E50-0010RA-G3
CONN@

1
C169

Remove C188 ,

07/28 Change JLVDS1 footprint

C184

due to PC57,PC55 is close to pin 48

LTCX003KB00

4.7U_0402_6.3V6M

C168
2

C183
2

0.1U_0201_10V6K

0.1U_0201_10V6K

4.7U_0402_6.3V6M

JTP1
1
2
3
4
5
6
7
8
9
10

<4> GEN2_I2C_SCL
<4> GEN2_I2C_SDA
<4>
TS_INT#
<4>

TS_RST#

<4> TS_PWR_EN

10/02 Modify R166 BOM

+3VS

D12 @
TVNST52302AB0_SOT523-3

GND1
GND2

ACES_50506-01041-001
CONN@

LTCX003HG00

D13 @
TVNST52302AB0_SOT523-3

TS_RST#

SCA00001W00

100K_0201_5%
@

11
12

GEN2_I2C_SCL
GEN2_I2C_SDA
3

R166

TS_INT#
TS_RST#
3

T15 PAD @
T16 PAD @

Structure from Mount to Unmount

1
2
3
4
5
6
7
8
9
10

SCA00001W00

Touch Panel

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

LCD Panel/Touch Panel

Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

13

of

38

+VDD_1V8_AUDIO

R168
2
0_0201_5%

VDD_IO_305
1

C193
1U_0402_6.3V4Z

C194
0.1U_0201_10V6K

+VDD_1V8_AUDIO

VDD_DAL_305

1U_0402_6.3V4Z

C197

C196

0.1U_0201_10V6K
R167 @
10K_0201_5%
2

R169
<6>

AUDIO_SEL

C198
1U_0402_6.3V4Z

U23
AUDIO_SEL_R

2
0_0201_5%

AUDIO_DOUT2
AUDIO_DIN2

VDD_P_305
C199

1
2
3
4
5

R170
470K_0402_5%

0.1U_0201_10V6K

+VDD_1V8_AUDIO
COM1
NC1
V+
NC2
COM2

CODEC_IN

10
9
8
7
6

CODEC_OUT

TS5A23157RSER_QFN10_2X1P5

C195
0.1U_0201_10V6K

SA000039100

+VDD_1V8_AUDIO

IN1
NO1
GND
NO2
IN2

AUDIO_DOUT2_R

AUDIO_DIN2_R

R180
@
10K_0201_5%

R177
2
0_0201_5%

UART_SOUT
+VDD_1V8_AUDIO

Support for input clock frequencies of 24 MHz and 26 MHz

requires a 10k pull-up resistor on the UART_SOUT pin.

<15> AUDIO_FS2_VOICE

1
2

<6> EN_ES305_OSC

2 0_0201_5%

Output

H
OPEN
L

OSC out
OSC out
High Z

GND

<6>

AUDIO_SCLK2

<6>

2
0_0201_5%

AUDIO_FS2

<6>

AUDIO_FS2_VOICE connect to portA and CODEC,

VDD
OUTPUT

AUDIO_FS2 connect to portB, portC and

4
3

ES305_CLK_12M

CPU.

AUDIO_SCLK2_VOICE connect to portA and CODEC

12MHZ_15PF_FK1200007

AUDIO_SCLK2 connect to portB, portC and

CPU.

SJ000004400

Vcount

R183
470K_0402_5%

OE

AUDIO_DIN2

2
0_0201_5%

20110823 Modify for Acer request

X5
R182 1

R205
470K_0402_5%
1

R187
0_0201_5%

@ R184
10K_0201_5%

<6>

R174
2

ES305_INT
C380
0.01U_0201_16V7

2
0_0201_5%
R171

<15> AUDIO_SCLK2_VOICE
1

AUDIO_DOUT2

R178

07/27 Change X5 footprint

Active --> 17 mA
Sleep --> 35 uA

20110823 Modify for Acer request

U24
VDD_IO_305

D6

VDD_DAL_305

C6
B6

<7> CLK_12M_ES305

SW

ES305_CLK_12M
<7> AUDIO_UART4_TX

<7> AUDIO_UART4_RX
<6> ES305_INT_R

DAP2_DIN

C_DO

CODEC_OUT

A_DI

ADC

<6> AUDIO_RST#

VDD_P_305

A6

AUDIO_DOUT2
AUDIO_SCLK2

DAP2_SCLK

C_DI

A_DO

C_CLK

A_CLK

CODEC_IN
AUDIO_SCLK2_VOICE

R186 1

2 0_0201_5%

ES305_CLK_IN

A4

R172 1

2 0_0201_5%

UART_SIN

A3

R175 1

2 0_0201_5%

UART_SOUT

B4

R176 1

2 0_0201_5%

ES305_INT

B3

R179 1

2 0_0201_5%

ES305_I2C_SDA

B5

ES305_I2C_SCL

C5

AUDIO_RST#_R

D5

T30S

A_FS

ES305
B_DO

D_DO

B_DI

D_DI

B_CLK

D_CLK

CLK

A5

E6
F6

WM8903

PORTA_FS

CODEC_IN
AUDIO_SCLK2_VOICE

B1

AUDIO_FS2_VOICE

CLK_IN

PORTB_DI

12M ~ 16M

UART_SIN

PORTB_DO

F3

AUDIO_DOUT2_R

UART_SOUT

PORTB_CLK

GPIO_A

PORTB_FS

F4 R173

<15>
<15>

1 100K_0201_5%

E4

AUDIO_SCLK2

E3

AUDIO_FS2

I2C_DATA
I2C_CLK
RESET_

PORTC_DI
PORTC_DO

low active

TEST

PORTC_CLK

GND_P

PORTD_DI

GND

PORTD_DO

GND

PORTD_CLK

GND

PORTD_FS

F2

AUDIO_DOUT2_R

E2

AUDIO_DIN2_R

E1

AUDIO_SCLK2

F1

AUDIO_FS2

D1
C1
C2
D2
R181
100K_0201_5%

ES305_BGA32

<7,10,15,26,32,34>

PWR_I2C_SDA

<7,10,15,26,32,34>

PWR_I2C_SCL

R226 1

2 0_0201_5%

ES305_I2C_SDA

R246 1

2 0_0201_5%

ES305_I2C_SCL
A

D_FS

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Audio Block Diagram

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

ES305
Size
C
Date:

CODEC_OUT

B2
A1

10/11 Change P/N from SA00004Y400 to SA00004Y410

B_FS

VDD_P

PORTC_FS

LRC
AUDIO_FS2_VOICE

PORTA_CLK

A2

C_FS
AUDIO_FS2

VDD_DPD

DAC

E5

DAP2_FS

PORTA_DO

2 0_0201_5%

F5

DAP2_DOUT

PORTA_DI

VDD_DAL

AUDIO_DIN2

R185 1

VDD_IO

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

14

of

38

C214
1U_0402_6.3V4Z

+AVDD_CDC

C212
1U_0402_6.3V4Z

C216
1U_0402_6.3V4Z
C217

Close U113.40

Close U113.39

Close U113.10

PWR_I2C_SDA

<7,10,14,26,32,34>

PWR_I2C_SCL

2 0_0201_5%

CODEC_I2C_SDA

R322 1

2 0_0201_5%

CODEC_I2C_SCL

+VDD_1V8_AUDIO
U25
L41
1
2
FBMA-10-100505-121T_0402

L17
1
2
FBMA-10-100505-121T_0402

39
40
10
24

+CPVDD
+AVDD_CDC
CODEC_I2C_SCL
CODEC_I2C_SDA

EN_SPEK
1
2

<7> SHORT_DET

10/13 Modify R392 from 0 ohm to 1K for noise issue.

R392 1

<20> COM_MIC

CDC_COM_MIC

C209
100P_0201_25V8J

2 1U_0402_10V6K
2 1U_0402_10V6K

32
35

AMIC_RIGHT+
AMIC_LEFT+

C224 1
C225 1

2 1U_0402_10V6K
2 1U_0402_10V6K

31
34

AMIC_RIGHTAMIC_LEFT-

C269 1
C258 1

2 1U_0402_10V6K
2 1U_0402_10V6K

30
33

19
21
20

LINEOUTR
LINEOUTL
LINEGND

IN2R
IN2L

2
2

<20>

1
1
S SUPPRE_ KC FBMA-11-100505-601T 0402
S SUPPRE_ KC FBMA-11-100505-601T 0402
C222 1

LINE_DOCK_R
LINE_DOCK_L

2 0.1U_0402_10V7K 1

<20>
<20>

20_0402_5%
R204
2 2.2U_0402_6.3VM

+MIC_BIAS

C226

+VMID_CDC

C227

+VMID_CDC
+VPOS_CDC
+VNEG_CDC

12
26
41
1

CPGND
AGND
GNDPAD
DGND

IN3R
IN3L

2 0.1U_0402_10V7K 1

20_0402_5%
L43
L42

+MIC_BIAS

25
14
15

VMID
VPOS
VNEG

R199

<20>

LINEGND

C223 1

29

MICBIAS

IN1R
IN1L

CFB1
CFB2

11
13

CFB1
CFB2

GPIO3/ADDR
DMIC_DAT/GPIO2
DMIC_LR/GPIO1

R452 10_0201_5% 2
CDC_LEFT_P
CDC_LEFT_N
CDC_RIGHT_P
CDC_RIGHT_N

20_0402_5%

C221 1
HPGND

R447 10_0201_5% 2 @

22
23
28
27

LOP
LON
ROP
RON

DACDAT
ADCDAT

38
3
4

C230 1
C231 1

CDC_COM_MIC

2 1K_0402_5%

EN_SPEK
SHORT_DETECT

2 0_0201_5%

R446 10_0201_5% 2

MCLK
BCLK
LRC

7
9

<14> CODEC_IN
<14> CODEC_OUT
R430 1

9/19 Modify Value from 1u to 0.1u Acer Request.

CDC_HP_R
CDC_HP_L
R443 10_0201_5% 2 @

16
18
17

HPOUTR
HPOUTL
HPGND

SCLK
SDIN
INTERRUPT

2
6
8

<6> AUDIO_CLK_R
<14> AUDIO_SCLK2_VOICE
<14> AUDIO_FS2_VOICE

Audio Codec

DCVDD
DBVDD
CPVDD
AVDD

37
36
5

<6> CDC_IRQ#

8/24 Modify Net Name for Acer request.

R196
2

0.1U_0201_10V6K

+VDD_1V8_AUDIO

R256 1

R457
300K_0201_1%

20_0402_5%

C220

08/09 Add C236 for AUDIO_CLK_R

<7,10,14,26,32,34>

Close U113.24
1

R194
2

0.1U_0201_10V6K

C219
68P_0201_25V8
@

+VPOS_CDC

C228

WM8903LGEFK-RV_QFN40_5X5

R209
620_0402_5%

Int. Speaker Conn.

08/01 Change L20-L23 to SM01000DI00

5
6

SP02000SC00

1
2

3
4

33P 50V J NPO 0201

1

GND1
GND2

D8

SCA00001W00
B+

SP02000S000

2 0_0402_5%

2
C238

1
10U_0402_6.3V6M

1
C239

2
R197
0_0201_5%

C202

C3
A3

SPKR_LEFT
SPKR_LEFT#

A1
C1

+MIC_BIAS

C2

APA2010HAI-TRG WLCSP 9P CLASS D AMP

1
2
3

CE
VDD
NC
GND VOUT

100P_0201_25V8J

100P_0201_25V8J

100P_0201_25V8J

+3VS

4
LDO@
C145
1U_0402_6.3V4Z

SA000059P00

LDO@
C143
1U_0402_6.3V4Z
LDO@
C144
0.1U_0201_10V6K

LDO@
C116
0.1U_0201_10V6K

2
R200

1
0_0201_5%

EAR_JACK_GND

<20>

SHUTDOWN#

close to 8903 for psudo differential

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Audio Codec / AMP

Size
C
Date:

C2561

COM_MIC
SPKR_RIGHT
SPKR_RIGHT#

C3
A3

Issued Date

RP114Q182D-TR-FE_SC-88A5
LDO@

B1
B2
VO+
VO-

resistor is for gain setting

APA2010HAI-TRG WLCSP 9P CLASS D AMP

IN+
IN-

150K_0201_5%
1
2
1 R267
2
R268
150K_0201_5%
EN_SPEK

SHUTDOWN#

A2
B3

1U_0402_6.3V4Z
2
2
1U_0402_6.3V4Z

VDD
PVDD

B1
B2
VO+
VO-

C2

U5
C248
CDC_RIGHT_P
1
CDC_RIGHT_N
1
C249

GND
GND

IN+
IN-

C2541

U8

4.7U_0402_6.3V6M

2
1U_0402_6.3V4Z

A2
B3

EN_SPEK

resistor is for gain setting

A1
C1

VDD
PVDD

U2
150K_0201_5%
1
2
1 R259
2
R263
150K_0201_5%

GND
GND

1U_0402_6.3V4Z
C250
CDC_LEFT_P 1
2
CDC_LEFT_N 1
2
C251
1U_0402_6.3V4Z

2
C2551

+VDD_1V8_AUDIO_LDO

R198
2.2K_0201_1%

AMIC_L+
AMIC_L-

1
1

+MIC_BIAS

+AMP_VDD

1
10U_0402_6.3V6M

CONN@

+AMP_VDD
R445 1

2
2

10/7 Change L51 and L50 from 60ohm to 68 ohm.

10/7 Change C2531,C2541,C2551 and C2561 from 100P to 47P
9/22 Add for MIC noise issue
01/18 Change to current symbol

ACES_50281-0020N-001
TVNST52302AB0_SOT523-3

+AMP_VDD

2
C261

C206
2
1

2
C207
33P 50V J NPO 0201

1
2

G1
G2

ACES_50281-0040N-001
CONN@

JMIC1
AMIC_L+_R

SCA00001W00

C243
2

620_0402_5%
1

SCA00001W00

C242
2

R269
2

D7
TVNST52302AB0_SOT523-3

D6
TVNST52302AB0_SOT523-3

SPK_L#
SPK_L

SPK_R#
SPK_R

C241
2

AMIC_L+
AMIC_L-

C240

1
2
3
4

L50
L51

referece to Acer
C2531

JSPK1
1
2
3
4

SPK_L#
SPK_L
SPK_R#
SPK_R

FBMA-101_0402
FBMA-101_0402
FBMA-101_0402
FBMA-101_0402

100P_0201_25V8J

1
1
1
1

100P_0201_25V8J

2
2
2
2

100P_0201_25V8J

L20
L21
L22
L23

100P_0201_25V8J

SPKR_LEFT#
SPKR_LEFT
SPKR_RIGHT#
SPKR_RIGHT

AMIC_LEFT+
AMIC_LEFT-

AMIC_RIGHT-

10/04 Add R269,C206 and C207 for Main Mic issue.

B

S SUPPRE_ KC FBMA-11-100505-680T 0402

S SUPPRE_ KC FBMA-11-100505-680T 0402

AMIC_RIGHT+

AMIC_LEFT-

0_0402_5%

R206
620_0402_5%

AMIC_LEFT+

2 C233
100P_0201_25V8J

2
R221
620_0402_5%

AMIC_R+ <20>
AMIC_R- <20>

from Docking/B

2 C235

47P 25V J NPO 0201

SD028000080

10U_0402_6.3V6M

2
R260
620_0402_5%

LDO@

1
1

47P 25V J NPO 0201

C237

2
2

47P 25V J NPO 0201

2
2.2U_0402_6.3VM

C398
1

620_0402_5%

NONLDO@

Vth (Max) = 1.5

R213
MIC_GND 2

10U_0402_6.3V6M

Q23
BSS138W-7-F_SOT323-3
NONLDO@

4.7U_0402_6.3V6M

2
G

C237

+MIC_BIAS

C232

C257

2
2.2U_0402_6.3VM

47P 25V J NPO 0201

620_0402_5%
MIC_GND

L18
L19

C234

1
1
C399

AMIC_RIGHT+
AMIC_RIGHT-

R212
620_0402_5%

1
C270
1

Second MIC

Main MIC

R265
MIC_GND 2

S SUPPRE_ KC FBMA-11-100505-601T 0402

S SUPPRE_ KC FBMA-11-100505-601T 0402

R243
620_0402_5%

11/17 Modify C210&C211 form 100P to 33P for Acer AUDIO request.
12/2 Modify R409 and R423 from 0ohm to 68nH for Acer AUDIO request.

10/2 Modify C398&C399 from 1u to 2.2u for Acer AUDIO

10/2 Modify C257&C270 from 1u to 10u for Acer AUDIO

+VDD_1V8_MIC

R151 1
2 0_0402_5%
NONLDO@
+VDD_1V8_AUDIO_LDO
R165 1
2 0_0402_5%
LDO@

SA00003MP00

9/22 Add R151&R165 for MIC noise issue

C211
33P_0201_50V8J

C229

<20>
+VDD_1V8_AUDIO

C210
33P_0201_50V8J

HP_L

8/25 Modify Value for Acer request.

HP_L

<20>

CDC_HP_L

HP_R

HP_R

R409 2
1
68NH_5% LQG15HS68NJ02D
R423 2
1
68NH_5% LQG15HS68NJ02D

CDC_HP_R

+VNEG_CDC

2.2U_0402_6.3VM

C213
1U_0402_6.3V4Z

+CPVDD

2.2U_0402_6.3VM

2
C218
68P_0201_25V8
@

+VDD_1V8_AUDIO

4.7U_0402_6.3V6M

1
2

4.7U_0402_6.3V6M

+VDD_1V8_AUDIO
R191 @
0_0201_5%

R190 @
0_0201_5%

C236
33P_0201_50V8J

AUDIO_SCLK2_VOICE
1

AUDIO_CLK_R

Document Number

Rev
1.0

Picasso 2 R04
Wednesday, January 18, 2012
1

Sheet

15

of

38

GYRO_FSYNC

V_logic must be <= VDD at all time

GYRO_CLKIN

R255 @
10K_0201_5%
2

R253 @
10K_0201_5%

+VDD_3V3_SENSOR

GYRO
U29
GYRO_CLKIN
IME_DA
IME_CL
+VDD_1V8_SENSOR

1
6
7
8
9

AD0

CLKIN
IME_DA
IME_CL
VLOGIC
AD0

VDD
REGOUT
FSYNC
INT
CPOUT
CLKOUT

1
C256
0.1U_0201_10V6K

2
3
4
5
14
15
16
17

NC
NC
NC
NC
NC
NC
NC
NC

13

C253

2 0.1U_0201_10V6K

10
11
12
20
22

C254
1
GYRO_FSYNC

2 0.1U_0201_10V6K

1
C255

GYRO_INT_R

<6>

07/28 Change C255 to SE00000TE00

23
24

SCL
SDA

R220
1
2
0_0201_5%

GYRO_INT
2
2200P_0201_50V7K

GEN1_I2C_SCL
GEN1_I2C_SDA

<7,20>
<7,20>

18

GND

19
21

RESV
RESV

MPU-3050_QFN24_4X4
AD0
1

G Sensor

R224
10K_0201_5%
2

U31
1
2
3
4
5

+VDD_1V8_SENSOR
1
C

C259
0.1U_0201_10V6K

07/28 Change R224 to 10K

IO VDD
DNC
DNC
GND
VDD

10
9
8
7
6

SDA
SCL
DNC
INT
DNC

IME_DA
IME_CL
C

G_INT

1
R231

P Sensor

<7>

08/09 Change PAD2 to CLIP_1P8X3P2

08/12 Change PAD2 footprint to EMIST_SQ-21G_1P
+VDD_3V3_SENSOR

CTRL
2

1
2
3

OUT
VSS
CTRL

@
CX
VDDHI
VREG

6
5
4

CAP3

CAP_VREG

IQS12800100TSR_TSOT23-6
1

R13
10K_0402_5%
@
1

@
C114
1U_0402_6.3V4Z

D11

1
C112 @
100P_0402_50V8J

U6
POUTL_R

CONN@

+VDD_3V3_SENSOR

R16
@
470_0402_5%
2
1

SCA00001W00

C113 @
1U_0402_6.3V4Z

TVNST52302AB0_SOT523-3
1

1
2
R15
@
0_0402_5%

C111
@
2P_0402_50V8C
1

TP
PAD2

R14
@
4.7K_0402_5%

POUT_WIFI

G_ACC_INT

0_0201_5%

KXTF9-4100_LGA10_3X3

<4>

close to PAD2

9/15 Add D11 to Compal ESD request.

10/13 Modify R14,U6,C111,R16,D11,C113,C112 and C114 from WIFI @ to @ .

A

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

GYRO/P-Sen/G-Sen
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

16

of

38

U39
+VDD_VCM_3V3

VIN

2
2

<7> EN_CAM_2V8

GND
NC

EN

C281
0.1U_0201_10V6K

C277
0.1U_0201_10V6K

1
C278
2.2U_0402_6.3VM

C279
0.1U_0201_10V6K

C280
47U_0805_4V6

C282
0.1U_0201_10V6K

C283
2.2U_0402_6.3VM

SA00004BW00
2

Vth=1.6V

+VDD_CAM_1V8_R

APL5603-28BI-TRG_SOT23-5

@ R257
100K_0201_5%

+VDD_CAM_2V8_R

+VDD_CAM_2V8
1

C276
2.2U_0402_6.3VM

VOUT

+3VS

10/17 Change L24-L28,L34 to 0 ohm

08/05 Change L24-L28,L34 to mount
08/05 Change L24-L28,L34 to SM070002N00

11/3 Modify R257 to unmount for panel garbage issue.

R258
1

<6> 5M_CAM_CLK#_R

5M_CAM_CLK#

2
0_0201_5%

L24 @
4
1

SM070002N00
2
JCAM1

OCF1210900YZF_4P
2M_CAM_DA2
2M_CAM_DA2#

R261
1

<6> 5M_CAM_CLK_R

0_0201_5%

2M_CAM_CLK
2M_CAM_CLK#

R262

2M_CAM_DA1#
2M_CAM_DA1

<6> 5M_CAM_DA1#_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47

5M_CAM_CLK

5M_CAM_DA1#

08/09 Add C373,C374,R271 for CAM_MCLK

0_0201_5%

R271
3

SM070002N00

1
C373
22P_0201_25V8

OCF1210900YZF_4P
5M_CAM_DA1

CAM_MCLK_R

2
0_0201_5%

C374
33P_0201_50V8J

5M_CAM_DA2
5M_CAM_DA2#
5M_CAM_CLK
5M_CAM_CLK#
5M_CAM_DA1
5M_CAM_DA1#

R264
1

<6> 5M_CAM_DA1_R

<6> CAM_MCLK

L25 @
4

0_0201_5%

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
GND
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48

2M_CAM_PWDN

<6>

+VDD_CAM_2V8_R

+VDD_CAM_2V8

1
R274

2
0_0402_5%

2M_CAM_RST# <6>
CAM_I2C_SCL <6,26,35>
CAM_I2C_SDA <6,26,35>+VDD_CAM_1V8_R

+VDD_CAM_1V8

1
R275

2
0_0402_5%

5M_CAM_RST# <6>
CAM_LED_EN <35>
5M_CAM_PWDN <6>

+VDD_VCM_3V3

PANAS_AXK8L44124BG
CONN@

R266
1

<6> 5M_CAM_DA2#_R

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
GND
GND

5M_CAM_DA2#

2
0_0201_5%

LTCX003I300

L26 @
4
1

Camera Board

SM070002N00
2

reference Acer schematic

CAM_LED_EN
5M_CAM_RST#
CAM_I2C_SCL
CAM_I2C_SDA
5M_CAM_PWDN

OCF1210900YZF_4P
R270
1

<6> 5M_CAM_DA2_R

5M_CAM_DA2

2
0_0201_5%

C321
10P_0201_50V8J

C327
10P_0201_50V8J

C334
10P_0201_50V8J

C361
10P_0201_50V8J

C362
10P_0201_50V8J

R277
1

<6> 2M_CAM_CLK#_R

2M_CAM_CLK#

2
0_0201_5%

L27 @
4
1

SM070002N00
2

reference Acer schematic

OCF1210900YZF_4P
R280
1

<6> 2M_CAM_CLK_R

2M_CAM_CLK

2M_CAM_RST#
2M_CAM_PWDN

0_0201_5%
R281
1

<6> 2M_CAM_DA1#_R

2M_CAM_DA1#

0_0201_5%
2

L28 @
4
1

C363
10P_0201_50V8J

C366
10P_0201_50V8J

SM070002N00
2

OCF1210900YZF_4P
R283
1

<6> 2M_CAM_DA1_R

2M_CAM_DA1

2
0_0201_5%
R425

<6> 2M_CAM_DA2#_R

2M_CAM_DA2#

2
0_0201_5%

L34 @
4
1

SM070002N00
2

OCF1210900YZF_4P
R386
1

<6> 2M_CAM_DA2_R

2M_CAM_DA2

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

0_0201_5%

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

5M Camera/ 2M Camera
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

17

of

38

12/16 Modify R454 from 3G@ to LTE@

to meet SPEC.

UIM_DATA

UIM_CLK
2

UIM_RST

SIM_DET
R454
15K_0201_5%

3G@

2
R285
100K_0201_5%

+UIM_PWR

8/23 Modify for Leakage issue.

+VDD_1V8_BB_TEGRA

D14 @
TVNST52302AB0_SOT523-3

LTE@

D15 @
TVNST52302AB0_SOT523-3

Q15

SCA00001W00

+UIM_PWR

SCA00001W00

UIM_DATA

+UIM_PWR_R
SIM_DET

AO3413_SOT23-3
3
3G@

V_MINCARD_3V3

T30 internal PU , reserve

R287
100K_0201_5%
3G@

JSIM1

<7>

SIM_DET

3G@ C285
10P_0201_50V8J

3G@ C297
10P_0201_50V8J

8
9

D+
DGND
GND

+UIM_PWR

1
2
3

UIM_RST
UIM_CLK

VCC
RST
CLK

R286 3G@
1
2
47K_0201_1%
3G@ C287
39P_0201_50V8J

10
11

3G@ C286
10P_0201_50V8J

1
@ C288
1U_0402_6.3V4Z

1
C289 3G@
0.1U_0201_10V6K
SIM_DET

R76
1

UIM_DATA

GND
VPP
I/O
DET

3G@
2
1

10K_0201_5%

TAITW_PMPAT7-08GLBS1N14H0
CONN@

SP07000NX00

Detect pin
Normal : short GND
Insert Card : Open

C290 3G@
0.047U_0201_10V6K

2
Q21
BSS138W-7-F_SOT323-3
3G@

2
G
3

4
5
6
7

C301 3G@
1U_0402_6.3V4Z

SIM CARD

SGA00006500
V_MINCARD_3V3
V_MINCARD_3V3

V_MINCARD_3V3

1
+

C292
3G@

C293
3G@
1
10U_0402_6.3V6M

2200P_0201_16V7K
1
C295
3G@
2
0.01U_0201_16V7

C291
@

1
C296 3G@
100U_A_6.3VM_R70M

V_MINCARD_3V3

1
C305
3G@
100U_A_6.3VM_R70M

C307
3G@
100U_A_6.3VM_R70M

C306 3G@
100U_A_6.3VM_R70M

10/04 Modify R55 from 2.2K to 1K.

C294
3G@
1
22P_0201_25V8

8/23 Add for Discharge V_MINCARD_3V3

8/25 Modify part form SB00000EO10 to SB00000IV00
change Cap value to 100U

V_MINCARD_3V3

+3VS

0.1U_0201_10V6K
2

V_MINCARD_3V3

<4> 3G_WAKE#

V_MINCARD_3V3

LTE_GPS_RESET

LTE@
1

0_0201_5%

Q49
S S TR DMN3150LW-7 1N SOT-323-3
Vth=1.4V

2
G

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
GND

4
3
6
1

DMN2004DWK-7_SOT363-6

need check module internal PU or not , All vender.

UIM_DATA
UIM_CLK
UIM_RST

3G_DISABLE#

+UIM_PWR_R

<4>

@
R292
1
2
0_0402_5%

USB2_N2_COMM

3G_USB_DN

<6>

3G_USB_DP

<6>

WCM-2012-900T_4P
2

3
L29

1
3G@

USB2_P2_COMM

1
2
0_0402_5%

R295
@

08/05 Change L29 to mount

LTE@

LTCX003HC00

WWAN Card

Add R92 and Q49 to GPS_RESET of LTE module .

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

3G card
Size
C
Date:

S1
D1
D2
S2

3G_DISABLE#

ACES_50709-0524W-001
CONN@

R92
<7,21> GPS_RESET#

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
GND

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
52
54

G2

3G@

R81
1M_0201_1%
3G@

C298 3G@
22P_0201_25V8
JMIN1
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53

1
R291
100K_0201_5%
@

G1

T30 internal PU , reserve

<7,30> EN_3V3_MODEM

@
2

R288
100K_0201_5%

V_MINCARD_3V3

Q45

V_MINCARD_3V3
V_MINCARD_3V3

R55
1K_0201_1%
3G@
2

R80
100K_0201_5%
3G@

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

18

of

38

8/25 Modify R451&R455 from 47K 1% to 4.7K 5%

+VDD_3V3_LCD_TEGRA

+VDD_3V3_LCD_TEGRA

+VDDIO_HDMI
C299 2

2
1

G
D

DDC_SCL

R420
1

Q43A
2N7002KDWH 2N SOT363-6

<4> EN_HDMI_5V0

HDMI_DDC_SCL

2
0_0402_5%

<4> DDC_SDA_R

+5VS

3.3V

Vth=2.0

1
D

0.1U_0201_10V6K

U40

Reserved

1
S

<4> DDC_SCL_R

C300 2
R450
4.7K_0201_5%

R449
4.7K_0201_5%

R455
4.7K_0402_5%
2

R451
4.7K_0402_5%

0.1U_0201_10V6K

IN

OUT

IN

GND

EN

DIS
TMLPAD

+VDDIO_HDMI

2
1 R323
2
0_0201_5%

3
7

G5287RR1U_TDFN6_1P6X1P6
DDC_SDA

R426
1

HDMI_DDC_SDA

2
0_0402_5%

Q43B
2N7002KDWH 2N SOT363-6

C400
4.7P_0402_50V8C

08/04 Change U40 to SA000055200 (TDFN6)

C401
4.7P_0402_50V8C

07/28 Change C400,C401 to SE07147AC80

to SB503010020 for HF request.

1

HDMI_TXD1N_R
HDMI_TXD0P_R

2
G
HDMI_DET

SC100000S00

<4>

HDMI_TXCN_R
HDMI_CEC_CON

Q39

1
1

@ C67
1000P_0201_16V7K

HDMI_CEC_CON

HDMI_DET_T30S

R448
100K_0201_5%

HDMI_DDC_SCL
HDMI_DDC_SDA

SSM3K7002FU_SC70-3
+VDDIO_HDMI

3
S

D1
RB751S40T1_SOD523-2~D
D2

HDMI_TXD0N_R
HDMI_TXCP_R

FDV301N_G 1N SOT23-3
1

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

HDMI_TXD2N_R
HDMI_TXD1P_R
R436
1M_0201_1%

Q1

R24
32.4K_0402_1%

<7> HDMI_CEC

HDMI_DET
HDMI_TXD2P_R

12/2 Modify Q1 from SB503010010

R25
162K_0402_1%

JHDMI1

+VDD_3V3_LCD_TEGRA

+3VS

20
21
22
23

BELLW_80082-5021
CONN@

RB751S40T1_SOD523-2~D

HP_DET
Utility
D2+
D2_Shield
D2D1+
D1_Shield
D1GND0
D0+
GND1
D0_Shield GND2
D0GND3
CK+
CK_Shield
CKCEC
DDC/CEC_GND
SCL
SDA
+5V

SC100000S00

DC232001M10

HDMI Type D Connector

08/05 Change L30-L33 to SM070002N00
HDMI_TXD0P_R

1 R310
2
@ 0_0201_5%

<4> HDMI_TXD0P

4
1

L31

SM070002N00
2

OCF1210900YZF_4P

<4> HDMI_TXD0N

<4> HDMI_TXCP

4
1

HDMI_TXD0N_R

1 R314
2
@
0_0201_5%
L32

HDMI_TXCP_R

1 R317
2
@ 0_0201_5%

SM070002N00
2
B

<4> HDMI_TXD1N

1 R313
2
@ 0_0201_5%

HDMI_TXD1N_R

<4> HDMI_TXD2P

1 R315
2
@ 0_0201_5%

HDMI_TXD2P_R

L33
3
2

SM070002N00
2

OCF1210900YZF_4P
<4> HDMI_TXCN

OCF1210900YZF_4P

1 R312
2
@ 0_0201_5%

HDMI_TXD1P_R

1 R311
2
@ 0_0201_5%

<4> HDMI_TXD1P

L30

SM070002N00
2

OCF1210900YZF_4P
HDMI_TXCN_R

<4> HDMI_TXD2N

1 R318
2
@ 0_0201_5%

HDMI_TXD2N_R

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

HDMI
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Sheet

Tuesday, January 17, 2012

1

19

of

38

1
LINE_OUT_DET# <7>
DEBUG_UART1_RX <7>

<7>

LINE_DOCK_L <15>
LINEGND <15>
LINE_DOCK_R <15>

R324
DOCK_DET_R# 1

PAD

<4>

POUT_3G

<7,32> ONKEY#
C

<7> SC_LOCK#
+VDD_1V8_SENSOR
<6> LIGHT_INT
GEN1_I2C_SDA
GEN1_I2C_SCL
HP_IN
HP_LEFT
HP_RIGHT
<15>

COM_MIC

<15> EAR_JACK_GND

DOCK_DET#

<6>

2
R320

VIB_EN_T30S

<4>

0_0201_5%

R321
100K_0201_5%

RB751V-40_SOD323-2
C146
4.7U_0402_6.3V6M

VIBRATOR

10/19 Add R324 and C146 to Dock_DET# for debouncing.

10/19 Change power domain from +VDD_1V8_CAM_TEGRA to VDD_1V8_PMU_VRTC
10/31 Modify C146 from 0.1U to 4.7U for Acer HW request.
11/7 Add D21 R431 to DOCK_DET_R# leakage issue.

2
1K_0201_1%

HP_DET#

<6>

+VDD_3V3_GMI_TEGRA
+VDD_1V8_BB_TEGRA

C9
0.1U_0201_10V6K
1

1
R234
100K_0201_5%

Flash LED / Board

JLED1
<35>
<35>

1
2

LED+
LED-

1
2
DEBUG_UART1_RX

<7> DEBUG_UART1_RX
3
4

D16

C397
0.1U_0201_10V6K

For debug port leakage

U3

D19
RB751V-40_SOD323-2
2
1
HP_LEFT

A2
A3
B3
C3
D3

<15>
HP_L
<7> UART_SW

GND1
GND2

V+
NO2
NO1
COM2
COM1
NC2
NC1
IN2
IN1
GND

ACES_50281-0020N-001
CONN@
TVNST52302AB0_SOT523-3

SCA00001W00
<15>

R210
100K_0201_5%

9/15 Add D16 to Compal ESD request.

HPGND

A1
B1
C1
D1
D2

DEBUG_UART1_TX

HP_RIGHT
HP_R

<7>

<15>

TS5A22362YZPR_DSBGA10

SP02000S000

close to JLED1

SA00005AE00
9/29 Modify U3 from TS5A22364 to TS5A22362.
SA00004ON00------>SA00005AE00

HP Switch

R345 @
0_0201_5%
2

R347
0_0201_5%
@

HP_IN

ACES_88196-3041
CONN@

Function / Board

R9
100K_0201_5%
R28
1

2
G
S

PAD
T20@

2
2

SP01000QQ00

D
Q20
BSS138W-7-F_SOT323-3

T19
@

<4,7> VOL_UP#
<4,7> VOL_DOWN#
+VDD_3V3_SENSOR

R431
100K_0201_5%

D21

0_0201_5%

remove POUT_WIFI net on JFUN1

Docking / Board

VB_N
EN_P_SENSOR

<4> EN_P_SENSOR

C303
0.1U_0201_10V6K

+VDD_1V8_CAM_TEGRA

R429
100K_0201_5%

+VDD_1V8_AUDIO

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
G1
G2

VB_N

AMIC_R+ <15>
AMIC_R- <15>

+3VS_VB

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

Q4
BSS138W-7-F_SOT323-3

VDD_1V8_PMU_VRTC

08/09 Add C375,C376 for B+

08/13 Add EN_P_SENSOR for P-sensor PWR Switch

<27> O_LED_CTL
<27> W_LED_CTL

2
G

HOT_RST#

for IR function

<32>

DEBUG_UART1_RX

JFUN1

B+

+3VS_VB
HDRST

1 C375

R432
100K_0201_5%

2 33P_0201_50V8J

1 C376

R316
0_0201_5%
R433
56K_0201_1%

DC_IN

C386

LTCX003I300

0.1U_0201_10V6K

08/09 Add C385,C386 for DC_IN

08/12 Delete C385

1.5 A

PANAS_AXK8L44124BG
CONN@

27P_0201_25V8

VDD_1V8_PMU_VRTC

<4> POUT_3G_1

VDD_1V8_PMU_VRTC

0.1U_0201_10V6K
VBUS_USB

1A (Max)

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48

HOT_RST#
<27> DOCK_DET_R#

+VDD_3V3_SENSOR

2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
GND
GND

+VDD_1V8_SENSOR

GEN1_I2C_SCL
GEN1_I2C_SDA

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
GND
GND

+3VS

USB1_DN
USB1_DP

1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47

08/09 Add C381,C382 for VBUS_USB

<6> USB_HOST_DN
<6> USB_HOST_DP
<6>
<6>

C381
JDOCK1
1A (Max)

<6>
USB1_ID
<6,27> ENABLE_USB_HOST

<6> COMPASS_DRDY
<7,16> GEN1_I2C_SCL
<7,16> GEN1_I2C_SDA

2 33P_0201_50V8J

1 C377

2
+5VS

08/09 Add C377,C383 for +5VS

C382

1 C383

0.1U_0201_10V6K

33P_0201_50V8J

10/13 Modify R345 from mount to @ for Acer AUDIO request.

Micro SD

+VDD_3V_SD
+VDD_3V_SD

reference NV schematic

C311
0.01U_0201_16V7

R337
2

Remove R332

47K_0402_1%

C312
1U_0402_6.3V4Z

reference PBJ20
reserve for 33 0hm
JMSD1
<5> SDMMC_DAT2
<5> SDMMC_DAT3
<5> SDMMC_CMD

Detect pin
Normal : Open
Insert Card : Short GND

<5> SDMMC_CLK
<5> SDMMC_DAT0
<5> SDMMC_DAT1
<7> SD_DET#

R343 2
R342 2
R341 2

1 0_0201_5%
1 0_0201_5%
1 0_0201_5%

SDMMC_DAT2_R
SDMMC_DAT3_R
SDMMC_CMD_R

R368 2

1 0_0201_5%

SDMMC_CLK_R

R340 2
R339 2

1 0_0201_5%
1 0_0201_5%

SDMMC_DAT0_R
SDMMC_DAT1_R
2
R344
1

reference Acer schematic

1
2
3
4
5
6
7
8
9
10

1
0_0201_5%

DAT2
DAT3
CMD
VDD
CLK
Vss
DAT0
DAT1
DETECT1
DETECT2

G1
G2
G3
G4
G5

11
12
13
14
15

PROCO_879S-R010-00A0

C325
10P_0201_50V8J

CONN@

11/28 Change JMSD1 form SP07000GQ00 to SP07000TV00

SDMMC_CLK_R
SDMMC_DAT0_R
SDMMC_DAT1_R
SDMMC_DAT2_R
SDMMC_DAT3_R
SDMMC_CMD_R

C367
10P_0201_50V8J

C368
10P_0201_50V8J

C369
10P_0201_50V8J

C370
10P_0201_50V8J

C371
10P_0201_50V8J

C310
10P_0201_50V8J

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

S/B conn / Vibrator / Micro SD

Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

20

of

38

+2V8_GPS

GPS_ANT2

Input

Output

I-PEX_20429-001E
CONN@

07/27 Change GPSANT from

LTCX003HH00 to SP060004L00

GND
GND
GND

D9 @
1P_0402_50V NPO

GPS@
2

GPS_ANT4

K9

C315
5.1NH_0.3NH_LQG15HN5N1S02D
GPS@

D17 @
1P_0402_50V NPO

J8
J9
K8
K10
E10

close to GPSANT

remove reserve 32K from T30S

GPS_CLK_26M_R

G10

GPS_CLK_32K_R

K2
F10

GPS_CLK_26M 1
R352 GPS@

2 GPS_CLK_26M_R
0_0402_5%

G9

GPS@
1

OE

Clock Output

GPS_CLK_32K

R351 1 GPS@

K6
CAL_REQ

LPO_IN
NC
NC

NC

NC

SYS IF

AUX_HI
VDD_AUX_O

GND
2

GND

VDD_AUX_IN
A8
32.768KHZ_15PF_KK3270032

A7

<7> GPS_PWRON

R383

2 0_0201_5%

GPS_RESET#_R

A5

R416

2 0_0201_5%

GPS_PWRON_R

J4
H2
K1
B3

GPS_PWRON_R

HOST_REQ
GPS_SYNC/PPS_OUT
LNA_EN
C_GPIO_6
C_GPIO_7

REGPU
D_GPIO_5
D_GPIO_6

TM1
TM2
TM3

REF_CAP

SCL2/UART_TX
SDA2/UART_RX
UART_nRTS
UART_nCTS

2
1

C332
1U_0402_6.3V4Z
GPS@

2
C326
0.1U_0201_10V6K
GPS@

F2
F7
H3
H4
J2
G8
G7
J1

1
C353
68P_0201_25V8
GPS@

FDG6331L_SC70-6
GPS@

<7> EN_VDD_GPS

C324
4.7U_0402_6.3V6M
GPS@

G6
G4
G1
F1
G5
C10
C8
D5

Vth = 1.5

1.8V

R304
1M_0402_5%
B

10/06 Modify R304 from @ to mount.

D8
D6
D9
J5

+3V3_GPS
R428 1 GPS@
0_0402_5%

VDD_PRE

H5

GPS_VDDC

E9
G2
C7
C3
K5
C6
D7
F3

+1V8_GPS

SB00000SM00
+3VS

+3V3_GPS

Q29

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC
NC
NC
NC
NC
NC

NC
NC
NC

NC
NC
NC

VDD_PRE

NC

PWR

VDDIFP
VDDC
VDDC
VDDC

AVSS
AVSS

VDD1P2_CORE

VSSC
VSSC
VSSC
VSSC
VSSC

VDDIO
VDDIO
VDDIO

C317
GPS_REF_CAP

R417
R421
R434
R435

E1
D1
B2
A1

1
1
1
1

2
2
2
2

0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%

GPS_UART_RXD <7>
GPS_UART_TXD <7>
GPS_UART_CTS# <7>
GPS_UART_RTS# <7>

E5
B1
E6
D4
C4
E3
F6
E7

9/25 Modify R346 from @ to mount for leakage issue.

C2
D10
B4
A9
A10
B9
C9
B10

+1V8_GPS

R346

1
FDG6331L_SC70-6
GPS@

100K_0201_5%
F5
E4
E2

GPS_UART_RXD

E8
J3
K3

G3
F4
B8
C5
D3

SA00004YJ00
+3V3_GPS

6
C331
1U_0402_6.3V4Z
GPS@

C333
2.2U_0402_6.3V6M
GPS@

U50

C347
68P_0201_25V8
GPS@

1
C329
VDD_PRE

1.8V

A2
H1
J6

VDD_BAT

GPS@
1

NC
NC
NC
NC
NC
NC
NC
NC

Vth = 1.5

1U_0402_6.3V4Z
GPS@

1
C319
2.2U_0402_6.3V6M
@

VIN

1
2

GPS_VDDC

EN_VDD_GPS
A

A3
B5

BCM47511IFBG_FBGA100

3
2

NC
NC
NC
NC
NC
NC
NC
NC

R305
1M_0402_1%
GPS@

B6

MEMORY

R303
1M_0402_1%
GPS@

A6

0.01U_0201_16V7
GPS@

C_GPIO_2
C_GPIO_3

Acer request

Q28

D2
C1

GPS@
2
1 0.22U_0201_6.3V6M

C318

+3V3_GPS

RST_N

1
+1V8_GPS

+GPS_AUX_OUT

H6
H7

IFVALID

SB00000SM00

K4

UART/I2C IF
R348
GPS@
100K_0201_5%

VDD_1V8_GEN

B7
H9
F9

NC

26MHZ_10PF_TX5651

<7,18> GPS_RESET#

C330
1U_0402_6.3V4Z
GPS@

H10

TCXO

2 0_0402_5% GPS_CLK_32K_R

C323
GPS@
1U_0402_6.3V4Z

K7

CLK IF

GPS_CAL

OUTPUT

ENABLE/DISABLE
NC
NC

J7
H8

X3

VDD

VCC

F8

5
1

GPS_AUXOP
GPS_AUXON

C316
0.01U_0201_16V7
GPS@

RF

GPS_VSSIF
GPS_VSSPLL
GPS_VSSLNA
GPS_VSSLNA
GND_IFP

+1V8_GPS
A4

GPS@
X2

9/15 Add D17 to Compal ESD request.

9/15 Add D9 to Compal ESD request.

+GPS_AUX_OUT

C379
0.1U_0201_10V6K
GPS@

GPS_RFIP

0_0201_5%

SP060004L00

L38
1

GPS_ANT3

22P_0402_50V8J

VDD1P2_GRF

C314 GPS@
1
2

GPS_VDDPL

L37
GPS@
SAFFB1G58KA0F0AR14_5P
GPS_ANT1

2
3
5

Ground

2
3
4

2 BLM15AG601SN1D_2P

2.2U_0402_6.3V6M
GPS@
J10

GPSANT

C313

GPS@
L35

GPS_VDDIF

2
2

Antenna

L39
GPS@
47NH_LQG15HN47NJ02D_5%

GPS_VDDLNA

C322
GPS@
0.1U_0201_10V6K

9/02 Modify C315 from GPS@ to @ for RF team request.

9/10 Modify C315 from 1.8P to 2.2P for RF team request.
9/14 Modify L38 from 6.2NH to 7.5P for RF team request.
12/7 Modify L38 from 7.5P to 0 ohm for RF team request.
12/7 Modify C315 from 2.2P to 5.1nH for RF team request. U47

GPS_PWRON_R

VOUT

+2V8_GPS

GND

1
NC

EN
2

Vth=1.6V

C320
2.2U_0402_6.3V6M
GPS@

C335
GPS@
2.2U_0402_6.3V6M

APL5603-28BI-TRG_SOT23-5
GPS@

SA00004BW00

For Antenna circuit

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

GPS POWER SOURCE

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

GPS BCM47511
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Tuesday, January 17, 2012

Sheet
1

21

of

38

SB00000SM00

+3VS

+3VS_WIFI

Q31

dual-Band wifi RF matching , Reserve " 2 Pi " filter

2
C339
1U_0402_6.3V4Z
WIFI@

6
2

C342

1
C341
0.1U_0201_10V6K
WIFI@

4.7U_0402_6.3V6M
2
WIFI@

9/10 Modify C136 from 100P to 1P for RF request.

FDG6331L_SC70-6
WIFI@

R308
1M_0402_1%
WIFI@

C340
68P_0201_25V8
WIFI@

2.4RF_IN_L

R375 1
2

1
<4> EN_WIFI_VDD

2
C137 @
100P_0402_50V8J

2
3
4

I-PEX_20429-001E
CONN@

C138 @
100P_0402_50V8J

SP060004L00

AH662 use 1U, AH663 use 0.1U

+1.8VS_WIFI

Q32

+SR_PA_OUT

C356
1U_0402_6.3V4Z
NH660@

C354
0.1U_0201_10V6K
2 WIFI@

C352
4.7U_0402_6.3V6M
1
WIFI@

6
2

1
2

FDG6331L_SC70-6
WIFI@

C349
1U_0402_6.3V4Z
WIFI@

C351
68P_0201_25V8
WIFI@

9/21 Add D10 to Compal ESD request.

2.4RF_IN

C356

2
5

R319
1M_0402_1%
WIFI@

8/23 Add for AH663.

+VDD_WL_PA

3
2

AH663@

C359
1U_0402_6.3V4Z
WIFI@

07/27 Change WIFANT from

LTCX003HH00 to SP060004L00

SB00000SM00

2
C136 @
1P_0402_50V NPO

2.4RF_IN

WIFI@ 2 0_0402_5%

R307
1M_0402_5%
@

VDD_1V8_GEN

C348
1U_0402_6.3V4Z
WIFI@

R387 1

Vth = 1.5

WIFANT
2.4RF_IN_R

WIFI@ 2 0_0402_5%

Ground

C337
1U_0402_6.3V4Z
WIFI@

SE070104Z80
0.1U 16V V4Z

close to H2

D10
@
1P_0402_50V NPO

close to G9

close to WIFANT

EN_WIFI_VDD
Vth = 1.5

+SR_PA_OUT

+3VS

+VDD_LN

+3VS_WIFI

+3VS_WIFI

+VDD_WL_PA

10/19 Add for Discharge +3VS_WIFI

1

reserve

G2

S1
D1
D2
S2

+VDD1P4_WIFI

Q37

4
3
6
1

1
1
+1.8VS_WIFI

C343
4.7U_0402_6.3V6M
WIFI@

C350
0.1U_0201_10V6K
2
WIFI@

3
2

VDD
VOUT
GND
VFB

5
4

CE

R356
0_0201_5%
WIFI@

RP111N331D-TR-FE_SOT23-5
WIFI@

<5>
<5>
<5>
<5>
<5>

WFMMC_CMD
WFMMC_DAT0
WFMMC_DAT1
WFMMC_DAT2
WFMMC_DAT3

R373
R374
R376
R377
R378

1
1
1
1
1

WIFI@
WIFI@
WIFI@
WIFI@
WIFI@

2
2
2
2
2

0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%
0_0201_5%

08/09 Add C387,C388,R272 for WFMMC_CLK

08/25 Modify C387&C388 from mount to unmount

G1
G3
F2
F1
G2
F3

E6
E4
D6
C6
<7>
WF_RST#
<7> WF_WAKE#

R382

1 WIFI@

2 0_0201_5%
TP36

WF_RST#_R

TP34
TP35
+SR_PA_OUT

C345 WIFI@
1
2

0.01U_0201_16V7

C344 WIFI@
1
2

4.7U_0402_6.3V6M

E3
G7
H3
J2

<7> CLK_32K_OUT

R384 1 WIFI@

2 0_0402_5%

RTC_32K_WIFI

D3
H8
D9

C355 WIFI@
1
2

+VDD_CORE

C357 WIFI@
1
2

+VDD_LN

ANT_MAIN_EN
ANT_AUX_EN
BT_I2S_DI
BT_I2S_DO
BT_I2S_WS
BT_I2S_CLK

WL_GPIO_5
WL_GPIO_6

BT_PCM_SYNC
BT_PCM_CLK
BT_PCM_IN
BT_PCM_OUT

WL_SHUTDOWN#_RST#
WL_HOST_WAKE
WL_UART_TX
WL_UART_RX

BT_DEVICE_WAKE
BT_HOST_WAKE
BT_SHUTDOWN#
BT_RST#

HSIC_DATA
HSIC_STROBE

BT_UART_RTS#
BT_UART_CTS#
RTC_CLK

4.7U_0402_6.3V6M

+VDD1P4_WIFI
C336
WIFI@
2
1

A8
A7

A6
A5
B

2.4RF_IN_L

J7

+1.8VS_WIFI

H4
H6
D7
D5
C7
B6

@ R366
100K_0201_5%

BT_UART_TXD
BT_UART_RXD

G4
F5
F4
G5

BT_PCM_SYNC <7>
BT_PCM_CLK <7>
BT_PCM_OUT <7>
BT_PCM_IN <7>

C8
B7
C3
C4

@ PAD T11
@ PAD T12
@ PAD T13

BT_WAKEUP <7>
BT_IRQ# <7>
BT_PD# <7>
R381

BT_UART_RXD

1 WIFI@

2 0_0201_5%

E7
F7

R365
R370

1 WIFI@
1 WIFI@

2 0_0201_5%
2 0_0201_5%

BT_UART_CTS# <7>
BT_UART_RTS# <7>

F8
E8

R371
R369

1 WIFI@
1 WIFI@

2 0_0201_5%
2 0_0201_5%

BT_UART_RXD <7>
BT_UART_TXD <7>

NC
NC

0.01U_0201_16V7
L40
1

1
2

J3
C2
D1
E2

C1

B1

B4
B3

H1
VDDIO

ANT_FM_TX
ANT_FM_RX
ANT_2G4_5G

A1
A4
A9
B2
B5
B8
C5
C9
D4
D8
E1
E5
E9
F9
G6
G8
H5
H7
J1
J4
J5
J6
J8
J9
A10
C10
E10
G10
J10

C358 WIFI@
1
2

FM_AUDIO_L
FM_AUDIO_R

WL_GPIO_1
WL_GPIO_2

4.7U_0402_6.3V6M

R456 @
15K_0402_5%
R389
1M_0201_1%
WIFI@

GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND

+VDD_LN

D2
F6

SDIO_CLK_SPI_CLK
SDIO_CMD_SPI_DI
SDIO_DATA0_SPI_DO
SDIO_DATA1_SPI_IRQ
SDIO_DATA2_SPI_NC
SDIO_DATA3_SPI_CS

2 WIFI@
0.1U_0201_10V6K

C346

WIFI@

@ C388
33P_0201_50V8J

@ C387
22P_0201_25V8

WFMMC_CLK_R
WFMMC_CMD_R
WFMMC_DAT0_R
WFMMC_DAT1_R
WFMMC_DAT2_R
WFMMC_DAT3_R

2
0_0201_5%

R272
1

<5> WFMMC_CLK
B

VDD_LN_IN
VDD_LN_OUT
VDD1P2_CLDO_OUT
VDD_CORE

2 100K_0201_5%

<4> EN_WIFI_VDD

VIN_LDO

VOUT_2P5_IN
VOUT_2P5_OUT

internal weak pull up resister to VDDIO

CBUCK_OUT

R367

VBAT_IN

WFMMC_CMD_R

A3
H9
H2
B9
G9

U53

SR_PA_OUT
VDD_WL_PA_A_MODE
VDDIO_RF
VDD_BT_PA
VDD_WL_PA

A2

FM power

+1.8VS_WIFI

1
C378

4.7U_0402_6.3V6M

+CBUCK_OUT

+VDD_WL_PA

+3VS_WIFI

+VDD_WL_PA

DMN2004DWK-7_SOT363-6

F1,F2,F3,G2,G3

2 0_0402_5%

B+

EN_WIFI_VDD

G1

+VDD_CORE

Q47
5

R361 1

R94
1K_0201_1%
2

R93
100K_0201_5%

BT_RST# <7>

8/22 Change BOM structure

U53

AH663@

8/22 Change BOM structure

NH660@

AW-NH660

PK29S003200

PK29S003200

WIFI@
2

Footprint use AH662 co-lay

+CBUCK_OUT

2.2UH_VLS252012T-2R2M1R3_1.8A_20%

10U_0402_6.3V6M

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

WIFI/BT AH662
Size
C
Date:

Document Number

Rev
1.0

Picasso 2 R04
Wednesday, January 18, 2012
1

Sheet

22

of

38

From PMU

VDD_1V8_GEN

R395 1

2 0_0201_5%

+VDD_1V8_SDMMC3_TEGRA

10mA

R391 1

2 0_0201_5%

+VDD_3V3_GMI_TEGRA

110mA

R397 1

2 0_0201_5%

+VDD_1V8_AUDIO_TEGRA

10mA

R396 1

2 0_0201_5%

+AVDD_3V3_USB_TEGRA

130mA

R399 1

2 0_0201_5%

+AVDD_1V8_USB_PLL_TEGRA

10mA

R419 1

2 0_0201_5%

+VDD_3V3_DDR_RX_TEGRA

50mA

R401 1

2 0_0201_5%

+VDD_1V8_CAM_TEGRA

10mA

R418 1

2 0_0201_5%

+VDD_3V3_LCD_TEGRA

10mA

R404 1

2 0_0201_5%

+VDD_1V8_BB_TEGRA

10mA

R406 1

2 0_0201_5%

+VDD_1V8_SYS_TEGRA

10mA

R398 1

2 0_0402_5%

+VDD_1V8_DDR_MEM

20mA

R101 1

2 0_0402_5%

+VDDIO_1V8_EMMC

200mA

R157 1

2 0_0402_5%

+VDD_1V8_AUDIO

33mA

R390 1

2 0_0201_5%

+VDD_1V8_SDMMC4_TEGRA

10mA

R402 1

2 0_0201_5%

+VDD_1V8_UART_TEGRA

10mA

+3VS

From PMU

VDD_PMU_LDO3

R442 1

2 0_0402_5%

+VDD_3V3_SDMMC1_TEGRA

10mA

VDD_PMU_LDO8

R412 1

2 0_0402_5%

+VDD_1V0_DDR_HS_TEGRA

30mA

VDD_PMU_LDO6

R410 1

2 0_0402_5%

+AVDD_1V2_DSI_CSI_TEGRA

56mA

VDD_PMU_LDO7

R411 1

2 0_0402_5%

+AVDD_1V1_PLL_TEGRA

54mA

VDD_PMU_LDO4

R407 1

2 0_0402_5%

+VDD_1V2_RTC_TEGRA

20mA

VDD_PMU_LDO1

R422 1

2 0_0402_5%

+VDD_2V85_EMMC

200mA

VDD_PMU_LDO5

R408 1

2 0_0402_5%

+VDD_VCM_3V3

135mA

VDD_PMU_LDO2

R441 1

2 0_0402_5%

+VDD_3V_SD

45mA

VDD_1V2_MEM

R444 1

2 0_0402_5%

+VDD_1V2_DDR_MEM

475mA

12/08 Add U51, C365 , C385 and R437 for EMMC drop issue.
12/16 Modify U51, C365 , C385 and R437 from @ to mount.
+3VS
+VDD_2V85_EMMC

U51

NC
EN

0_0402_5%

C365
1U_0402_6.3V4Z

G9001-300TO1U TSOT-23 5P LDO

H1
H_2P3

SA00005II00

H_2P3 *6

Q26 close to Camera Conn.

H_2P0N *1

+VDD_CAM_1V8
Q26
ME2301A-G_SOT23-3

10/04 Add R19 and Q46 to Discharge +VDD_CAM_1V8.

Q33 close to T30S

SB00000JL00

C33
1U_0402_6.3V4Z

+3VS

+VDD_3V3_FUSE_TEGRA
Q33
ME2301A-G_SOT23-3

C159
1U_0402_6.3V4Z

R300
R326
200K _0201_1%

100K_0201_5%

1
2
3

C384
0.1U_0201_10V6K

100K_0201_5%

@
FD2
FIDUCIAL_C40M80

FD3
FIDUCIAL_C40M80

FD4
FIDUCIAL_C40M80

9/2 Add CLP22~CLP27

9/2 Add CLP28,CLP29
11/8 Del CLP22~CLP27 for ME request
Clip type conn
BOTTOM

CLP1

CLP7

CLP11

CLP17

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

CLP2

CLP8
CLP12

CLP18

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

1
C389
0.1U_0201_10V6K

3.3V

Q25B
DMN2004DWK-7_SOT363-6

<4> EN_T30S_FUSE_3V3

TOP

R325

<7> EN_CAM_1V8#

SB00000JL00

B+

Q46
S TR DMN3150LW-7 1N SOT-323-3

1
3

2
G

H6
H_2P3

R19
2.2K_0201_1%

FD1
FIDUCIAL_C40M80

H5
H_2P3

H8
H_2P0N

VDD_1V8_GEN
C

H2
H_2P3

VDD_PMU_LDO1

1
2

VOUT
GND

R437
2

C385
2.2U_0402_6.3V6M

VIN

SB00000IV00
9/29 Modify Q25 from 2N7002KDWH to DMN2004DWK-7
B

VDD_1V8_GEN

+VDD_1V8_SENSOR
Q35
ME2301A-G_SOT23-3
D

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

CLP3

CLP9

CLP13
CLP19

SB00000JL00

9/2 Modify R330 to meet SPEC sequence

C160
1U_0402_6.3V4Z

+3VS

+VDD_3V3_SENSOR

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

CLP4

CLP10

CLP14

Q38
ME2301A-G_SOT23-3
S

CLP20

R330
2

1
2

<7> EN_SENSOR_1V8#

B+

C390 @
0.1U_0201_10V6K

SB00000JL00

C163
1U_0402_6.3V4Z

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

47K_0201_1%
2

R414
200K _0201_1%

R427 1

<4> EN_SENSOR_3V3

2 0_0201_5%

CLP28

CLP15

CLP21

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

EC0M5000700
EMIST_SUL-12A2M_1P

100K_0201_5%

Q25A
DMN2004DWK-7_SOT363-6

C391
0.1U_0201_10V6K

CLP6

CLP16
CLP29
A

3.3V
R424 1

<7> EN_SENSOR_3V3_2

2 0_0201_5%
EC0M5000700
EMIST_SUL-12A2M_1P

1.8V

9/27 Add EN_SENSOR_3V3_2 from U1.AA3

9/29 Modify R424 from unmout to mount
9/29 Modify R427 from mout to unmount

EC0M5000700
EMIST_SUL-12A2M_1P

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

EC0M5000700
EMIST_SUL-12A2M_1P

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

DC interface/Power Button
Size
C
Date:

EC0M5000700
EMIST_SUL-12A2M_1P

CLP5

R415

10/07 Modify C390 from mount to @.

EC0M5000700
EMIST_SUL-12A2M_1P

Document Number

Rev
1.0

Picasso 2 R04
Wednesday, January 18, 2012
1

Sheet

23

of

38

AC Mode

DC_IN

PU7
PU1
Charger IC
BQ24171

VIN

T30S-R-A1-1.4G
Core Power

PTPS659110A2ZRCR
T30 PWR RAIL
PMU IC

VDD_PMU_LDO4
VDD_1V8_GEN

+VDD_1V2_RTC_TEGRA

VDD_1V0_GEN 6100mA
VDD_1V2_SOC 2500mA

+3VS

PU2
TPS63020DSJR
SYSTEM
Boost-Buck IC

PL3
Batt. Mode

Q28

0.37mA

B+

BATT+
PR19

+1V8_GPS

Q29

250mA

VDD_1V2_MEM

1.8V

+2V8_GPS

VDD_PMU_LDO8

2.8V

+3V3_GPS

+3VS

+VDD_3V3_FUSE_TEGRA

475mA
30mA R412_0_0402

+VDD_1V0_DDR_HS_TEGRA

50mA R419_0_0201

+VDD_3V3_DDR_RX_TEGRA

10mA R418_0_0201

+VDD_3V3_LCD_TEGRA

Q32
Q31

800mA
20mA

+1.8VS_WIFI
+3VS_WIFI

VDD_CPU

1.0V~1.2V

VDD_CORE

3.3V

VPP_FUSE

1.2V

VDDIO_DDR

1.05V

VDD_DDR_HS

3.3V

VDD_DDR_RX

3.3V

WIFI/BT

VDD_5V0_SBY

VDD_RTC

0.9V~1.0V

LCD
+3VS

G5910-50RBU_TDFN6
Charge PUMP
Boost IC

Q33

3.3V

PU4

Charge

40mA

1.0V~1.2V

DDR

GPS

+3VS
U50

Battery
1S2P

20mA R407_0_0402

VDDIO_LCD

HDMI
+3VS

1.8V
3.3V

15mA

Q2

+AVDD_3V3_HDMI_S

80mA

L2

AVDD_HDMI_PLL

3.3V

AVDD_HDMI

1.8V

AVDD_HDMI_PLL

SD Card
VDD_PMU_LDO3

10mA R442_0_0402

+VDD_3V3_SDMMC1_TEGRA

PU3
TPS61030RSAR
SYSTEM
Buck IC

L14

+5VS

3.3V

VDDIO_SDMMC1

WiFi

Touch Panel

10mA R395_0_0201

+VDD_1V8_SDMMC3_TEGRA

1.8V

VDDIO_SDMMC3

5V
Audio
10mA R397_0_0201

+VDD_1V8_AUDIO_TEGRA

1.8V

VDDIO_AUDIO

Camera
VDD_PMU_LDO6

PU2
3G CARD

TPS63020DSJR
3G
Boost-Buck IC

BATT+

56mA R410_0_0402

+AVDD_1V2_DSI_CSI_TEGRA

10mA R401_0_0201

+VDD_1V8_CAM_TEGRA

2750mA
3.3V

V_MINCARD_3V3

+3VS

130mA R396_0_0201

+3VS

10mA R399_0_0201

LVDS Panel

10mA

20mA

+VDD_LED_BL

L3

+AVDD_3V3_USB_TEGRA
+AVDD_1V8_USB_PLL_TEGRA

5V

+AMP_VDD 400mA

AVDD_OSC

1.8V

+VDD_1V8_SDMMC4_TEGRA

LED Board
3V

1.8V

THERMAL

Light Sensor

Camera

R275_0_0402

0.4mA

+VDD_CAM_1V8

Q26

+VDD_CAM_1V8_R

2.8V

0.67mA

VDD_PMU_LDO7

+VDD_1V8_SYS_TEGRA

54mA R411_0_0402

+AVDD_1V1_PLL_TEGRA

10mA R404_0_0201

+VDD_1V8_BB_TEGRA

10mA R402_0_0201

+VDD_1V8_UART_TEGRA

110mA R391_0_0201

+VDD_3V3_GMI_TEGRA

180mA
+VDD_CAM_2V8_R

1.8V
3.3V

P Sensor

+VDD_3V3_SENSOR

1.8V

VDDIO_SYS

1.1V

AVDD_PLL

1.8V

VDDIO_BB

1.8V

VDDIO_UART

1.8V

VDDIO_GMI

DDR
20mA R398_0_0402

+VDD_1V8_DDR_MEM

180mA R444_0_0402

+VDD_1V2_DDR_MEM

+VDD_CAM_2V8
VDD_1V2_MEM
U39

1.8V

VDD1

1.2V

VDD2

3.3V

Q38

+VDD_1V8_SENSOR
Q35

0.07mA

eMMC

R57_49.9_0201

VDD_PMU_LDO1 200mA R422_0_0402

0.35mA
+VDD_1V8_AUDIO
U21

+VDD_2V85_EMMC

R157_0_0402

+3VS

200mA R101_0_0402

44mA

+VDDIO_1V8_EMMC

2.85V

VCC

1.8V

VCCQ

LCD Panel
A

300+171mA
3.3V

DS90C387AVJD
300mA
+LCDVDD

171mA
R122_0_0201 +VDD_LVDS

ES305

Codec

1.8V

1.8V

VDD_PMU_LDO2

45mA R441_0_0402

+VDD_3V_SD

3.3V

3.3V

LVDSVCC

Compal Electronics, Inc.

Compal Secret Data

2011/05/20

Issued Date

Deciphered Date

2012/05/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4

Micro SD

LVDS Transmitter

Security Classification

VDDIO_SDMMC4

MT46H64M32L2JG

R274_0_0402

6.5mA

1.8V

180mA

1.8V

1.8V
0.10mA

Gyro Sensor
VDD

10mA R406_0_0201

1500mA

LED+
LEDG Sensor

3.3V

AVDD_OSC

eMMC

NCT1008CMT3R2G
+3VS_TH

AVDD_USB_PLL

SYSTEM

TPS61050YZGR
LED flash
Boost IC

R445_0_0402

AVDD_USB

1.8V

12V
10mA R390_0_0201

3.3V

OSC

PU9
AMP

AVDD_DSI_CSI
VDDIO_CAM

USB

PU6
OZ9979LN-A3-0-TR
BACK LIGHT
Boost IC

1.2V
1.8V

Title

Power Tree
Size Document Number
Custom
Date:

Rev
1.0

Picasso 2 R04

Tuesday, January 17, 2012

Sheet

24

of

38

SWITCH
+VIN_USB
USB=5V

TPS61030
SYSTEM
Boost-Buck

Charger IC
BQ24171

VIN
AC=12V

+5VS
IC

B+

Battery
1S2P

TPS63020
SYSTEM
Boost-Buck IC

+3VS

G5910
Charge PUMP
Boost IC

+VDD_5V0_SBY

TPS63020
3G
Boost-Buck IC

+V_MINICARD_3V3
C

Oz9979
BACK LIGHT
Boost IC

+VDD_LED_BL

TPS61050
LED flash
Boost IC

LED+

PTPS6591102AA2ZRC
T30 PWR RAIL
PMU IC

T30
CHIP

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

Block Diagram
Size
C
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

25

of

38

SP02000V310
ACES_88231-09001
11
10
9
8
7
6
5
4
3
2
1

BATT+
D

PWR_I2C_SDA

<7,10,14,15,32,34>

CAM_I2C_SDA

<6,17,35>

1
2

1
2

PC11
1

PC1
2200P_0402_50V7K

100_0402_1%
1

@ PR12 0_0402_5%
1
2

<6,17,35>

PC2
0.033U_0402_16V7K

<7,10,14,15,32,34>

CAM_I2C_SCL

0.01UF_0402_25V7K

PR3

PWR_I2C_SCL

@ PR2 0_0402_5%
1
2

PC9
1000P_0402_50V7K

100_0402_1%
2

PR1
1

BATT_TEMP <27>
PC8
33P_0402_50V8J

GND
GND
9
8
7
6
5
4
3
2
1
@ PJP1

Battery I2C reserve CAM_I2C-10/31

VIN

PC7
0.22U_0402_16V7K

PC6
0.22U_0402_16V7K
2
1

1
2

PC4
1000P_0402_50V7K

PC120
0.01UF_0402_25V7K
2
1

PL1
FBMA-L11-160808-301LMA20T
1
2

DC_IN

PC5
1000P_0402_50V7K

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

DC IN/BATT IN
Size
C
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

26

of

38

100K_0402_5%
PR5

SBR3U40P1-7_POWERDI123-2

10

BQ24171_TS

FB

14

BQ24171_FB

PGND

11

TTC
PGND

@ PR34
10K_0201_1%

CHARGER_LED#

STAT

THERMALPAD

PR32
0_0402_5%
2

W_LED_CTL

BATDRV#
2 PR38

100K_0402_1%

O_LED_CTL

CHARGER_STAT

2
1
PR119
100K_0201_1%

CP_GPIO

2
G
SI1034CX-T1-GE3_SC89-6
PQ7A

PQ21B
PQ21A D
5
2
G
G
DMN66D0LDW-7_SOT363-6
SDMN66D0LDW-7_SOT363-6

Orange LED
D

D
PQ7B
S SI1034CX-T1-GE3_SC89-6

5
G

2
2
PR68
1

LED status: (USB)

All LED off

<20>
6

<4>

White LED

VDD_3V3_BQ24171_VREF

<20>

PR37
82.5K_0402_0.1%
2

2
PR1013
51K_0402_1%

PR67
1

Vbat=2.1*(1+R27/R37)

LED status: (AC/Dock station)

No charge : LED off
Fully charged : Static White LED
Charging : Static Orange LED
Charging error : Blink

VDD_3V3_BQ24171_VREF

200K_0402_1%

23

PC32
0.1U_0402_25V6

+3VS

PR132
0_0201_5%
2
1
<5>

BATT_TEMP <26>

25

PC24

22U_0603_6.3V6M

22

2
G

PR35
82K_0402_0.1%

Charging 0-58C
LNJT103F011-20

BQ24171RGYR_VQFN24_3P5X5P5

@ PR36
1
2
10K_0402_5%

38.3K_0402_1%

2
1
2
1

PQ27
SSM3K7002FU_SC70-3

0.01UF_0402_25V7K

OVPSET

TTC_PRECH

PC28
0.1U_0402_16V4Z

@PR27
@
PR27
82K_0402_0.1%

1
BATT_LEARN <6>

PR33
100K_0402_1%

PR1012

3
3

5
G
S
SI1034CX-T1-GE3_SC89-6

PC27
0.1U_0402_16V4Z

PR30
7.68K_0402_1%
1
2

AVCC

18

BQ24171_TTC

S SI1034CX-T1-GE3_SC89-6

@ PR130
0_0201_5%
2
1 DOCK_CP
D

BQ24171_OVPSET

PR93
0_0201_5%
1
2

0_0201_5%

PQ22B

PR29
2.43K_0402_1%

TS

PR1009
0_0402_5%

1
2

JUMP_43X118

BQ24171_AVCC

PD6
BAT54CW_SOT323-3

PR31
768K_0402_1%

PR1331
2
0_0201_5%

## VISET voltage is between 0.12~0.8V ##

PC31
1
2

BQ24171_REGN

20

0.1U_0402_16V4Z

VDD_3V3_BQ24171_VREF

ACSET

REGN

VDD_3V3_BQ24171_VREF
PQ23B
5
G

1
BQ24171_SRN

15

SRN

PC26

BQ24171_SRP

0.047U_0402_25V7K

16

3
0.01_1206_1%

ISET

17

PC22
1
2

1
PC23
22U_0603_6.3V6M

13

2
BQ24171_BTST
PR98
1
2
2.2_0603_5%

21

charger_out

SRP

BATT+
PJ7

PR19

BTST

PL3
1
2
2.2UH_PCME051E-2R2MS_3.3A_20%

BQ24171_SW

24

VREF

1
S

2.39V

RT9818A-36PV_SOT23-3

1U_0402_16V6K
3

PQ28
SSM3K7002FU_SC70-3

PR129
100K_0201_1%
2
1

1
SW

12

PR28
10_0805_1%
1 1
2

BATT+

PC25
0.01UF_0402_25V7K

SW

PC21
1U_0402_6.3V6K

5
G

PR135 49.9K_0402_1%
2
1
PR1010
4.99K_0402_1%

PQ24B
PQ24A
SI1034CX-T1-GE3_SC89-6 SI1034CX-T1-GE3_SC89-6

6
3

PR105
470K_0201_1%
2
1

2
G
CORE_PWR_REQ
VIN

2
ACDRV

BQ24171 internal regulator

P2

CMSRC

GND

Batt OVP :
Batt+ over 4.4V
Back to back will turn off

1
2
2

PR25
73.2K_0402_1%
2

19

SH00000OD00

BQ24171_ACSET
PC30
1U_0603_25V6K
1
2

806K_0402_1%
PR114

VDD
RESET/RESET

B+

SBR3U40P1-7_POWERDI123-2

BQ24171_ISET

PR48 1
2
73.2K_0402_1%

100K_0402_1%

BATDRV#

1
1
2

PR123
57.6K_0402_1%

PD5

PU17
BTB_OFF

ACP

Battery OVP protect

806K_0402_1%
PR62

2
G

4.02K_0402_1%
2

PR127
1M_0201_1%

4.02K_0402_1%
2

PR18
1

PC20

1
PVCC

BATDRV#

PR21

Charge Current setting:

ICHG=VISET/(20*PR352)
<<AC adaptor charge>>
VISET=VREF*[PR26/(PR26+(PR22//PR46))]
=3.3*[11/(11+267//47.5)]= 0.707V
ICHG=0.707/(20*0.01)=3.536A
<<USB charge>>
VISET=VREF*[PR26/(PR26+PR22)]
=3.3*[11/(11 +267)]= 0.131V
ICHG=VISET/(20*0.01)=0.653A

1
2
PR131
1K_0402_1%

PVCC

1
2

6
1

ACN

PC19
10U_0805_25V6K

3
4

1
PR124
2

PU1

PQ6B
DMN66D0LDW-7_SOT363-6

4
1

0.047U_0402_25V7K

PR20 2
1
21K_0402_1%
3

PR23
1
2
100K_0402_1%

PQ6A
DMN66D0LDW-7_SOT363-6

CHARGER_LED#

2.2U_0603_16V6K

BQ24171_ACP

BATT+

PC121

PC16
0.1U_0402_25V6

S SI1034CX-T1-GE3_SC89-6

PR17
1

PC13
0.01UF_0402_25V7K

PD4

SB000005N00

1M_0201_1%

6
1

PQ26A
SI1034CX-T1-GE3_SC89-6

VDD_3V3_BQ24171_VREF

<7,32>

PC17
0.1U_0402_25V6

PC18
1
2

11K_0402_1%
PR26

5
G

PC29
0.1U_0402_25V6
1
2

1 PR24
2
100K_0402_1%

USB500MA

ACIN_12V_OFF

PQ26B
5
G

1@ PR14
2
499K_0402_1%
S SI1034CX-T1-GE3_SC89-6

267K_0402_1%
PR22

2.5V

S SI1034CX-T1-GE3_SC89-6

VBUS_USB

@
1

<7>

2
1

PR40 1DOCK_CP

WAKE_UP_VBUS

10K_0402_1%

0.1U_0402_25V6

PQ23A
2
G

2
1
6

PQ4A
2
G
ENABLE_USB_HOST

PC15
0.01U_0603_50V7K

100K_0402_1%
SI1034CX-T1-GE3_SC89-6
D
PQ4B
DOCK_DET_R#
5 <20>
G
2
G
S

PC12
0.01UF_0402_25V7K

RB751V-40_SOD323-2

BTB_OFF

PR8

BATT+

PC14
1

RB751V-40_SOD323-2

3.3_1206_5%
PR11

VDD_3V3_BQ24171_VREF

PR15
100K_0402_1%

Charge_in

<7>

0.05_1206_1%

Change 0.22U*2 for VBUS_USB issue 10/19

VBUS_USB

PR9
1
2

PR10
100K_0402_1%
1

PC89
2.2U_0402_6.3V6M
2
1

P2
5

1
2
3

PQ3
SI7716ADN-T1-GE3_POWERPAK8-5
1
2
3
5

BQ24171_ACN

PC101
1U_0603_25V6K
1
2

1
2
PR13
10K_0402_5%

PQ2
AON7403L_DFN8-5
1
2
3

1 PR16
2
100K_0402_1%

PQ1
AON7403L_DFN8-5
5

VBUS_USB

4.02K_0402_1%
P3

PQ17
SI7716ADN-T1-GE3_POWERPAK8-5
1
2
5
3

PC125
0.01UF_0402_25V7K

Max Rds(on) 16.5mohm

Max Rds(on) 36mohm

100K_0402_5%
PR6

PD3
VBUS_USB
WAKE_UP_ACIN

PD2
RB751V-40_SOD323-2
1
2

PR136
2

VIN

VDD_1V8_GEN
1

VDD_1V8_GEN

AC Insert or remove --> Wake up T30S

USB Insert or remove --> Wake up T30S
SW to check if Acer USB --> Change charge current to 1A

CHARGER BQ24171

PC118
0.1U_0402_16V4Z

IF=3A VF=0.5V VR=40V

PD1
2

VIN

OVP UVP Range setting:

##OVPSET voltage is between 0.497~1.6V ##
1.6V*(768+100)/100=13.888V
0.497V*(768+100)/100=4.314V
Setting "OVP 13.888V" & "UVP 4.314V"

TTC setting:
High:Disable charge timer,allow termination.
Low:Disable charge termination & timer.
Connect capacitor:Set fast charge timer.

Boot : Static White LED 5sec

Wake up : Static White LED 5sec
Pre-Charge reserved circuit

PD9
2

PC33
0.1U_0402_16V4Z

3
1
USB500MA

6
BSS8402DW_SOT363-6

BQ24171_TTC

6
BSS8402DW_SOT363-6

PR46
BQ24171_ISET 1

47.5K_0402_1%
5

300_0402_1%

@ PQ9
AON7403L_DFN8-5

charger_out

@
PQ5
2SA1037AK_SC59-3~D

BATT+

1
2
3

PU18 @

IN+
VCC+

@
100K_0402_5%
PR7

@ PR41
0_0201_5%
2
1

@ PR61
100K_0402_5%

1
@ PR86

0_0402_5%
PR92

PR75@
100K_0402_5%

0_0402_5%
PR125

BATT+
1

1
S

BAT54CW_SOT323-3
2

3
WAKEUP_LED

PR45
51K_0402_5%

<7>

PQ29B
DMN66D0LDW-7_SOT363-6

PQ29A
DMN66D0LDW-7_SOT363-6

6
1

4.7U_0402_6.3V6M

PC127
2

2.2U_0402_6.3V6M

CP setting:
Idpm=Vacset/(20*PR9)
<<AC adaptor>>
Vacset=3.3*PR25/(PR21+PR25)=1.395V
Iin=Vacset/(20*PR9)=1.395A
<<USB>>
Vacset=3.3*(PR25//PR20)/(PR21+PR25//PR20)=0.463V
Iin=Vacset/(20*PR9)=0.463A
<<Dock-in>>
Vacset=3.3*(PR25//PR23)/(PR21+PR25//PR123)=0.804V
Iin=Vacset/(20*PR9)=0.804A

USB500MA

GND
OUT

IN-

TTC_PRECH
A

LMV331IDCKRG4_SC70-5

BATT+ under 3.3V,

Pre-charge will start

4 1

PQ19

2
G

PR79@
100K_0402_5%
@ PR82
100K_0402_5%
1
2

2
2

PQ18

USB500MA

L: charge in progress
H : charge is complete or in sleep mode
Blink (0.5Hz): fault occur (charge suspend, input over-voltage, timer fault and battery absent)
PR44
10K_0201_1%

PR47
10K_0201_1%

3
1
ACIN_12V_OFF

PR42
402K_0402_1%
2
1
PR43
100K_0402_5%
2
1

2.39V

1M_0402_1%
PR39

SB00000SP00 use BSS8402DW footprint

A

1
D

VDD_3V3_BQ24171_VREF

VDD_3V3_BQ24171_VREF

VIN

WAKEUP_LED 2
G
SI1034CX-T1-GE3_SC89-6
PQ22A

PC126
2

PC124
0.022U_0402_25V7K

PR126
26.1K_0402_1%

VDD_3V3_BQ24171_VREF

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
3

BATT+

Title

Charger
Size
A2

Document Number

Date:

Rev
1.0

Picasso II/M

2005/4/21

Tuesday, January 17, 2012

1

Sheet

27

of

38

63020_B+

@ PR113
1

<32> EN_3V3_SYS

560K_0402_1%
2
1

PC56
@ 0.1U_0402_25V6

1
2

B+

HCB2012KF-121T50_0805
PC35

TPS63020DSJR_QFN14_4X3

PL5
1

PL4
63020_B+

PC113
33P_0402_50V8K

+3VS

1M_0201_1%
2

PC36
10U_0603_6.3V6M

PR53
1

PR52
0_0201_5% @
1
2

14
13
12
11
10
9
8

PR54

PG
PS/SYNC
EN
VIN
VIN
L1
L1

Vfb = 0.5V

1SS355_UMD2-2

VINA
GND
FB
VOUT
VOUT
L2
L2

1
2
3
4
5
6
7

+3VS_FB

15

@ PD11
2

0_0402_5%
1

PU2

10U_0603_6.3V6M

100K_0402_1%

PGND

PC34
0.1U_0402_25V6

PR50

PR49
1

PR51
0_0201_5%

10K_0402_1%

1.5UH_TMPC0412HP-1R5M-Z02_3A_20%

<Vo=3.3 VS> VFB=0.5V

Vo=VFB(1+R12/R14)
3.3=0.5(1+560/100)

22U_0603_6.3V6M

22U_0603_6.3V6M

PC38
1

PC37

Imax=1A

PR55
2.05K_0402_1%

+5VS_FB

Vout = 0.5* (1+PR56/PR55) = 5.158V

PC1007
1000P_0402_25V8J

5.045V
H/W maxloading:2A

16

17

15

VOUT

14

LBO

PADGND

12

VOUT

spec: Ven >0.8*VBAT

FB

GND

PU3

13

PR56
19.1K_0402_1%

FB: 0.5V

VOUT

+5VS

SYNC

SW

LBI

SW

2
1

SYNC High : disable power saving

SYNC low : enable power saving

PGND

Change C_B3 footprint

1

PGND
6

VBAT
8

PGND

2
9
PR58
1
2
0_0402_5%

PR96
1
2
0_0402_5%

PR57
1M_0402_1%

PC41
0.1U_0402_25V6

+
10

PC40
22U_0603_6.3V6M

NC

EN

11

<13,32> EN_5V0_BUCKBOOST

PC39
100U_B3_6.3VM_R45M

VBAT=5V-->Ven>4V

PL6
2.2UH_PCMB041B-2R2MS_2.75A_20%

TPS61030RSAR_QFN16_4X4

PL7

B+

2
PC42

10U_0603_6.3V6M

HCB2012KF-121T50_0805

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

+3.3VALWP/+5VALWP
Size
C
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

28

of

38

B+

VDD_5V0_SBY

PU4

PC43
1
2 G5910_CN

6
7

1U_0603_25V6K

C+
VOUT
VIN
GND
CTP

SHDN

3
2

5
G5910_CP

1
2

G5910_CP

PL8
HCB1608KF-121T30_0603
1
2

G5910-50RBU_TDFN6_2X2
PC45
10U_0603_6.3V6M

PC44
10U_0603_6.3V6M

Imax=110mA
Iocp(min)=250mA

PR59
2

1
1

0_0201_5%

@
PC46
0.1U_0201_6.3V6K

@ PR60
100K_0201_1%

<32,34> EN_5V_CHARGEPUMP

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

+5V_charge_pump
Size
C
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

29

of

38

BATT+
EN_3V3_MODEM

1
PC114 3G@
33P_0402_50V8K
PL9
1

3G@
2

2
1

3G@ PL16
HCB1608KF-121T30_0603
1
2

PC119
1

TPS63020DSJR_QFN14_4X3
2

1U_0402_6.3V6K
3G@

PC1006
1

PG
PS/SYNC
EN
VIN
VIN
L1
L1

@ PR64
0_0201_5%
1
2

10U_0603_6.3V6M

V_MINCARD_3V3

PC48
@ 0.1U_0201_10V6K

PJ8
@ JUMP_43X79
2
1
2
1

PR66
3G@
1
2
560K_0402_1%

VINA
GND
FB
VOUT
VOUT
L2
L2

14
13
12
11
10
9
8

PC49 3G@
10U_0603_6.3V6M
2
1

1SS355_UMD2-2

3G_FB

PR65 3G@
100K_0402_5%

PU5 3G@
1
2
3
4
5
6
7

PGND

0_0402_5%
2
1

15

@ PD10
2

100K_0201_1%

<7,18>

PR85

PC50 3G@
2
1

3G@

10K_0201_1%
PR63
1
2

3G@ PC47
0.1U_0402_25V6

3G@

BATT+

47U_0805_6.3V6M

@ PR89
1

1.5UH_TMPC0412HP-1R5M-Z02_3A_20%

3G@

22U_0603_6.3V6M

22U_0603_6.3V6M

<Vo=3.3 VS> VFB=0.5V

Vo=VFB(1+R12/R14)
3.3=0.5(1+560/100)

PC52
1

PC51

Imax=1A

3G@

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

3G PA(SY8033B/APL5916)
Size
C
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

30

of

38

VISHAY use DII footprint

PL10

1
2
1

<13>

P2@PR112
P2@
PR112
PM@ PR112
93.1K_0201_1% 76.8K_0201_1%

16

17

ISEN1

OVP

18

19

SSTCMP

ISEN3

14

Picasso M: PR112 76.8K

Picasso II : PR112 93.1K
FB2

<13>

FB3

<13>

FB4

<13>

FB5

<13>

OVP :35.05V
OVP :29.35V

OZ9979LN-A3-0-TR_QFN20_4X4

ADIM

ISEN4

12

RT

ISEN5

11

10

ENA

GNDA

LPF

VREF

13

PWM dimming frequency: 6K(TYP)

SYNC

SW

PWM

ISEN2

15

LRT

9979_VREF
PR1007
0_0201_5%
1
2
PR1008
100K_0201_1%
1
2

VIN

PC1004
1U_0402_6.3V6K
1
2

ISET

1
2

PC59
1000P_0201_50V7K
@

9979_EN

DCTRL

0_0201_5%
PR70
2

20

21
PAD

1
2

PU6

PR103
100K_0201_1%
1
2

FB1

PC1005
100P_0201_25V8J

SA000051D00

@PR97
@
PR97
0_0201_5%

PC55
4.7U_0805_50V6K

1
2

9979_OVP
1
0.47U_0402_10V4Z

2
10_0402_1%

PR107
1M_0201_1%

9979_OVP

PR94
0_0201_5%
PC58
0.1U_0402_25V6

PC57
4.7U_0805_50V6K
2
1

1
2
2

2
1
2
PR100 100_0402_1% PC110

PC117
33P_0402_50V8J

PC61
0.01UF_0402_25V7K
2
1

PR69

<4,13> DISPOFF#

+VDD_LED_BL

ISEN6

1
2

PC54
4.7U_0603_6.3V6M

0.1U_0603_25V7K
PC53
2
1

SBR3U40P1-7_POWERDI123-2

+5VS

Use other footprint

PD8
SW

1
2
4.7UH_PCME051E-4R7MS_3A_20%

B+

1
2

@PC62
1000P_0201_50V7K

9979_EN

DCTRL

INVTPWM

100K_0201_1%
PR73

<13>

PR72
24K_0402_1%
1
2
PR99
56K_0201_1%
1
2
PC60
1U_0402_6.3V6K
1
2

TP2
1K_0201_1%
PR71
1
2

PAD

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Deciphered Date

2012/06/20

Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

LED driver
Size
B
Date:

Document Number

Rev
1.0

Picasso II/M
Wednesday, January 18, 2012

Sheet
1

31

of

38

PMU-TPS65911 1/3

OSC32KIN

PMU_OSC32KIN
F8

SDA

1
TP1
PAD

0_0201_5%

M7
M6

PR81

<7> CPU_PWR_REQ

EN1
EN2

GPIO0

VDD_1V8_GEN
GPIO7
GPIO8

PR83
10K_0402_5%

PR84

<7,27> CORE_PWR_REQ

0_0201_5%

F1

SLEEP

GPIO2

<7>

GPIO6

L3

PMU_INT#

POWERHOLD
PR88
1

<7> AP_OVERHEAT#

0_0201_5%
2

HDRST

<20> HDRST

N1

N2

L6

L5

EN_5V_CHARGEPUMP

PR80

<29,34>

L4
TP_PMU_GPIO8

K5

EN_5V0_BUCKBOOST

<13,28>

L2

EN_VDD_SOC

G3

<34>

EN_3V3_SYS

<28>

INT1
GPIO1

TP4
PAD

PR78
1

SCL

M5

M4

0_0201_5%

0_0201_5%

PC64
22P_0402_50V8J

PR76

PC63
22P_0402_50V8J

PR74

<7>

100K_0201_1%

PWR_I2C_SCL
PWR_I2C_SDA

<7>PMU_OSC32KOUT

100K_0201_1%

<7,10,14,15,26,34>
<7,10,14,15,26,34>

PMU_OSC32KIN

F7

VDD_5V0_SBY

VDD_1V8_PMU_VRTC

PMU_OSC32KOUT
OSC32KOUT

EN_5V_CP
Follow ACER circuit 6/22
EN_SOC
EN_3V3_SYS
EN_DDR (Optional on Cardhu S since we are using VDD2 for memory)
EN_5V0

PU7A

GP0:
GP2:
GP6:
GP7:
GP8:

a.
b.
c.
d.
e.

PR77

100K_0201_1%

GPIO3
PWRHOLD
CLK32KOUT

F6
B7
TP5
PAD
F4

PWRDN

PR87

HDRST
NRESPWRON
NRESPWRON2

PMU_CLK_32K <7>
TP7
PAD

33_0402_1%

PR91 0_0201_5%
1
2

H4

PMU_RESET_OUT_1V8#

<7>

C7
TP6 PAD

1@ PR134

VDD_1V8_GEN

100K_0402_5%

D7

VBACKUP

PMU_VBACKUP

H7

TP11
PAD

G6

VDD_1V8_GEN

TP12
PAD

PC65
1U_0402_6.3V6K

GPIO4
GPIO5

VDDIO

N7

B+

B+

B6
1

VCC7

PC66
4.7U_0402_6.3V6M

ONKEY#

PR95 1

2 0_0201_5%

PMU_ONKEY#

E4

PWRON
2

<7,20>

PC67
4.7U_0402_6.3V6M

VDD_1V8_PMU_VRTC
E8

VCCS

PC68
4.7U_0402_6.3V6M

VDD_0V85_PMU_VREF

0 = Hardcode

0.85V

1 = EEPROM
BOOT1

J5

10MIL

G8

REFGND
B8
D6
E6
E5
F5
G4
H6
J3
J4
J6
K3
H5
M8
N8
A1
B1
B2

0.05A

VREF
PMU_BOOT1

0.05A

10MIL

B5

2
PR90
0_0201_5%

Always on

VRTC
PMU_VCCS

PC181
1U_0402_6.3V6K

VDD_1V8_PMU_VRTC

1.8V

PR4 1
2
0_0402_5%

PC69
0.1U_0402_25V6

G7

TESTV
AGND1
AGND2
AGND3
AGND4
AGND5
AGND6
AGND7
AGND8
AGND9
AGND10
AGND11
AGND21
AGND22
DGND1
DGND2
DGND3
PTPS659110A2ZRCR_BGA98

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PMU part1
Size
C
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

32

of

38

PMU-TPS65911 2/3
D

Note: LDO1 & LDO2 need 4.7uF cap according to TI on July 6th

LDO3
LDO4

0.2A

30MIL

VDD_PMU_LDO3
VDD_PMU_LDO4

VDD_PMU_LDO3

3V
0.2A

VDD_PMU_LDO4
PC75

1.2V

PC74

2.2U_0402_6.3V6M

0.1A

2.2U_0402_6.3V6M

PC122
1M_0402_5%

20MIL
1

C8

PC72
1U_0402_6.3V6K

PC71
4.7U_0402_6.3V6M

E7

VCC5

PC73
4.7U_0402_6.3V6M

3V

1
D8

B+

0.5A

VDD_PMU_LDO2

N4

VDD_PMU_LDO1

30MIL

VDD_PMU_LDO2

LDO2

PC70
4.7U_0402_6.3V6M

2.85V

VDD_PMU_LDO1

N6

LDO1

VCC6

N5

+3VS

PU7B

30MIL
L1

B+

VCC4
LDO5

VDD_PMU_LDO5

PC76
4.7U_0402_6.3V6M

2.8V
0.2A

0_0402_5%

0.2A

PC77

N3

VDD_1V8_GEN

VCC3

LDO6

M2

5V

PR110

20MIL

K1

LDO7

PC78
4.7U_0402_6.3V6M

LDO8

2.2U_0402_6.3V6M

10MIL

VDD_PMU_LDO6

M3

VDD_PMU_LDO7

M1

VDD_PMU_LDO8

VDD_PMU_LDO6

10MIL

1.2V
VDD_PMU_LDO7

0.1A

1.2V
VDD_PMU_LDO8

0.05A

1.0V

1
PC81
2.2U_0402_6.3V6M

2.2U_0402_6.3V6M

PC80
2

2.2U_0402_6.3V6M

0.02A
PC79

PTPS659110A2ZRCR_BGA98

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PMU part2
Size
C
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

33

of

38

B+

2
2

0.1U_0402_25V6

F3

SWA1
SWA2
SWA3

VCCA2

D2
D1
E2

GNDSWA1
GNDSWA2
GNDSWA3

VFB1

VCCBB1

SWB1

VCCB2

SWB2

SW
SW

TPS62361_SW1
2
2.2UH_PCMB041B-2R2MS_2.75A_20%

B3
B4

EN

PWR_I2C_SDA

1
1

PWR_I2C_SCL

PR104 0_0201_5%
<7,10,14,15,26,32>
2
2

D2
D3

<7,10,14,15,26,32>
PR106 0_0201_5%

C2
A3
A2

VDD

SENSE+

SDA
SCL

SENSE -

VSEL0
VSEL1
AGND

PGND
PGND
PGND

VDD_1V2_SOC

B1
C1

Close to CPU

D4
C3
C4

Ipeak =2.5A( 6us)

Imax = 1.8A(60us) sustained

TPS62361YZHR_XBGA16

D4

TPS62361B
TPS62361YZHR_XBGA16
2.2UH_VLS252012T-2R2M1R3_1.8A_20%
PL13
1
2

50MIL

H2

1.2V

H1

50MIL
VDD_1V2_MEM

2A

1.2V

PR108
0_0402_5%

GNDSWB2

VFB2

J2

GNDSWB1

50OHM_NETCLASS1

J1

K2

PMU_VFB2

A2

PMU_VBST

PC102
0.1U_0402_25V6

PC91
10U_0603_6.3V6M

2A
1

1
PC87
2

G1

0.1U_0402_25V6

PC90
10U_0603_6.3V6M
2
1

G2

PC88

C2
C1
D3

B+

30MIL

VDD_1V8_GEN

VCCA3

1
PC86
2

10U_0603_6.3V6M
PC108
2
1

F2

VCCA1

D1
0.1U_0402_25V6

E1

B2

<32> EN_VDD_SOC

20MIL

B+

PL11

VIN
AVIN

100K_0201_5%

PU7C

VDD_1V2_SOC

PU8
A4
A1

PR102

PC83
0.1U_0402_25V6

PR101
100K_0201_5%

22U_0603_6.3V6M

<29,32> EN_5V_CHARGEPUMP

22U_0603_6.3V6M
PC112
2
1

PC82
10U_0603_6.3V6M

PMU-TPS65911 3/3

FOR VDD_1V2_CORE_TEGRA

PC100
0.1U_0402_25V6
PC111
2
1

PC84
22U_0603_6.3V6M
2
1
PC85
22U_0603_6.3V6M
2
1

VDD_5V0_SBY
PC92

B+

PR109
2

PMU_DRVH_R
PMU_DRVH_R

Tj<90 degree ==>6.1A

Tj<70 degree ==>5.1A

200MIL

VDD_1V0_GEN

Change C_B3 footprint

G2

1V
FDMC7200_POWER33-8-10
PQ16

PMU_DRVL
PMU_DRVL

1
+

2 @

1
+

8A

2 @

1
+
2

ZZZ
X76376BOL11

PR121
0_0402_5%

PC104
0.1U_0402_25V6

D1

G1

PMU_SW

PL14
2.2UH_MMD-06AE-2R2M-M1L_6A_20%
1
2

A6

5
DRVL

D2/S1
S2

D1

10

S2

PMU_SW

S2

A4

SW

D1

D1

0_0402_5%

PC123
150U_B_6.3VM_R35M

PC109
220U_A_2.5VM_R35M

PMU_DRVH

PC96
220U_A_2.5VM_R35M

DRVH

A3

PC103
0.1U_0402_25V6

2
0.1U_0402_25V6

PC95
10U_0603_6.3V6M

4.5 ~ 6.5V

VBST

V5IN

PC94
10U_0603_6.3V6M
2
1

PC107
0.1U_0402_25V6

1U_0402_16V6K

PC93
2
1

A5

VOUT

B4

PMU_VOUT

X76 control
X76376BOL11: NEC 220U_R35*2
X76376BOL12: NEC 220U_R70*2+Sanyo 100U_R45*1

PC97
VFB

C5

50OHM_NETCLASS1

330P_0402_50V7K
PGOOD
A8
A7

GNDC1

EN

GNDC2

TRAN
TRIP

C4

PMU_PGOOD

PAD

TP8

D5
C6
B3

PMU_TRIP

2
PR111
90.9K_0402_1%

B+

SWIO2

K8

PMU_SWIO

2.2UH_VLS252012T-2R2M1R3_1.8A_20%
PL15
2

50MIL
VDD_1V8_GEN

1.8V

K7

PR122
0_0402_5%

J7

GNDIO1
GNDIO2

J8

PC105
0.1U_0402_25V6

SWIO1
VCCIO2

PC99
10U_0603_6.3V6M

VCCIO1

PC106
0.1U_0402_25V6

L7

10U_0603_6.3V6M

PC98
1

L8
1

2A
A

50OHM_NETCLASS1
VFBIO

H8

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification
PTPS659110A2ZRCR_BGA98

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Title

PMU part3
Size
C
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

34

of

38

0_0402_5%
P2@ PR118
1
2

<7> CAM_LED_EN_NV

B+

1
2
P2@PR128
P2@
PR128
0_0201_5%

<6,17,26> CAM_I2C_SCL

PGND

C2

A3

SDA

ENVM

C3

B1

SW

AGND

D1

B2

SW

LED

D2

AVIN

D3

PR116 P2@
1
2
0_0201_5%
2
1
P2@PL17
P2@
PL17
2.2UH_VLS252012T-2R2M1R3_1.8A_20%

C1

VOUT

B3

SCL

indicator for TPS61050

LED-

<20>

B+

TPS61050YZGR_DSBGA12
P2@
PC116
P2@

<6,17,26> CAM_I2C_SDA

FLASH_SYNC PGND

A2

LED+

A1

10U_0603_6.3V6M

<20>

PU9

PC115
P2@ 10U_0805_25V6K
1
2

PR115
100K_0402_1%

+3VS

@ PR120
1M_0402_1%

1
2
@ PR117
0_0201_5%

<17> CAM_LED_EN

Compal Electronics, Inc.

Compal Secret Data

Security Classification
2011/06/20

Issued Date

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

LED FLASH
Size
A3
Date:

Document Number

Rev
1.0

Picasso II/M
Tuesday, January 17, 2012

Sheet
1

35

of

38

Version change list (P.I.R. List)

Item

Fixed Issue
Ripple un-stable

Reason for change

Rev.

PG#

28
30

01

Loop stable for TPS63020

Modify List

Date

change PL5, PL9 from PCMB041B-2R2MS 2.75A to

PCMB041B-1R5MS 3A,
change
change
change
Remove

PR9 form 0.01_1206_1% to 0.05_1206_1%

PR25 form 10K to 73.2K
PR20 form 3.83K to 21K
ACER USB setting circuit

charger CP setting for adaptor protect

02

26

Net name error

02

35

change net name from VDD_1V8_SYS to VDD_1V8_GEN

Material version change

02

35

change PQ16 from FDMC7200 2N POWER33-8 to FDMC7200S 2N POWER33-8

Use low Vth dual N TR

02

26

change PQ4,PQ6,PQ7,PQ21,PQ21 from DMN66D0LDW-7_SOT363 to SI1034CX

material change for common use

02

26

change PQ18 from BSS8402DW 1P/1N SOT363-6 to SI1553CDL-T1-GE3

1P/1N SC70-6

GPIO only support 1.8V

6
C

No support Acer USB, delete related

control circuit

02

26

Delete PQ19, PR40, PR44, PR47, PR41.

Back-to-back MOS can't

fully turn on

The BATDRV# pull low 1K will cause ACDRV

abnormal

02

26

Change PR16, PR12, PD4 to reserve

Charger will terminate

The TTC pull high 100K will cause wrong

voltage level

02

26

Change PR34 from 100K to 10K

Orange LED can't turn off

STAT pull high 100K can't drive TR

02

26

Change PR36 from 100K to 10Kohm

Modify Battery OVP circuit to avoid AC

turn off when Battery over discharge

02

26

7
8

9
10
11

Pre-charge circuit can't

work normally

13

Sub/B +5VS will drop to

under 4.75V

Modify Pre-charge circuit

02

26

Modify +5VS voltage setting to 5.15V

02

28

14

TPS63020 add 33P on feedback resistor

for loop stable

02

28
30

15

V_MINCARD_3V3 sequence

02

30

16

modify crystal cap

02

32

17

Add LED control circuit for wake up/boot

define

02

26

Add PC118, PR144,PQ23. Delete PD7

Change PR86,PR92,PR93 to PNP 2SA1037K

Change PU3 to TPS61030, PR56 to 19.1K, PR55 to 2.05K

Add PC113, PC114 33P

Change PR65 from 1M_0402_1% to 100K_0402_1%

Add PC1006 1U_0402_6.3V6K

Change PC63, PC64 from 12P_0402_50V8J to 22P_0402_50V8J

Add PQ22 to turn off O_LED

2011/06/20

Issued Date

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Compal Electronics, Inc.

Compal Secret Data

Security Classification

EVT
20110806 (QAJ70)
20110809 DVT
(QAJ50)
20110809 DVT
(QAJ50)
20110809 DVT
(QAJ50)
20110809 DVT
(QAJ50)
20110809 DVT
(QAJ50)
20110809 DVT
(QAJ50)
20110809 DVT
(QAJ50)
DVT
20110809 (QAJ50)
DVT
20110809 (QAJ50)
20110809 DVT
(QAJ50)
DVT
20110816 (QAJ50)
20110824 DVT
(QAJ50)
20110824 DVT
(QAJ50)
20110824 DVT
(QAJ70)
20110825 DVT
(QAJ70)
DVT
20110825 (QAJ70)

12

Phase

Title

PIR
Size Document Number
Custom
Date:

Rev
1.0

Picasso II/M

Tuesday, January 17, 2012

Sheet
1

36

of

38

Version change list (P.I.R. List)

Item

Fixed Issue

Reason for change

Rev.

Add for pre-charge and fast charge timeout

PG#

02

Modify List

27

Date

Phase

DVT
20110826 (QAJ70)

Add PQ19 ,PR44,PR47

BOM control

02

27,31

Modify PD1, PD5, PD8 from SS3P4-M3-84A_SMP2

to SBR3U40P1

footprint control

02

34,35

Modify PL13, PL15, PL17 footprint to

TOKO_1239AS-H-2R2N-P2_2P

Change CP setting for adaptor protect

02

27

Add PQ23

Add VDD_1V0_GEN and VDD_1V8_GEN

Fb resistor for test request

02

34

Add PR121, PR122

EMI request

03

27

Change PL1 to 300ohm bead, add PC120, PR11, PC15,

PC20, PR98, PC1,PC2 for EMI request

Cancel the function

03

27

Delete PR12, PR16, PD4

Reserve the CP control for thermal improve

03

27

Add PR48, PQ24 for reserve

Dock in CP setting

03

27

Add PQ26 PR93 PR96 PR124 PR123 PR40

10

Solve White LED flash issue when AC

plug in

03

27

Add PD4,PC121,PR126,PR127,PQ27

11

Battery OTP change to 55C

03

27

Change PR29 to 2.74K, PR30 to 8.87K

DVT
20110826 (QAJ70)
DVT
20110826 (QAJ70)
DVT
20110826 (QAJ70)
DVT
20110826 (QAJ70)
DVT2
20110920 (QAJ50)
20110920 DVT2
(QAJ50)

20110920 DVT2
(QAJ50)
DVT2
20110920 (QAJ50)
20110920 DVT2
(QAJ50)
20110920 DVT2
(QAJ50)

12

remove pre-charge function

03

13

solve leakage current

03

27,31 Change PD1,PD5,PD8 from SBR3U40 to SS3P4;

14

Thermal over temperature

04

28

PQ1 will turn on when AC plug out

04

26,27

16

OTP change to 58C

04

17

Modify battery OVP to 4.4V

15

VBUS leakage

Reserved PU18, PQ9, PR7, PR61, PR79, PR86, PR41

20111006
20111006

PR62, PR114 to 806K

Change PC39 to 100U_B3_6.3VM_R45

20111027

Change PC6, PC7 to 0.22U. Add PC89 2.2U

20111027

27

Change PR29 to 2.43K, PR30 to 7.68K

20111027

27

Change PR67 to 38.3K

04

2011/06/20

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

27

Compal Electronics, Inc.

Compal Secret Data

Security Classification
Issued Date

20111105

DVT2
(QAJ50)
DVT2
(QAJ50)
DVT2
(QAJ70)
PVT
(QAJ50)
PVT
(QAJ50)
PVT
(QAJ50)

Title

PIR
Size Document Number
Custom
Date:

Rev
1.0

Picasso II/M

Tuesday, January 17, 2012

Sheet
1

37

of

38

Version change list (P.I.R. List)

Item

Fixed Issue

Rev.

PG#

04

27

Add PQ29, PC126, PC127

Don't need the component

04

27

Change PR45 to reserve

Adjust CP setting when power on for

thermal issue

04

27

Add PQ22, PR132, PR135

Battery can't be charged

when dock in

Modify the battery capacity control for

EN_USB_HOST to BATT_LEARN

04

27

Add PR1012, change P135 to 4.99K

T30S WAKE_UP_ACIN damage

Avoid WAKE_UP_ACIN in-rush voltage

04

27

Add PR136, PR131

Modify charge output voltage to improve

battery capacity

04

27

Change PR35 to 82K and PR31 to 82.5K

Turn off charge LED when USB in

1
2

White LED can't light

when power on

3
4
5

Reason for change

Modify List

Date

PVT
20111210 (QAJ50)

7
8

EMMC voltage drop

10

Phase

Avoid white LED will flash 1s when AC/USB

plug in/out

04

27

Change PD4 to reserve, Add PR1013, PR126, PC124

Modify crystal cap value

04

32

Change PC63, PC64 to 22P

PMIC LDO1 compensation

04

33

Change PC72 to

Avoid EMMC external LDO floating

04

33

Add PC122 1M

20111210 PVT
(QAJ50)
PVT
20111210 (QAJ50)
20111210 PVT
(QAJ50)
20111210 PVT
(QAJ50)
20111210 PVT
(QAJ50)
20111210 PVT
(QAJ50)
20111210 PVT
(QAJ50)

20111210 PVT
(QAJ50)
PVT
20111219 (QAJ50)

1U

11
B

12
13
14

15
16
A

17

2011/06/20

Issued Date

Compal Electronics, Inc.

Compal Secret Data

Security Classification

Deciphered Date

2012/06/20

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
5

Title

PIR
Size Document Number
Custom
Date:

Rev
1.0

Picasso II/M

Tuesday, January 17, 2012

Sheet
1

38

of

38

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