J

{
K

K(Data Sheet)

W
AND

KAND K
AND K

K( Truth Table )

AND K
K( Truth Table )

AND

(AND)

LOW

LOW

LOW

LOW

HIGH

LOW

HIGH

LOW

LOW

HIGH

HIGH

HIGH

ANDEJ F
--

EJ F
K

ANDEJ F74LS08

W
SW1,SW2KA, B1, 2 K
KY3 K
K75V14 K

K K

FEJ FAND K
(LOW)"0"{E
K(HIGH)"1"

74LS08ANDEJ

ANDEJ

--

AND
ANDAND
KY=A.B.CEJ F

AND

A.B

AND

Y = A.B.C

ANDEJ F

A.B

ANDEJ F

--

OR

KOR K
OR K

K( Truth Table )

OR K
K( Truth Table )

OR

(OR)

LOW

LOW

LOW

LOW

HIGH

HIGH

HIGH

LOW

HIGH

HIGH

HIGH

HIGH

OREJ F
--

EJ FW
K

OREJ F74LS32W
W
SW1,SW2KA, B1, 2 K
KY3 K
K75V14 K

KSW1, SW2 K

EJ FOR K
(LOW)"0"{EF
K(HIGH)"1"

74LS32OREJ

OREJ
--

OR
OROR

KY=A+B+CEJ F

OREJ F

A+B

OREJ F

--

NOT

{NOT

"1" EF

K"0"

NOT

K( Truth Table )

KNOT

(NOT)

Y

HIGH

LOW
HIGH

LOW

Y=A

KNOTEJ F

--

EJ F
K

NOTEJ F74LS04
W
SW1KA1 K
KY2 K
K75V14 K

K K

FEJ FNOT K
(LOW)"0"{E
(HIGH)."1"

74LS04NOTEJ

0
1

NOTEJ

--

NAND

{NAND K

ANDEFNAND
KAND

NAND K
K( Truth Table )

NAND K
K( Truth Table )

NAND

(NAND)

LOW

LOW

Y

HIGH

LOW

HIGH

HIGH

HIGH

LOW

HIGH

HIGH

HIGH

LOW

Y = AB

Y = AB

NANDEJ F
--

EJ F
K

EJ F74LS00

WNAND
SW1,SW2KA, B1, 2 K
KY3 K
K75V14 K

K K

EJ FNAND K
(LOW)"0"{EF
K(HIGH)"1"

74LS00NANDEJ

NANDEJ
- -

NAND
NANDNAND

Y = A.B.C EJ F

Y = A.B.C

NANDEJ F

Y1 = A B

Y2 = A B = AB

Y = A.B.C

NANDEJ F

- -

NOR

{NOR K

OREFNOR
KOR

NOR K
K( Truth Table )

NOR K
K( Truth Table )

NOR

(NOR)

Y

HIGH

LOW

LOW

LOW

HIGH

LOW

HIGH

LOW

LOW

HIGH

HIGH

LOW

Y = A+B
Y = A+B

NOREJ F

- -

EJ F
K

NOREJ F74LS02

W
SW1,SW2KA, B2, 3 K
KY1 K
K75V14 K

K K

EJ FNOR K
(LOW)"0"{EF
K(HIGH)"1"

74LS02NOREJ

NOREJ
- -

NOR
NORNOR

K Y = A + B + C EJ F

Y = A+B+C

NOREJ F

Y1 = A + B

Y2 = A + B = A + B

Y = A+B+C

NOREJ F

- -

W
XOR&XNOR

{OR{EXORFExclusive-OR K
A, "1"(Y)

K"0"B

KXORXNOR K

KXOR

(XOR)

LOW

LOW

LOW

LOW

HIGH

HIGH

HIGH

LOW

HIGH

HIGH

HIGH

LOW

Y = AB

XOREJ F
- -

EJ F
K

XOR74LS86

AND

K
KY3 K
K75V14 K
K K

SW1,SW2KA, B1, 2

Y = AB

XOREJ

- -

KNANDXOR
EJ FNANDXOR

K Y = A B = A.B + A.B

NANDXOREJ

Y = AB

NANDXOREJ

- -

KXNOR
74LS86XORXNOR
KEJ F{

Y = AB

XNOREJ F

Y = AB

XNOREJ

- -

KEF
K Y = (A + B) (A.B) K

KA, B

OR

Y = (A + B) (A.B)

AND

NAND

W
KA, BOR K

KA, BNAND K

KANDNANDOR K

KEJ FEJ F
A+B

Y = (A + B) (A.B)

AB

Y = (A + B) (A.B) EJ

- -

A+B

AB

EJ FEJ F

- -

EJ F74LS0874LS86
W

74LS0874LS861, 2 K
SW1,SW2KA, BEF

K75V14 K
K K

A
B

S
HA

Y1= Sum

Y2= Carry

KEJ F

- -

EJ F

EJ F74LS0874LS86

EJ F

Cin

SUM

CARRY

KEJ F

- -

Demorgan's Theorems

Demorgan's Theorems

KWAND{
W

A+B=AB

AB = A + B

Y = A+B

Y = AB

Y = AB

KEJ F

ANDEJ F K
K74LS04NOT74LS08

SW1, SW2 K
KEJ F

- -

Y= A B

EJ FEJ F
W

Y = AB

Y = A+B

Y = A+B

KEJ F

OREJ F K
K74LS04NOT74LS32

SW1, SW2 K
KEJ F

- -

Y= A + B

KEJ FEJ F

- -

W
SR

SR(Basic SR Flip-Flop)SR

KD(Clocked SR Flip-Flop)

KNORSR

EJ F74LS02

.SW1,SW2S,R K
K75V14 K

K K

Q
S
Q

Q
R

.NORSREJ F

.NORSREJ F
--

K(Clock)SR

EJ F74LS00
K

Q
S
Q
CK

KSR EJ F

CK

KSR EJ F

--

KD

S, RNOTEJ F

KD

Q
CK

CK

D.EJ F

CK

KD EJ F

CKD

KHIGH

--

JK

KSRJK

KJKMaster Slave

SRJK

KEJ FK
NAND

K74LS00

J
Q
CK

KJKEJ F

JK74LS76

12

11

10

PR

CK
QK

PR

KEJ F

16

Vcc = pin 5
GND = pin 13

15

CK

QK

14

K74LS76JKEJ F
--

CK

KJKEJ F

K
K
{

KEF

WEFrequency DividerF
K
K

K N = 2n {Nn

--

KW

JK

Kn = 4 16 = 2n

JK74LS76

SW2HIGHSW1{EJ F

KHIGHLOW

{HIGH LOWSW1
K

KEJ F

--

23

22

21

20

CLOCK

Y4

Y3

Y2

Y1

=
=
=
=
=
=
=
=
=
=
=
=
=

KEJ F

--

KW

JK

Kn = 4 16 = 2n

JK74LS76

SW2HIGHSW1{EJ F

KEFHIGHLOW

{HIGH LOWSW1
K

KEJ F

--

23

22

21

20

CLOCK

Y4

Y3

Y2

Y1

15

=
=
=
=
=
=
=
=
=
=
=
=
=

KEJ F

--

KW

JK

Kn = 4 16 = 2n

JK74LS76
HIGHSW1{EJ FAND

HIGHLOWSW2

{HIGH LOWSW1
K

KEJ F

--

23

22

21

20

CLOCK

Y4

Y3

Y2

Y1

=
=
=
=
=
=
=
=
=
=
=
=
=

KEJ F

--

Serial In Parallel Out Shift J

{Register

JK74LS76
HIGHLOWSW3{EJ F

SW1EJ F
KSW2

KEJ F

--

Serial
Input
x

Shift
Pulses

Y4

Y3

Y2

Y1

KEJ F

--

(Microcomputer)
WEJ F

Control Bus

~^^
INPUTS

/ _^
CPU

Address Bus

Data Bus

^ ^= ^
ROM

f_k^=
^ ^=
^
RAM

u_^
OUTPTS

EJ F

K
K

KEF
--

Microcomputer

.( -)

POWER

CPU

OUTPUT

RAM

ROM

INPUT

KEJ F

{
K

--

(ADDRESS BUS)80386CPU

K(DATA BUS){

WEJ F
K 9

K 9

??

KK

EJ F

--

READ 9
W

Read Address?
----:----

0000 0000 0000 0000 0010 0000 0000 0000

04000; xx xx xx
xx xx xx xx xx

xx

K04000

WRT 9
K WRT0400704000

--

1111 1111 1101 0000 0000 0000 0000 0000

FFC00

FFC01

FFC02

FFC03

FFC04

FFC05

FFC06

FFC07

--

W
EF

EF
K

KEJ F7489 RAM

A 0 , A 1 , A 2 , A 3

K11110000 2 4 = 16

D 0 , D1 , D 2 , D 3
KZCEF

0000

1111

EJ F

--

7489 RAM74LS04NOT

KEJ F

Data Input

Address Input

ME

WE

EJ F

K0000

K1100

K ME "0"LOW

K WE "0"LOW

--

A 3 , A 2 , A1 , A 0
0000
0101
1100
1101

D 3 , D 2 , D1 , D 0
1100
0011
1010
1110

ME

0
0
0
0

WE

0
0
0
0

K0000

K ME "0"LOW

K WE "1"HIGH
K

A 3 , A 2 , A1 , A 0
0000
0101

D 3 , D 2 , D1 , D 0

1100
1101

ME

WE

0
0

1
1

0
0

1
1

--

EJ F

KEJ F
9
K

READ 9
W

Read Address?
----:----

--

1111 1111 1111 1111 1111 1111 1111 0000

WRT{WRT 9
K

; B0 80 E6
04 CC xx xx xx

FFFFFFF0GO TO 9
KREST

Go to Address?
----:----

--

[1] Nigel P. Cook, Introductory Digital Electronics. New Jersey: Prentice-Hall,

Inc. 1998.
[2] M. Morris Mano, Digital Logic and Computer Design, Prentice- Hall, Inc.
of India - 2000.
[3] Thomas L. Floyd, Digital Fundamentals, Seventh Edition, Prentice-Hall,
Inc. 2000.
[4] M. Morris Mano, Digital Design, Prentice- Hall, Inc. Aug 2001.

- -

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