3/7/2010

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

11Mlocations
1
1
1

StartingAddress=00000
0

EndAddress=FFFFF
1

FFFFF

AddressDecoding

A0 A19

1Mbyte
memory

8088

Memory/IO

D0 D7

CS

CS=ChipSelect.
IfCS=0thenthememorywillbeON
IfCS=1thenthememorywillbesleepingandallitspinswillbeZ

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

StartingAddress=00000
0

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

11Mlocations
1
1
1

StartingAddress=00000
0

EndAddress=FFFFF
0

A19

00000

EndAddress=FFFFF
1

11Mlocations
1
1
1

A19

A19
FFFFF

A0 A19

A0 A18

8088

CS

7FFFF

A0 A19

7FFFF

D0 D7

A0 A18

8088

512KB
memory
D0 D7

FFFFF

00000

CS

7FFFF

512KB
memory
D0 D7

80000
D0 D7
00000

00000

00000

3/7/2010

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

StartingAddress=00000
0

0
0

0
0

0
0

A18

A17

11Mlocations
1
1
1

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

11Mlocations
1
1
1

EndAddress=0FFFF
0

FFFFF
A16 A19

A0 A19

CS

FFFFF

Thismemoryshouldbe
selectedonlywhen

Address
Decoding
A16 A19

8088

A16

StartingAddress=00000

EndAddress=0FFFF
0

A19

FFFF

A16=0
A17=0
A17
=0
A18=0
A19=0

A0 A15
64KB
memory
D0 D7

CS FFFF
A0 A15
64KB

D0 D7

0000

memory

0FFFF
00000

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

StartingAddress=00000
0

A19

A18

A17

A16

A15

00000

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

11Mlocations
1
1
1

EndAddress=0FFFF
1

11Mlocations
1
1
1

FFFFF

Thismemoryshouldbe
selectedonlywhen

A16 A19

0000

StartingAddress=00000

EndAddress=0FFFF
0

0FFFF

D0 D7

A16=1
A17=0
A17
=0
A18=0
A19=0

FFFFF

Thismemoryshouldbe
selectedonlywhen

A16 A19

A16=1
A17=0
A17
=0
A18=0
A19=0

CS FFFF
A0 A15

CS FFFF
1FFFF

A0 A15

20000

64KB

64KB

memory

memory

10000

D0 D7

2FFFF

D0 D7
0000

00000

0000

00000

3/7/2010

A19

A18

A17

A16

A15

A14

A13

A12

A11

A10

A9

A8

A7

A6

A5

A4

A3

A2

A1

A0

11Mlocations
1
1
1

StartingAddress=00000
0

ConnectionsBetweenCPUandMemory

EndAddress=0FFFF
0

Thismemoryshouldbe
selectedonlywhen

A16 A19

Controlsignals

FFFFF
8088

A16=1
A17=0
A17
=0
A18=0
A19=0

Memory
DataBus
Addressbus

3FFFF

Whatarethecontrolsignalsfromthemicroprocessortomemory?
Whatarethecontrolsignalfrommemorytothemicroprocessor?

30000

Addressanddatasignalsshouldbebuffered

CS FFFF

Theuseofbuffersonaddressbusincreasesdrivingcapability
Bidirectionalbuffersareusedtocontrolthedatatransferringdirections
ondatabus
DlatchesareusedtodemultiplexsignalsonAD[7:0](andA[19:16])

A0 A15
64KB
memory

D0 D7
0000

00000

510

MemoryChips

TimingDiagramofAMemoryOperation
Example: 8088sendsaddress70C12tomemoryinamemoryreadoperation
assumethatdata30Hisread
T2

T1

AD[7:0]

7H

A[15:8]

Memory

Dlatch

AD[7:0]

Thenumberofaddresspinsisrelatedtothenumberofmemory
locations .

Thedatapinsaretypicallybidirectional inreadwritememories.

Commonsizestodayare1K to256M locations. (10and28addresspins

arepresent.)

ALE
A[19:16]

Buffer

T4

CLK

Addr[15:0]
Dlatch

8088 A[15:8]

T3

Thenumberofdatapinsisrelatedtothesizeofthememorylocation .
Forexample,an8bitwide(bytewide)memorydevicehas8 datapins.
Cataloglistingof1KX8indicateabyteaddressable8K
C t l li ti
f 1K X 8 i di t b t dd
bl 8K memory.

S3S6
0CH

12H

30H

D[7:0]
DT/R
DEN
IO/M
WR
RD

Trans
ceiver

Eachmemorydevicehasatleastonechipselect ( CS )orchipenable (
CE )orselect ( S )pinthatenablesthememorydevice.
Eachmemorydevicehasatleastonecontrolpin.

Addr[19:16]

7H

Addr[15:8]

0CH

ForROMs,anoutputenable ( OE )orgate ( G )ispresent.

Addr[7:0]

12H

ForRAMs,areadwrite ( R/W )orwriteenable ( WE )andreadenable

(OE )arepresent.

D[7:0]

TheOE pinenablesanddisablesasetoftristatebuffers.
30H

Fordualcontrolpindevices,itmustbeholdtruethatbotharenot0atthe
sametime.
511

512

3/7/2010

MemoryAddressDecoding

MemoryAddressDecoding
Theprocessorcanusuallyaddressamemoryspacethatis
muchlarger thanthememoryspacecoveredbyanindividual
memorychip.
Inordertospliceamemorydeviceintotheaddressspaceof
theprocessor,decodingisnecessary.
Forexample,the8088issues20bitaddressesforatotalof
1MBofmemoryaddressspace.
However,theBIOSona2716EPROMhasonly2KBofmemory
and11 addresspins.
Adecodercanbeusedtodecodetheadditional9addresspins
andallowtheEPROMtobeplacedinany 2KBsectionofthe
1MBaddressspace.
513

514

MemoryAddressDecoding

DecodingCircuits

UsingFullmemoryaddressingspace

NANDgatedecodersarenotoftenused.
3to8LineDecoder(74LS138)ismorecommon.

Addr[19:0]
FFFFF
Highestaddress

00110111111111111111

Lowestaddress

00110000000000000000

37FFF
32KB
30000
These5addresslines
arenotchanged.They
setthebaseaddress

00000

Addr[14:0]
Addr[19]
Addr[18]
Addr[17]
Addr[16]
Addr[15]
515

IO/M

These15addresslinesselect
oneofthe215 (32768)locations
insidetheRAMs

32KB
CS

Canwedesignadecodersuchthatthefirstaddress
ofthe32KBmemoryis37124H?
516

3/7/2010

MemoryMap
Fulladdress
decoding

Alltheaddresslinesusedbythedecoderormemorychip=>
eachbyteisuniquelyaddressed=fulladdressdecoding
A14
A15
A16
A17
A18
A19
A14
A15
A16

A19=A18=...=A14=1
selecttheEPROM
A16,A15,A14select
oneEPROMchip
A19=1,A18=0,A17=0
activatethedecoder

A17
A18
A19

A0
... 256KB
A17 RAM
CS1 chip

CS2
A0A13
A0A13

A
B
C

7
6
5
74LS138 4
3
E1
2
E2
1
E
0

16KB
EPROM
chip
OE

FFFFF
FC000

Designa1MBmemorysystemconsistingofmultiplememorychips
Solution1:

CS10
CS9
16KB
CS8
16KB
16KB
16KB
CS7 EPROM
16KB
EPROM
16KB
16KB
EPROM
16KB
EPROM
CS6
chip
EPROM
chip
EPROM
EPROM
chip
CS5
EPROM
chip
p
chip
chip
chip
CS4
chip
hi
CS3
OE

9FFFF
9C000
83FFF
80000
220 =
1,048,576
different
byte
addresses
=1Mbyte
3FFFF

MRDC
ThesameMemorymap
assignment
A0
A19
MWTC
A256Kbyte=218 RAMchiphas ... 256KB
18addresslines,A0 A17
MRDC
A17 RAM
chip
A18
A19,A18assignedto00=>
CS1 WRRD
A19
00000
A18=0
CSactiveforeveryaddress
WR
IO/M
A19=0
8088MemoryMap
from00000to3FFFF
RD
IO/M=0
IO/M=0=>Memorymap
CS 1 A19 A18 IO / M A19 A18 IO / M
A18

MemoryAddressDecoding

256KB
CS

256KB

256KB

CS

CS

256KB
CS

Addr[17:0]
Addr[18]

2to4
decoder

Addr[19]
CS
IO/M

518

MemoryAddressDecoding

MemoryAddressDecoding

Designa1MBmemorysystemconsistingofmultiplememorychips

Designa1MBmemorysystemconsistingofmultiplememorychips

Solution2:

Solution3:

256KB
CS

256KB
CS

256KB
CS

256KB

256KB

Addr[19:2]
Addr[1]

CS

Addr[19:18]
Addr[16:7]
Addr[5:0]

CS

Addr[17]
2to4
decoder

256KB

256KB

CS

CS

256KB
CS

2to4
decoder

Addr[6]

Addr[0]

CS

CS
IO/M

IO/M

519

Itisabaddesign,butstillworks!

520

3/7/2010

MemoryAddressDecoding

MemoryAddressDecoding

Designa1MBmemorysystemconsistingofmultiplememorychips

ExerciseProblem:
A64KBmemorychipisusedtobuildamemorysystemwiththestartingaddressof

Solution4:

7000H.Ablockofmemorylocationsinthememorychiparedamaged.

256KB

256KB

CS

512KB

CS

CS

FFFFH

7FFFFH

3317H

73317H

3210H

73210H

0000H

70000H

733FFH

Addr[17:0]

Addr[18]

Addr[18]
Addr[19]
IO/M

Replacethisblock
73200H

64KB
Addr[19]

Addr[18]
Addr[19]
IO/M

Damagedblock
IO/M

1Maddressingspace

1Maddressingspace

521

MemoryAddressDecoding

522

MemoryAddressDecoding
ExerciseProblem:
A2MBmemorychipwithadamagedblock(from0DCF12Hto103745H)isusedto

A[19]
A[18]
A[17]
A[16]
IO/M

builda1MBmemorysystemforan8088basedcomputer

64KB

A[15:0]

1FFFFFH

1FFFFFH
512K

CS
103745H

Usethese
Use
these
two
blocks

0FFFFFH
0DCF12H
A[15]
A[14]
A[13]
A[12]
A[11]

A[8:0]

512B

07FFFFH
512K

000000H

180000H

000000H

Damagedblock

CS
A[19]

A[10]
A[9]

A[19:0]

A[20]
A[19:0]
CS

523

524

3/7/2010

MemoryAddressDecoding

MemoryAddressDecoding

Partialdecoding

Implementationofpartialdecoding

Example:
builda32KBmemorysystembyusingfour8KBmemorychips
Thestartingaddressofthe32KBmemorysystemis30000H
00110111111111111111
0011 0 11 0 0000 0000 0000
00110110000000000000
Chip#4
Chip#3
Chip#2
Chip#1

36000H
34000H
32000H
30000H

8KB

8KB

CS

highaddr.ofchip#4

Addr[12:0]

Low addr of chip #4

Lowaddr.ofchip#4

Addr[13]
[ ]

8KB

CS

8KB

CS

CS

2 to 4
2to4
decoder

Addr[14]

00110101111111111111
00110100000000000000

Lowaddr.ofchip#3

00110011111111111111
00110010000000000000

Lowaddr.ofchip#2

00110001111111111111
00110000000000000000

Lowaddr.ofchip#1

highaddr.ofchip#3

highaddr.ofchip#2

highaddr.ofchip#1

IO/M

Withtheabovedecodingscheme,whathappensiftheprocessoraccesseslocation
02117H,32117H,and9A117H?
Iftwo16KBmemorychipsareusedtoimplementthe32KBmemorysystem,what
isthepartialdecodingcircuit?
Whataretheadvantageanddisadvantageofpartialdecodingcircuits?

525

Someaddresslinesnot usedbythedecoderormemory
chip=>mirrorimages=partialaddressdecoding

MemoryMap
Partialaddress
decoding
A18=...=A14=1
selecttheEPROM
A16,A15,A14select
oneEPROMchip
A19=1,A17=0
activatethedecoder
A0
...
A15

64KB
RAM
CS1 chip

526

A14
A15
A16
A17
A18
A14
A15
A16
A17
A19

CS2
A0A13
A0A13

A
B
C

7
6
5
74LS138 4
3
E1
2
E2
1
E
0

16KB
EPROM
chip
OE

CS10
CS9
16KB
CS8
16KB
16KB
16KB
CS7 EPROM
16KB
EPROM
16KB
16KB
EPROM
16KB
EPROM
CS6
chip
EPROM
chip
EPROM
EPROM
chip
CS5
EPROM
chip
p
chip
chip
chip
CS4
chip
hi
CS3
OE

GeneratingWaitStates

FFFFF mirror
FC000 image
DFFFF
DC000

mirror
CF000 image
CC000

9FFFF
9C000 base
83FFF image
80000
7FFFF base
7C000 image

MRDC
ThesameMemorymap
A18
assignment
3FFFF
A0
A19
30000
64KB
MWTC
A64Kbyte=216 RAMchiphas
2FFFF mirror
...
20000 images
RAM
16addresslines,A0 A15
MRDC
A15
1FFFF
chip
10000
A18
0FFFF base
A19,A18assignedto00=>
CS1 WRRD
A19
00000 image
A18=0
CSactiveforeveryaddress
WR
A19=0 IO/M
8088MemoryMap
from00000to3FFFF
RD
IO/M=0
A16,A17notused=>fourimagesforthesamechip
IO/M=0=>Memorymap

Waitstatesareinsertedintomemoryreadorwritecyclesifslowmemories
areusedincomputersystems
Readysignalisusedtoindicateifwaitstatesareneeded
data
Address

memory

8088
Delay
circuit

decoder
Ready

clr

clr
D

Ready

clk
528

3/7/2010

GeneratingWaitStates(Timing)

clr
Q

clr
D

Ready

clk
529