;9DEC07 jammer022.

asm
;DEVICE = 16F628A
;Jammerdan - aka Silencer. Control a LMX2306 PLL and VCO to jam FM broadcasts. T
unes to 107.9 MHz then steps down to 87.5 MHz.
;3DEC07 Interrupts (TIMER0)
;6DEC07 Step Downto 87.5, Blinkenlichten, accurate step length (100 ms),
;9DEC07 Fixed PORTA Init (CMCON)
;9DEC07 Pilot Freq -> 3.4 kHz
;This version tests the IN3KC detector, stays on 107.9
LIST
P=16F628a, F=INHX8M
#include <p16f628a.inc>
__CONFIG 0x2021
; XT OSC, RA5-MCLR
; Equates
RESET_V
OSC_FREQ

EQU
EQU

; Registers
PLLHI
EQU
PLLLO
EQU
Word. Max value 0x07.
GPCTR
EQU
DATABYTE
EQU
(gets destroyed)
TEMPW
EQU
TEMPST
EQU
BITBCKT
EQU
LSTNCNT
EQU
#define
#2)
#define
#define
#define
#define
#define
#define
#define
#define
#define

0x00
D'4000000'

; Address of RESET Vector

; Oscillator Frequency is 4 MHz

0x20
; MSB of PLL N-Divider Word
0x21
; LSB (Swallow Counter) of PLL N-Divider
Must be left-shifted before outputting.
0x22
; General Purpose Counter
0x23
; Databyte to be output on the dataline
0x24
0x25
0x26
0x27

;
;
;
;

Temp W Storage (@ INT)

Temp STATUS Storage (@ INT)
Need storage for some bits
Listen Counter

IN3KC

PORTA,3

; Pilot Tone (Listen) Input (Pin

OUT3KC
PLL_CLK
PLL_DATA
PLL_LE
RUN3
RUN2
RUN1
LOCK
LSTNBIT

PORTB,7
PORTB,6
PORTB,5
PORTB,4
PORTB,3
PORTB,2
PORTB,1
PORTB,0
BITBCKT,3

;
;
;
;
;
;
;
;
;

Pilot Tone Output (Pin#13)

Pin #11 on LMX2306
Pin #12
Pin #13 on LMX2306
Lightshow #3
Lightshow #2
Lightshow #1
LOCK LED (Green)
Listen Bit

;**************************************************************
; Begin Program
;**************************************************************

RESET
INT

ORG

RESET_V

; RESET vector location

GOTO
ORG
GOTO

START
4
INT_HANDLER

; INT vector

;**************************************************************
; Initialization Routine
;**************************************************************
START
CLRF

STATUS

; POWER_ON Reset (Beginning of program)

; Do initialization, Select bank 0

CLRF
BSF
CLRF

INTCON
INTCON,GIE
PCLATH

MOVLW
MOVWF
BSF
MOVLW
MOVWF
CLRF
MOVLW
MOVWF
BCF

0x07
CMCON
STATUS,RP0
0xFF
TRISA
TRISB
0x88
OPTION_REG
STATUS,RP0

; Turn comparators off and

; enable pins for I/O
; Select bank 1

CLRF
BSF
GOTO

PORTB
OUT3KC
MAIN

; Make all PORT B outputs low

; Except PORTB,7

; Enable GIE
; Keep in lower 2KByte

;
;
;
;
;

RA7-0 Inputs
RB7-0 Outputs
PSA -> WDT hence prescaler 1:1
Select bank 0

;**************************************************************
; Subroutines
;**************************************************************
PLL_INIT
0011

; Initialization Word: 00000000001001010

BSF
PLL_LE
BCF
PLL_LE
MOVLW 0x0A
MOVWF GPCTR
CALL
OUT_ZEROES
MOVLW 0x94
MOVWF DATABYTE
CALL
OUT_BYTE
CALL
OUT_ZERO
CALL
OUT_ONE
CALL
OUT_ONE
BSF
PLL_LE
BCF
PLL_LE
MOVLW 0x0D
rd: 000000000000010100000
MOVWF GPCTR
ency of 100 kHz
CALL
OUT_ZEROES
MOVLW 0xA0
MOVWF DATABYTE
CALL
OUT_BYTE
BSF
PLL_LE
BCF
PLL_LE
RETURN
PLL_TUNE
nd PLLLO

; Latch Data. This may be unnecessary

; Output Ten Zeroes F19:F10
; Output 10010100
;
;
;
;
;

F9:F2
F1
C2
C1
Latch Data

; Output 13 Zeroes, Reference Divider Wo

; yields divide by 40 giving a PLL frequ
; Output 10100000
; C2 & C1 are both zero
; Latch Data

; Loads PLL with the contents of PLLHI a

CALL
MOVLW
MOVWF
CALL
MOVFW
MOVWF
CALL

OUT_ZERO
0x05
GPCTR
OUT_ZEROES
PLLHI
DATABYTE
OUT_BYTE

; Clear GO bit
; Output Five Zeroes N18:N14
; Get the N-Counter N13:N6 bits
; Load into DATABYTE

CALL
CALL
MOVFW

OUT_ZERO
OUT_ZERO
PLLLO

; N5
; N4
; Get the swallow counter: N3:1 (Note: o

MOVWF
CALL
CALL
CALL
BSF
BCF
RETURN

DATABYTE
OUT_PLLLO
OUT_ZERO
OUT_ONE
PLL_LE
PLL_LE

; Load into DATABYTE

ffset by 1!)
; C2
; C1
; Latch Data

OUT_ZERO
BCF
PLL_DATA
BSF
PLL_CLK
BCF
PLL_CLK
RETURN
OUT_ZEROES
th the number

; Output string of zeroes, load GPCTR wi

CALL
OUT_ZERO
DECFSZ GPCTR,1
GOTO
OUT_ZEROES
RETURN

; Test if all zeroes have been output

; No, still one or more to go
; Yes, done

OUT_ONE
BSF
PLL_DATA
BSF
PLL_CLK
BCF
PLL_CLK
RETURN
OUT_BYTE

; Output a byte, which sits in DATABYTE

MOVLW
MOVWF

0x08
GPCTR

RLF
BTFSC
CALL
BTFSS
CALL
DECFSZ
GOTO
RETURN

DATABYTE,1
STATUS,C
OUT_ONE
STATUS,C
OUT_ZERO
GPCTR,1
OUT_BYTE1

OUT_BYTE1

OUT_PLLLO
the swallow counter
DECF
)
SWAPF
RLF
MOVLW
MOVWF
GOTO
RETURN
in case

;
;
;
;
;
;

Leftrotate into Carry

Test Carry
Carry was set, output a 1
Test Carry Again
Carry was cleared, output a 0
Test if eight bits have been output

; Only used to output the three bits for

DATABYTE,1

; Compensate for zero test in MAIN (ugly

DATABYTE,1
DATABYTE,1
0x03
GPCTR
OUT_BYTE1

; Prepare DATABYTE for output

; Shift five bits to the left

SCREAM
tshow and detector (LISTEN)
BSF
INTCON,T0IE
MOVLW 0x35

; Bad programming. Redundant RETURN just

; 100 ms delay, 3.4 kHz modulation, ligh
; Enable Timer0 Interrupt
; Main Counter

MOVWF

GPCTR

MOVLW
MOVWF

0xFF
DATABYTE

DECFSZ
GOTO
DECFSZ
GOTO
BTFSC
GOTO
BTFSC
GOTO
BCF
BSF
GOTO

DATABYTE,1
LOOP1
GPCTR,1
LOOP
RUN1
RUN_2
RUN2
RUN_3
RUN3
RUN1
LISTEN

;
;
;
;
;
;
;
;
;

BCF
BSF
GOTO

RUN1
RUN2
LISTEN

; RUN1 Must Be On
; Turn RUN2 On
; Exit

BCF
BSF

RUN2
RUN3

BCF
BSF
CLRF
MOVLW
MOVWF

INTCON,T0IE
OUT3KC
LSTNCNT
0x1F
DATABYTE

;
;
;
;
;

Disable Timer0 Interrupt

Preload VCO Modulator
Clear Listen Counter
Test 32 cycles
Another Unauthorized use of DATABYTE a

BCF
MOVFW
ANDLW
BSF
XORWF
GOTO

LOCK
PORTA
B'00001000'
LSTNBIT
BITBCKT,1
LISTEN2

;
;
;
;

Read IN3KC
Mask IN3KC (PORTA,3)
Set Listen Bit
Store in Listen Bit, Inverted!

MOVFW
ANDLW

PORTA
B'00001000'

; This part must last exactly 147 us!

; Read IN3KC
; Mask IN3KC (PORTA,3)

XORWF
ANDLW
BTFSS
INCF

BITBCKT,0
B'00001000'
STATUS,Z
LSTNCNT,1

;
;
;
;

MOVLW
XORWF
MOVLW
XORWF
MOVLW
MOVWF

B'00001000'
BITBCKT,1
B'10000000'
PORTB,1
0x2C
GPCTR

DECFSZ
GOTO
DECFSZ
GOTO
MOVLW
SUBWF
BTFSC

GPCTR,1
LOOP3
DATABYTE,1
LISTEN1
0x11
LSTNCNT,0
STATUS,C

LOOP
; Unauthorized use of DATABYTE as an Inn

er Counter...
LOOP1
Inner Counter Zero?
No
Main Counter Zero?
No
Is RUN1 On?
Yes
Is RUN2 On?
Yes
No, RUN3 Must Be On

; Exit

RUN_2

RUN_3
LISTEN

s a Counter...

LISTEN1
LISTEN2

XOR LSTNBIT With IN3KC

Mask LSTNBIT (BITBCKT,3)
Is Zero Bit Set? Was there NO change?
No, Increase Listen Counter, there _wa

s_ a change
; Toggle LSTNBIT
; Toggle PORTB,7 (OUT3KC)
; Use the GP Counter for...

LOOP3
; 147 us delay

; Test if CARRY is Set

BSF
LOCK
RETURN

; Yes, enough cycles detected

;**************************************************************
; Interrupt Routines
;**************************************************************
INT_HANDLER
MOVWF TEMPW
; Copy W to a Temporary Register
; regardless of current bank
SWAPF STATUS,W
; Swap STATUS nibbles and place
; into W register
MOVWF TEMPST
; Save STATUS to a Temporary register
; in Bank0
; Push Complete
MOVLW 0x79
; Load TMR0, preset for 3.4 kHz (147 us
period)
MOVWF TMR0
BTFSS INTCON,T0IF
; Timer0 Flag Set?
GOTO
OTHER_INT
; No
BCF
INTCON,T0IF
; Clear Source of Interrupt
MOVLW B'10000000'
XORWF PORTB,1
; Toggle OUT3KC
OTHER_INT
SWAPF

TEMPST,W

MOVWF

STATUS

SWAPF

TEMPW,F

SWAPF

TEMPW,W

BSF
INTCON,GIE
RETFIE

;
;
;
;
;
;
;
;
;
;

Swap original STATUS register value

into W (restores original bank)
Restore STATUS register from
W register
Swap W_Temp nibbles and return
value to W_Temp
Swap W_Temp to W to restore original
W value without affecting STATUS
Pop Complete
Re-enable GIE

;**************************************************************
; Main Routine
;**************************************************************
MAIN
CALL

PLL_INIT

MOVLW
MOVWF
MOVLW
MOVWF
CALL
CALL
GOTO

0x86
PLLHI
0x08
PLLLO
PLL_TUNE
SCREAM
FREQSTART

CALL
CALL
BCF
DECFSZ
GOTO
MOVLW
MOVWF

PLL_TUNE
SCREAM
INTCON,T0IE
PLLLO,1
FREQSET
0x08
PLLLO

FREQSTART
; Divider set to 1079
; Ensure PLL is tuned properly
;TEST Stay on 107.9 MHz

FREQSET
; Disable Timer0 Interrupt
; Not yet zero, continue scanning down
; Reset swallow counter to 7+1

DECF
MOVLW
SUBWF

PLLHI,1
0x6D
PLLHI,0

BTFSS
GOTO
CALL
CALL
DECF
CALL
CALL
DECF
CALL
CALL
DECF
CALL
CALL
DECF
CALL
CALL
GOTO

STATUS,Z
FREQSET
PLL_TUNE
SCREAM
PLLLO,1
PLL_TUNE
SCREAM
PLLLO,1
PLL_TUNE
SCREAM
PLLLO,1
PLL_TUNE
SCREAM
PLLLO,1
PLL_TUNE
SCREAM
FREQSTART

; Test for Zero bit in STATUS

; Continue scanning down
; 87.9 MHz

NOP
GOTO

STOP

; Loop Forever

; Divider set to 880?

; Test value of PLLHI, result goes to WR

EG

; 87.8 MHz
; 87.7 MHz
; 87.6 MHz
; 87.5 MHz
; Start new scan

STOP

END