Asembly

Bi 1 - Lm quen AVR
5
( 388 Votes )
Ni dung
Cc bi cn tham kho trc
1.
Gii thiu.
2.
Cng c.
AVR Studio.
3.
V d.
M phng vi Proteus.
4.
M phng.
Download v d
I. Gii thiu
AVR l mt h vi iu khin do hng Atmel sn xut (Atmel cng l nh sn
xut dng vi iu khin 89C51 m c th bn tng nghe n). AVR l chip vi
iu khin 8 bits vi cu trc tp lnh n gin ha-RISC(Reduced Instruction Set
Computer), mt kiu cu trc ang th hin u th trong cc b x l.
Ti sao AVR: so vi cc chip vi iu khin 8 bits khc, AVR c nhiu c tnh
hn hn, hn c trong tnh ng dng (d s dng) v c bit l v chc nng:
Gn nh chng ta khng cn mc thm bt k linh kin ph no khi s dng

AVR, thm ch khng cn ngun to xung clock cho chip (thng l cc khi thch
anh).
Thit b lp trnh (mch np) cho AVR rt n gin, c loi mch np ch

cn vi in tr l c th lm c. mt s AVR cn h tr lp trnh on chip bng
bootloader khng cn mch np
Bn cnh lp trnh bng ASM, cu trc AVR c thit k tng thch C.
Ngun ti nguyn v source code, ti liu, application notert ln trn

internet.
Hu ht cc chip AVR c nhng tnh nng (features) sau:
C th s dng xung clock ln n 16MHz, hoc s dng xung

clock ni ln n 8 MHz (sai s 3%)
B nh chng trnh Flash c th lp trnh li rt nhiu ln v dung
lng ln, c SRAM (Ram tnh) ln, v c bit c b nh lu tr lp
trnh c EEPROM.
Nhiu ng vo ra (I/O PORT) 2 hng (bi-directional).
8 bits, 16 bits timer/counter tch hp PWM.
Cc b chuyn i Analog Digital phn gii 10 bits, nhiu knh.
Chc nng Analog comparator.

Giao din ni tip USART (tng thch chun ni tip RS-232).
Giao din ni tip Two Wire Serial (tng thch chun I2C)
Master v Slaver.
Giao din ni tip Serial Peripheral Interface (SPI)
...
Mt s chip AVR thng dng:
AT90S1200
AT90S2313
AT90S2323 and AT90S2343
AT90S2333 and AT90S4433
AT90S4414 and AT90S8515
AT90S4434 and AT90S8535
AT90C8534
ATtiny10, ATtiny11 and ATtiny12
ATtiny15
ATtiny22
ATtiny26
ATtiny28
ATmega8/8515/8535
ATmega16
ATmega161
ATmega162
ATmega163
ATmega169
ATmega32
ATmega323
ATmega103
ATmega64/128/2560/2561
AT86RF401.
....
Trong bi vit ny ti s dng chip ATmega8 lm v d, ti chn ATmega8
v y l loi chip thuc dng AVR mi nht, n c y cc tnh nng ca AVR
nhng li nh gn (gi PDIP c 28 chn) v low cost nn cc bn c th mua t

mnh to ng dng.
Ti sao Assembly (ASM): bn c th khng cn bit v cu trc ca AVR vn
c th lp trnh cho AVR bng cc phn mm h tr ngn ng cp cao nh
BascomAVR (Basic) hay CodevisionAVR (C), tuy nhin khng phi l mc
ch ca bi vit ny. hiu thu o v AVR bn phi lp trnh bng chnh ngn
ng ca n, ASM. Nh vy lp trnh bng ASM gip bn hiu tng tn v AVR,
v tt nhin lp trnh c bng ASM bn phi hiu v cu trc AVR.Mt l
do khc bn m ti khuyn bn nn lp trnh bng ASM l cc trnh dch
(compiler) ASM cho AVR l hon ton min ph, v ngun source code cho AVR
vit bng ASM l rt ln. Tuy nhin mt khi bn thnh tho AVR v ASM bn
c th s dng cc ngn ng cp cao nh C vit ng dng v u im ca ngn
ng cp cao l gip bn d dng thc hin cc php ton i s 16 hay 32 bit (vn
l vn kh khn khi lp trnh bng ASM).
II. Cng c.
Trnh bin dch: c rt nhiu trnh bin dch bn c th s dng bin dch
code ca bn thnh file intel hex np vo chip, mt s trnh dch quen thuc c
th k n nh sau:
AvrStudio: l trnh bin dch ASM chnh thc cung cp bi Atmel, y l

trnh bin dch hon ton min ph v tt nhin l tt nht cho lp trnh AVR bng
ASM. Phin bn hin ti l 4.18 SP1, bn c th download phn mm AvrStudio
ti trang web chnh thc ca Atmel hoc bn 4.623 ti y.
Wavrasm: cng c cung cp bi Atmel, n chnh l tin thn ca

AvrStudio. Hin ti wavrasm khng cn c s dng nhiu v so vi AvrStudio
trnh bin dch ny c nhiu hng ch, nu bn quan tm c th download ti y.
WinAVR hay avr-gcc: l b trnh dch c pht trin bi gnu, ngn ng s

dng l C v c th c dng tch hp vi AvrStudio (dng Avrstudio lm trnh
bin tp editor). c bit b bin dch ny cng min ph v a s ngun source
code C c vit bng b ny, v vy n rt l tng cho bn khi vit cc ng dng

chuyn nghip. Vic lp trnh bng avrgcc ti s cp trong nhng phn sau.
CodeVisionAvr: mt chng trnh bng ngn ng C rt hay cho AVR, h tr

nhiu th vin lp trnh. Tuy nhin l chng trnh thng mi. Bn c th
download bn demo (y chc nng nhng nhng gii hn dung lng b nh
chng trnh 2KB) ti Website hpinfotech
ICCAVR: lp trnh C cho avr, download bn demo.
BascomAVR: lp trnh cho AVR bng basic, y l trnh bin dch kh hay
v d s dng, h tr rt nhiu th vin. Tuy nhin rt kh debug li v khng
thch hp cho vic tm hiu AVR. V vy ti khng bn khuyn khch bn s dng
trnh dch ny. Bn c th download bn demo (4K limit).
V cn rt nhiu trnh bin dch khc cho AVR m ti khng k ra y, nhn

chung tt c cc trnh bin dch ny h tr C hoc Basic hoc thm ch Pascal. Vic
chn 1 trnh bin dch ty thuc vo mc ch, vo mc ng dng, vo kinh
nghim s dng v nhiu l do khc na. V d ti thng dng Avrstudio v
avrgcc khi hc s dng AVR v khi vit th vin. Nhng khi cn vit chng trnh
ng dng ti thng chn avrgcc v CodeVisionAVR.
Trong bi vit ny ti hng dn bn s dng AvrStudio vit chng trnh
cho AVR bng ASM.
Chng trnh np (Chip Programmer): a s cc trnh bin dch (AvrStudio,
CodeVisionAVR, Bascom) u tch hp sn 1 chng trnh np chip h tr
nhiu loi mch np nn bn khng qu lo lng. Trong trng hp khc, bn c th
s dng cc chng trnh np nh Icprog hay Ponyprogl cc chng trnh np
min ph cho AVR. Vic chn v s dng chng trnh np s c gii thiu trong
cc bi sau.
Mch np: tham kho bi vit gii thiu mch np AVR.

Chng trnh m phng: avr simulator l trnh m phng v debbug c tch
hp sn trong Avrstudio, avr simulator cho php bn quan st trng thi cc thanh
ghi bn trong AVR nn rt ph hp bn debug chng trnh. Proteus l chng
trnh th hai ti mun ni n, Proteus khng nhng m phng hot ng bn
trong chip m cn m phng mch in t. Proteus m phng rt trc quan, n l 1
cng c hu ch khi cc bn cha c iu kin lm cc mch in t.
III. V d u tin ca bn.
Sau khi download AvrStudio, bn hy ci t phn mm trn my ca bn, qu
trnh ci t rt n gin, bn hy theo cc mc nh v nhn next ci t.
Trong bi u tin ny chng ta s vit th 1 chng trnh n gin cho AVR sau
chy m phng bng Proteus. C th c mt s cu lnh cc bn s khng hiu,
nhng ng lo lng qu, trong bi th 2 chng ta s hc v cu trc AVR cc bn
s c gii thich r hn.
thc hin v d ny, bn hy to mt Project bng AVRStudio, phn hng
dn chi tit cho vic to Project trong AVRStudio bn hy tham kho bi hng
dn AVRStudio.on code v d trong bi u tin ny c trnh by trong List1.
List 1. on code u tin ca bn.
1 .CSEG
2 .INCLUDE "M8DEF.INC"
3 .ORG 0x000
4
RJMP BATDAU
5
6 .ORG 0x020
7 BATDAU:
8 ; KHOI TAO CAC DIEU KIEN DAU
9
LDI R16, HIGH(RAMEND)
10 LDI R17, LOW(RAMEND)
11 OUT SPH, R16
12 OUT SPL, R17
13 LDI R16, 0xFF;
14 OUT DDRB, R16
15
16 ; CHUONG TRINH CHINH
17 MAIN:
18 LDI R16, 0B00000001
19 OUT PORTB, R16

20 RCALL DELAY
21
22 LDI R16, 0B00000010
23 OUT PORTB, R16
24 RCALL DELAY
25
26 LDI R16, 0B00000100
27 OUT PORTB, R16
28 RCALL DELAY
29
30 LDI R16, 0B00001000
31 OUT PORTB, R16
32 RCALL DELAY
33
34 LDI R16, 0B00010000
35 OUT PORTB, R16
36 RCALL DELAY
37
38 LDI R16, 0B00100000
39 OUT PORTB, R16
40 RCALL DELAY
41
42 LDI R16, 0B01000000
43 OUT PORTB, R16
44 RCALL DELAY
45
46 LDI R16, 0B10000000
47 OUT PORTB, R16
48 RCALL DELAY
49
50 RJMP MAIN
51 ; CHUONG TRING CON DELAY 65535 chu ky (khoang 65535us neu xung ;clock cho chip
52 DELAY:
53 LDI R20, 0xFF
54 DELAY0:
55
LDI R21, 0xFF
56
DELAY1:
57
DEC R21
58
BRNE DELAY1
59
DEC R20
60
BRNE DELAY0
61 RET
Trc khi tm hiu ngha on code, hy nhn 1 lt qua on code. Trc ht
vic vit HOA hay vit thng l khng quan trng, bn c th vit on code vi
bt c hnh thc no min ng c php, t kha l c. Trong on code:
Bn thy 1 s t c mu BLUE (v d LDI, OUT, RJMP, RCALL,

RET) l cc INSTRUCTiON, tc l cc cu lnh ca ngn ng ASM, bn c
th c ti liu AVR INSTRUCTION tm hiu tt c cc INSTRUCTION.
Cc INSTRUCTION sau s c trnh dch dch thnh cc m tng ng.
Mt s t bt u bng bng du chm . l cc DIRECTIVE (v d

.INCLUDE hay .ORG ) cng l nhng t kha mc nh ca ASM AVR, cc
DIRECTIVE khng phi l m lnh m ch l cc ch dn v a ch b nh, khi
ng b nh, nh ngha macrov khng c trnh dch dch thnh m. Chi tit
v DIRECTIVE c th tm thy trong cc ti liu v ASM AVR, di y ti tm
tt cc DIRECTIVE v chc nng ca chng nh sau:
Thng thng 1 INSTRUCTION c theo sau bi 2 ton hng operand

(tuy nhin c nhiu trng hp ch c 1 ton hng hoc khng c ton hng), khi
ton hng th nht s l cc THANH GHI. ca AVR (nh cp, chng ta
s kho st thanh ghi AVR trong cc bi sau), v d : LDI R16, 0xFF; trong
ton hng R16 l tn 1 thanh ghi trong AVR, v 0xFF l 1 hng s dng
hexadecimal c gi tr tng ng l 255 dng thp phn hay 11111111 nh phn.
Cc t theo sau bi du : l cc nhn label (v d MAIN, DELAY),

l t do chng ta t t, n thc cht l 1 v tr trong b nh chng trnh, c
th s dng nhn nh 1 chng trnh con.
Phn i sau du ; gi l gii thch comment, phn ny khng c bin

dch, bn c th ghi comment bt c u trong chng trnh vi yu cu phi s
dng du ; trc n.
Gii thch on code:c th chia on code trn thnh 4 phn: phn u cha
cc DIRECTIVE v lnh RJMP dng xc nh cc a ch b nh chng trnh,
phn 2 l khi to mt s iu kin u cho Stack Pointer v PORT, phn 3 l

chng trnh chnh, v phn 4 l chng trnh con ( ch y ch l cch b tr ca
ring ti, mt khi quen thuc, bn c th b tr chng trnh theo cch ring ca
bn).
Phn 1 v phn 2:
.CSEG
Ch th .CSEG: Code Segment bo cho trnh bin dch rng phn code theo sau
l phn chng trnh thc thi, phn ny s c download vo b nh chng
trnh ca chip.
.INCLUDE "M8DEF.INC"
Ch th .INCLUDE bo cho trnh bin dch bt u c 1 file nh km, trong
trng hp trn l file M8DEF.INC, y l file cha cc khai bo cho chip
Atmega8 nh thanh ghi, ngtcho vic truy xut trong chng trnh ca bn, y
l dng bt buc, nu bn lp trnh cho chip khc bn hy i tn file nh km, v
d m32def.inc cho chip ATmega32 bn c th tm thy cc file ny trong th
mc C:\Program Files\Atmel\AVR Tools\AvrAssembler2\Appnotes.
.ORG 0x000
Ch th .ORG: Set Program Origin, set v tr trong b nh s c tc ng n,
trong trng hp trn, .ORG 0x000 xc nh phn code theo ngay sau s nm a
ch 000, v tr u tin, trong b nh chng trnh. V dng lnh trong v tr u
tin l:
RJMP BATDAU
RJMP: Relative Jump l lnh nhy khng iu kin n 1 v tr trong b nh,

trong trng hp trn l nhy n nhn BATDAU, v nhn BATDAU nm v tr
0x020 (s hexadecimal, 0x020 =32 decimal) v n c khai bo ngay sau
DIRECTIVE .ORG 0x020.
.ORG 0x020
BATDAU
Nh th phn b nh chng trnh nm gia 0 v 0x020 khng c s dng
trong on code ca chng ta, phn ny c s dng cho mc ch khc, l cc
vect ngt ( khng c cp y). Tip theo:
; KHOI TAO CC DIEU KIEN DAU
LDI R17, LOW(RAMEND)
OUT SPH, R16
OUT SPL, R17
Bn dng code trn khi to cho Stack Pointer, chng ta s tm hiu phn ny
trong cc bi v Stack v chng trnh con.
Li khuyn: cc bn nn khi ng 1 chng trnh theo cch trn v chng ta
s hiu chng r hn sau ny !
LDI R16, 0xFF
OUT DDRB, R16
Bn ch 2 dng trn v nhng g ti gii thch sau y, 2 dng ny c tc

dng khi ng PORTB ca chip ATmega8 tc dng nh cc ng xut tn hiu
(OUTPUT). Trc ht hy quan st chip ATmega8 trong hnh sau
Hnh 1: chip ATmega8.

Bn c th thy chip ny gm 28 chn, trng c cc chn c ghi l
PB0(chn 14), PB1(chn 15),,PB7(chn 10), l cc chn ca PORTB. PORT
l khi nim ch cc ng xut nhp. Trong AVR, PORT c th giao tip theo 2
hng (bi directional), c th dng xut hoc nhn thng tin, mi PORT c 8
chn. Chip Atmega8 c 3 PORT c tn tng ng l PORTB, PORTC v PORTD
(mt s chip AVR khc c 4 hoc 6 PORT). PORT c coi l ca ng then cht
ca vi iu khin.
Trong AVR, mi PORT lin quan n 3 thanh ghi (8 bits) c tn tng ng l
DDRx, PINx, v PORTx vi x l tn ca PORT, mi bit trong thanh ghi tng
ng vi mi chn ca PORT. Trong trng hp ca Atmega8 x l B, C hoc D.
V d chng ta quan tm n PORTB th 3 thanh ghi tng ng c tn l DDRB,
PINB v PORTB, trong 2 thanh ghi PORTB v PINB c ni trc tip vi cc
chn ca PORTB, DDRB l thanh ghi iu khin hng ( Input hoc Output). Vit
gi tr 1 vo mt bit trong thanh ghi DDRB th chn tng ng ca PORTB s l
chn xut (Output), ngc li gi tr 0 xc lp chn tng ng l ng nhp. Sau
khi vit gi tr iu khin vo DDRB, vic truy xut PORTB c thc hin thng
qua 2 thanh ghi PINB v PORTB.
Quay li vi 2 dng code ca chng ta, dng u: LDI R16, 0xFF, vi LDI
LoaD Immediately, dng lnh c ngha l load gi tr 0xFF vo thanh ghi R16,
R16 l tn 1 thanh ghi trong b nh ca AVR, 0xFF l 1 hng s c dng thp lc
phn, k hiu 0x ni ln iu , bn cng c th dng k hiu khc l $
ch 1 s thp lc phn, v d &FF, v 0xFF=255(thp phn)=0B11111111 (nh
phn). Nh th sau dng u thanh ghi R16 c gi tr l 11111111 (nh phn). Dng
th 2: OUT DDRB, R16 ngha l xut gi tr t thanh ghi R16 ra thanh ghi
DDRB, tm li sau 2 dng trn gi tr DDRB nh sau:
1
C th bn s hi ti sao chng khng s dng 1 dng duy nht l LDI DDRB,

0xFF hay OUT DDRB, 0xFF, chng ta khng th v lnh LDI ch cho php
thc hin trn cc thanh ghi R16,R31 v lnh OUT khng thc hin c vi
cc hng s.
V v DDRB=11111111 nn trong trng hp ny tt c cc chn ca PORTB
sn sng cho vic xut d liu. Lc ny thanh ghi PINB khng c tc dng,
thanh ghi PORTB s l thanh ghi xut, ghi gi tr vo thanh ghi ny s tc ng n
cc chn ca PORTB.1
Phn 3: Chng trnh chnh

MAIN:
LDI R16, 0B00000001
OUT PORTB, R16
RCALL DELAY
Bn ch cn ch 4 dng trn trong ton b phn chng trnh chnh, trc ht
MAIN: ch l 1 nhn do chng ta t t tn, ging nh 1 ct mc trong chng
trnh thi. Dng LDI R16, 0B00000001 th bn hiu, ch c 1 khc bit nh l
ti s dng hng s dng nh phn cho bn d hiu hn. V dng OUT PORTB,
R16 xut gi tr 0B00000001 c sn trong R16 ra thanh ghi PORTB, lc ny
chn PB0 ca chip s ln 1 (5V) v cc chn cn li s mc 0 (0V). Dng th 3:
RCALL DELAY l lnh gi chng trnh con DELAY, tm hon trc khi thc
hin cc dng lnh tip theo:
LDI R16, 0B00000010
OUT PORTB, R16
RCALL DELAY
Ba dng lnh ny cng ging ba dng trn, nhng gi tr xut ra lc ny l
0B00000010, chn PB1 s ln 5V v cc chn khc xung mc 0V. V c nh th
n on cui:
LDI R16, 0B10000000
OUT PORTB, R16
RCALL DELAY
RJMP MAIN
Sau khi kt thc 3 dng trn chn PB7 s ln 5V, kt thc 1 vng xoay. Cui
cng l quay v u chng trnh chnh bng dng RJMP MAIN
By gi chc bn on c chng trnh ca chng ta thc hin vic g,

l qut xoay vng cc chn ca PORTB, nu chng ta kt ni cc chn ca
PORTB vi cc LED, chng ta s c 1 hiu ng qut LED xoay vng, chng ta
thc hin iu ny bng phn mm Proteus.
Phn 4: chng trinh con DELAY: on chng trnh ny khng lm g c

ngoi vic tr hon 1 khong thi gian, tuy nhin bn cha th hiu n ngay c.
y ch l 1 v d n gin, ti c gng thc hin n theo cch d hiu nht cho
bn, v th on code c v hi di dng, bn hy thc hin li on chng trnh
chnh bng on code ca bn.
Phn cui cng l bin dch on code thnh file intel hex vo chip,
nhn phm F7 bin dch.
Sau khi bin dch bn s c 1 file tn avr1.hex trong thc mc project, chng ta
s dng file ny vo chip sau ny.
IV. M phng bng Proteus.
Chng ta hy th nghim on chng trnh ca chng ta bng Proteus. Nu
bn thc hin ng kt qu s nh minh ha trong hnh 2 Hng dn c th cch
v mch in v m phng bng phn mm Proteus bn hy xem bi "M phng
Proteus".
Hnh 2. M phng.
Bi 2 - Cu Trc AVR
5
( 581 Votes )
Ni dung
1.
Gii thiu.

Lm quen AVR.
2.
T chc AVR.
3.
Stack.
4.
Thanh ghi trng thi.
5.
V d.
Assembly cho AVR.

AVR Studio.
M phng vi Proteus.
Download v d
I. Gii thiu.
Bi ny tip tc bi u tin trong lot bi gii thiu v AVR, nu sau bi "Lm
quen AVR" bn phn no bit cch lp trnh cho AVR bng AVRStudio th trong
bi ny, chng ta s tm hiu k hn v cu trc ca AVR. Sau bi ny, bn s:
Hiu c cu trc AVR, cu trc b nh v cch thc hot ng ca chip.
Hiu v Stack v cch hot ng.
Bit c mt s instruction c bn truy xut b nh.
Hc cc instruction r nhnh v vng lp.
Chng trnh con (Subroutine) v Macro.
Ci tin v d trong bi 1.
Vit 1 v d minh ha cch s dng b nh v vng lp.
II. T chc ca AVR.

AVR c cu trc Harvard, trong ng truyn cho b nh d liu (data
memory bus) v ng truyn cho b nh chng trnh (program memory bus)
c tch ring. Data memory bus ch c 8 bit v c kt ni vi hu ht cc thit

b ngoi vi, vi register file. Trong khi program memory bus c rng 16 bits
v ch phc v cho instruction registers. Hnh 1 m t cu trc b nh ca AVR.
B nh chng trnh (Program memory): L b nh Flash lp trnh c,
trong cc chip AVR c (nh AT90S1200 hay AT90S2313) b nh chng trnh
ch gm 1 phn l Application Flash Section nhng trong cc chip AVR mi chng
ta c thm phn Boot Flash setion. Boot section s c kho st trong cc phn
sau, trong bi ny khi ni v b nh chng trnh, chng ta t hiu l Application
section. Thc cht, application section bao gm 2 phn: phn cha cc instruction
(m lnh cho hot ng ca chip) v phn cha cc vector ngt (interrupt vectors).
Cc vector ngt nm phn u ca application section (t a ch 0x0000) v di
n bao nhiu ty thuc vo loi chip. Phn cha instruction nm lin sau ,
chng trnh vit cho chip phi c load vo phn ny. Xem li phn u ca v
d trong bi 1:
.ORG 0x000
RJMP BATDAU
.ORG 0x020
Trong v d ny, ngay sau khi set v tr 0x000 bng ch th (DIRECTIVE)
.ORG 0x000 chng ta dng instruction RJMP nhy n v tr 0x020, nh th
phn b nh chng trnh t 0x00 n 0x01F khng c s dng (v trong v d
ny chng ta khng s dng cc vector ngt). Chng trnh chnh c bt u t
a ch 0x020, con s 0x020 l do ngi lp trnh chn, tht ra cc vector ngt ca
chip ATMEGA8 ch ko di n a ch 0x012, v vy chng trnh chnh c th
c bt u t bt c v tr no sau . bit di cc vector ngt ca tng
chip bn hy tham kho datasheet ca chip .
V chc nng chnh ca b nh chng trnh l cha instruction, chng ta
khng c nhiu c hi tc ng ln b nh ny khi lp trnh cho chip, v th i vi
ngi lp trnh AVR, b nh ny khng qu quan trng. Tt c cc thanh ghi
quan trng cn kho st nm trong b nh d liu ca chip.
Hnh 1. T chc b nh ca AVR.

B nh d liu (data memory): y l phn cha cc thanh ghi quan trng
nht ca chip, vic lp trnh cho chip phn ln l truy cp b nh ny. B nh d
liu trn cc chip AVR c ln khc nhau ty theo mi chip, tuy nhin v c bn
phn b nh ny c chia thnh 5 phn:
Phn 1: l phn u tin trong b nh d liu, nh m t trong hnh 1, phn
ny bao gm 32 thanh ghi c tn gi l register file (RF), hay General Purpose
Rgegister GPR, hoc n gin l cc Thanh ghi. Tt c cc thanh ghi ny u l
cc thanh ghi 8 bits nh trong hnh 2.
Hnh 2. Thanh ghi 8 bits.
Tt c cc chip trong h AVR u bao gm 32 thanh ghi Register File c a ch
tuyt i t 0x0000 n 0x001F. Mi thanh ghi c th cha gi tr dng t 0 n
255 hoc cc gi tr c du t -128 n 127 hoc m ASCII ca mt k t no
Cc thanh ghi ny c t tn theo th t l R0 n R31. Chng c chia
thnh 2 phn, phn 1 bao gm cc thanh ghi t R0 n R15 v phn 2 l cc thanh
ghi R16 n R31. Cc thanh ghi ny c cc c im sau:
c truy cp trc tip trong cc instruction.
Cc ton t, php ton thc hin trn cc thanh ghi ny ch cn 1 chu k

xung clock.
Register File c kt ni trc tip vi b x l trung tm CPU ca chip.
Chng l ngun cha cc s hng trong cc php ton v cng l ch cha

kt qu tr li ca php ton.
minh ha, hy xt v d thc hin php cng 2 thanh ghi bng instruction ADD
nh sau:
ADD R1, R2
Bn thy trong dng lnh trn, 2 thanh ghi R1 v R2 c s dng trc tip
vi tn ca chng, dng lnh trn khi c dch sang opcode download vo chip
s c dng: 0000110000010010 trong 00001=1 tc thanh ghi R1 v 00010 = 2
ch thanh ghi R2. Sau php cng, kt qu s c lu vo thanh ghi R1.
Tt c cc instruction s dng RF lm ton hng u c th truy nhp tt c cc
RF mt cch trc tip trong 1 chu k xung clock, ngoi tr SBCI, SUBI, CPI,
ANDI v LDI, cc instruction ny ch c th truy nhp cc thanh ghi t R16 n
R31.
Thanh ghi R0 l thanh ghi duy nht c s dng trong instruction LPM (Load
Program Memory). Cc thanh ghi R26, R27, R28, R29, R30 v R31 ngoi chc
nng thng thng cn c s dng nh cc con tr (Pointer register) trong mt
s instruction truy xut gin tip. Chng ta s kho st vn con tr sau ny. Hnh
3 m t cc chc nng ph ca cc thanh ghi.
Hnh 3. Register file.

Tm li 32 RF ca AVR c xem l 1 phn ca CPU, v th chng c CPU
s dng trc tip v nhanh chng, gi cc thanh ghi ny, chng ta khng cn gi
a ch m ch cn gi trc tip tn ca chng. RF thng c s dng nh cc
ton hng (operand) ca cc php ton trong lc lp trnh.
Phn 2: l phn nm ngay sau register file, phn ny bao gm 64 thanh ghi
c gi l 64 thanh ghi nhp/xut (64 I/O register) hay cn gi l vng nh I/O
(I/O Memory). Vng nh I/O l ca ng giao tip gia CPU v thit b ngoi vi.
Tt c cc thanh ghi iu khin, trng thica thit b ngoi vi u nm y.
Xem li v d trong bi 1, trong ti c cp v vic iu khin cc PORT ca
AVR, mi PORT lin quan n 3 thanh ghi DDRx, PORTx v PINx, tt c 3 thanh
ghi ny u nm trong vng nh I/O. Xa hn, nu mun truy xut cc thit b
ngoi vi khc nh Timer, chuyn i Analog/Digital, giao tip USARTu thc
hin thng qua vic iu khin cc thanh ghi trong vng nh ny.
Vng nh I/O c th c truy cp nh SRAM hay nh cc thanh ghi I/O. Nu
s dng instruction truy xut SRAM truy xut vng nh ny th a ch ca
chng c tnh t 0x0020 n 0x005F. Nhng nu truy xut nh cc thanh ghi

I/O th a ch ca chng c tnh t 0x0000 n 0x003F.
Xt v d instruction OUT dng xut gi tr ra cc thanh ghi I/O, lnh ny s
dng a ch kiu thanh ghi, cu trc ca lnh nh sau: OUT A, Rr, trong A l
a ch ca thanh ghi trong vng nh I/O, Rr l thanh ghi RF, lnh OUT xut gi tr
t thanh ghi Rr ra thanh ghi I/O c a ch l A. Gi s chng ta mun xut gi tr
cha trong R6 ra thanh ghi iu khin hng ca PORTD, tc thanh ghi DDRD,
a ch tnh theo vng I/O ca thanh ghi DDRD l 0x0011, nh th cu lnh ca
chng ta s c dng: OUT 0x0011, R6. Tuy nhin trong 1 trng hp khc, nu
mun truy xut DDRD theo dng SRAM, v d lnh STS hay LDS, th phi dng
a ch tuyt i ca thanh ghi ny, tc gi tr 0x0031, khi lnh OUT trn
c vit li l STS 0x0031, R6.
thng nht cch s dng t ng, t by gi chng ta dng khi nim a
ch I/O cho cc thanh ghi trong vng nh I/O ni n a ch khng tnh phn
Register File, khi nim a ch b nh ca thanh ghi l ch a ch tuyt i
ca chng trong SRAM. V d thanh ghi DDRD c a ch I/O l 0x0011 v
a ch b nh ca n l 0x0031, a ch b nh = a ch I/O + 0x0020.
V cc thanh ghi trong vng I/O khng c hiu theo tn gi nh cc Register
file, khi lp trnh cho cc thanh ghi ny, ngi lp trnh cn nh a ch ca tng
thanh ghi, y l vic tng i kh khn. Tuy nhin, trong hu ht cc phn mm
lp trnh cho AVR, a ch ca tt c cc thanh ghi trong vng I/O u c nh
ngha trc trong 1 file Definition, bn ch cn nh km file ny vo chng trnh
ca bn l c th truy xut cc thanh ghi vi tn gi ca chng. Gi s trong v d
bi 1, lp trnh cho chip Atmega8 bng AVRStudio, dng th 2 chng ta s
dng INCLUDE "M8DEF.INC" load file nh ngha cho chip ATMega8, file
M8DEF.INC. V vy, trong sau ny khi mun s dng thanh ghi DDRD bn ch
cn gi tn ca chng, nh: OUT DDRD,R6.
Phn 3: RAM tnh, ni (internal SRAM), l vng khng gian cho cha cc bin
(tm thi hoc ton cc) trong lc thc thi chng trnh, vng ny tng t cc
thanh RAM trong my tnh nhng c dung lng kh nh (khong vi KB, ty
thuc vo loi chip).
Phn 4: RAM ngoi (external SRAM), cc chip AVR cho php ngi s dng
gn thm cc b nh ngoi cha bin, vng ny thc cht ch tn ti khi no
ngi s dng gn thm b nh ngoi vo chip.
Phn 5: EEPROM (Electrically Ereasable Programmable ROM) l mt phn
quan trng ca cc chip AVR mi, v l ROM nn b nh ny khng b xa ngay
c khi khng cung cp ngun nui cho chip, rt thch hp cho cc ng dng lu tr
d liu. Nh trong hnh 1, phn b nh EEPROM c tch ring v c a ch
tnh t 0x0000.
Cu hi by gi l AVR hot ng nh th no?
Hnh 4 biu din cu trong bn trong ca 1 AVR. Bn thy rng 32 thanh ghi
trong Register File c kt ni trc tip vi Arithmetic Logic Unit -ALU (ALU
cng c xem l CPU ca AVR) bng 2 line, v th ALU c th truy xut trc tip
cng lc 2 thanh ghi RF ch trong 1 chu k xung clock (vng c khoanh trn
mu trong hnh 4).
Hnh 4. Cu trc bn trong AVR.

Cc instruction c cha trong b nh chng trnh Flash memory di dng
cc thanh ghi 16 bit. B nh chng trnh c truy cp trong mi chu k xung
clock v 1 instruction cha trong program memory s c load vo trong
instruction register, instruction register tc ng v la chn register file cng nh
RAM cho ALU thc thi. Trong lc thc thi chng trnh, a ch ca dng lnh
ang thc thi c quyt nh bi mt b m chng trnh PC (Program
counter). chnh l cch thc hot ng ca AVR.
AVR c u im l hu ht cc instruction u c thc thi trong 1 chu k
xung clock, v vy c th ngun clock ln nht cho AVR c th nh hn 1 s vi
iu khin khc nh PIC nhng thi gian thc thi vn nhanh hn.
III. Stack.
Stack c hiu nh l 1 thp d liu, d liu c cha vo stack nh

thp v d liu cng c ly ra t nh. Kiu truy cp d liu ca stack gi l
LIFO (Last In First Out vo sau ra trc). Hnh 5 th hin cch truy cp d liu
ca stack.
Hnh 5. Stack.
Khi nim v cch thc hot ng ca stack c th c p dng cho AVR,
bng cch khai bo mt vng nh trong SRAM l stack ta c th s dng vng nh
ny nh mt stack thc th.
khai bo mt vng SRAM lm stack chng ta cn xc lp a ch u ca
stack bng cch xc lp con tr stack-SP (Stack Pointer). SP l 1 con tr 16 bit bao
gm 2 thanh ghi 8 bit SPL v SPH (ch L l LOW ch thanh ghi mang gi tr byte
thp ca SP, v H = HIGH), SPL v SPH nm trong vng nh I/O. Gi tr gn cho
thanh ghi SP s l a ch khi ng ca stack. Quay li v d bi 1, phn khi
to cc iu kin u.
; KHOI TAO CC DIEU KIEN DAU
OUT SPH, R16
OUT SPL, R17
Bn dng khai bo trn mc ch l gn gi tr ca RAMEND cho con tr SP,
RAMEND (tc End of Ram) l bin cha a ch ln nht ca RAM ni trong
AVR, bin ny c nh ngha trong file M8DEF.INC. Nh th sau 4 dng trn,
con tr SP cha gi tr cui cng ca SRAM hay ni cch khc vng stack bt u
t v tr cui cng ca b nh SRAM. Nhng ti sao l v tr cui cng m khng
l 1 gi tr khc. C th gii thch nh sau: stack trong AVR hot ng t trn
xung, sau khi d liu c y vo stack, SP s gim gi tr v th khi ng SP
v tr cui cng ca SRAM s trnh c vic mt d liu do ghi . Bn c th
khi ng stack vi 1 a ch khc, tuy nhin v l do an ton, nn khi ng stack

RAMEND.
Hai instruction dng cho truy cp stack l PUSH v POP, trong PUSH dng
y d liu vo stack v POP dng ly d liu ra khi stack. D liu c y vo
v ly ra khi stack ti v tr m con tr SP tr n. V d cho chip ATMega8,
RAMEND=0x045F, sau khi khi ng, con tr SP tr n v tr 0x045F trong
SRAM, nu ta vit cc cu lnh sau:
LDI R16,
PUSH R16
LDI R16,
PUSH R16
LDI R16,
PUSH R16
Khi ni dung ca stack s nh trong hnh 6.
1
5
8
Hnh 6. Ni dung stack trong v d.

Sau mi ln PUSH d liu, SP s gim 1 n v v tr vo v tr tip theo.
By gi nu ta dng POP ly d liu t stack, POP R2, th R2 s mang gi tr
ca ngn nh 0x045D, tc R2=8. Trc khi instruction POP c thc hin, con
tr SP c tng ln 1 n v, sau d liu s c ly ra t v tr m SP tr n
trong stack.
Stack trong AVR khng phi l v y, ngha l chng ta ch c th PUSH
d liu vo stack 1 su nht nh no y (ph thuc vo chip). S dng stack
khng ng cch i khi s lm chng trnh thc thi sai hoc tn thi gian thc
thi v ch. V th khng nn s dng stack ch lu cc bin thng thng. ng
dng ph bin nht ca stack l s dng trong cc chng trnh con (Subroutine),
khi chng ta cn nhy t mt v tr trong chng trnh chnh n 1 chng trnh
con, sau khi thc hin chng trnh con li mun quay v v tr ban u trong
chng trnh chnh th Stack l phng cch ti u dng cha b m chng
trnh trong trng hp ny. Xem li v d trong bi 1, trong chng trnh chnh
chng ta dng lnh RCALL DELAY nhy n on chng trnh con DELAY,
RCALL l lnh nhy n 1 v tr trong b nh chng trnh, trc khi nhy, PC

c cng thm 1 v PUSH mt cch t ng vo stack. Cui chng trnh con
DELAY, chng ta dng instruction RET, instruction ny POP d liu t stack ra PC
mt cch t ng, bng cch ny chng ta c th quay li v tr trc . Chnh v
cc lnh RCALL v RET s dng stack mt cch t ng nn ta phi khi ng
stack ngay t u, nu khng chng trnh s thc thi sai chc nng.
Tm li cn khi ng stack u chng trnh v khng nn s dng stack
mt cch ty thch nu cha tht cn thit.
IV. Thanh ghi trng thi - SREG (STATUS REGISTRY).
Nm trong vng nh I/O, thanh ghi SREG c a ch I/O l 0x003F v a ch
b nh l 0x005F (thng y l v tr cui cng ca vng nh I/O) l mt trong s
cc thanh ghi quan trng nht ca AVR, v th m ti dnh phn ny gii thiu
v thanh ghi ny. Thanh ghi SREG cha 8 bit c (flag) ch trng thi ca b x l,
tt c cc bit ny u b xa sau khi reset, cc bit ny cng c th c c v ghi
bi chng trnh. Chc nng ca tng bit c m t nh sau:
Hnh 7. Thanh ghi trng thi.
Bit 0 C (Carry Flag: C nh): l bit nh trong cc php i s hoc

logic, v d thanh ghi R1 cha gi tr 200, R2 cha 70, chng ta thc hin php
cng c nh: ADC R1, R2, sau php cng, kt qu s c lu li trong thanh ghi
R1, trong khi kt qu thc l 270 m thanh ghi R1 li ch c kh nng cha ti a
gi tr 255 (v c 8 bit) nn trong trng hp ny, gi tr lu li trong R1 thc cht
ch l 14, ng thi c C c set ln 1 (v 270=100001110, trong 8 bit sau
00001110 =14 s c lu li trong R1).
Bit 1 Z (Zero Flag: C 0): c ny c set nu kt qu php ton i s

hay php Logic bng 0.
Bit 2 N (Negative Flag: C m): c ny c set nu kt qu php ton

i s hay php Logic l s m.
Bit 3 V (Twos complement Overflow Flag: C trn ca b 2): hot

ng ca c ny c v s kh hiu cho bn v n lin quan n kin thc s nh
phn (phn b), chng ta s cp n khi no thy cn thit.
Bit 4 S (Sign Bit: Bit du): Bit S l kt qu php XOR gia 1 c N v V,

S=N xor V.
Bit 5 H (Half Carry Flag: C nh na): c H l c nh trong 1 vi php

ton i s v php Logic, c ny hiu qu i vi cc php ton vi s BCD.
Bit 6 T (Bit Copy Storage): c s dng trong 2 Instruction BLD (Bit

LoaD) v BST (Bit STorage). Ti s gii thch chc nng Bit T trong phn gii
thiu v BLD v BST.
Bit 7 I (Global Interrupt Enable) : Cho php ngt ton b): Bit ny phi
c set ln 1 nu trong chng trnh c s dng ngt. Sau khi set bit ny, bn
mun kch hot loi ngt no cn set cc bit ngt ring ca ngt . Hai instruction
dng ring Set v Clear bit I l SEI v CLI.
Ch : tt c cc bit trong thanh ghi SREG u c th c xa thng qua cc
instruction khng ton hng CLx v set bi SEx, trong x l tn ca Bit.V d
CLT l xa Bit T v SEI l set bit I.
Ti ch gii thch ngn gn chc nng ca cc bit trong thanh ghi SREG, c th
chc nng v cch s dng ca tng bit chng ta s tm hiu trong cc trng hp
c th sau ny, ngi c c th t tm hiu thm trong cc ti liu v
INSTRUCTION cho AVR.
Ti cung cp thm 1 bng tm tt s nh hng ca cc php ton i s, logic
ln cc Bit trong thanh ghi SREG.
Hnh 8. nh hng ca cc php ton ln SREG.

IV. Macro v chng trnh con.
Macro l khi nim ch mt on code nh thc hin mt cng vic no ,
nu c 1 on code no m bn rt hay s dng khi lp trnh th bn nn dng
macro trnh vic phi vit i vit li on code . Lp trnh ASM cho AVR cho
php bn s dng Macro, to 1 Macro bn s dng DIRECTIVE.
.MACRO delay4
NOP
NOP
NOP
NOP
.ENDMACRO
on Macro trn c tn delay4 thc hin vic delay 4 chu k my bng 4 lnh
NOP, nu trong chng trnh bn cn dng Macro ny th ch cn gi delay4 bt
k dng no.
[] ; code ca bn
Delay4
[] ; code ca bn
Mi ln tn ca Macro c gi, trnh bin dch s tm n Macro v copy
ton b ni dung Macro vo v tr bn gi. Nh vy thc cht con tr chng trnh
khng nhy n Macro, Macro khng lm gim dung lng chong trnh m ch
lm cho vic lp trnh nh nhng hn. y chnh l khc bit ln nht ca Macro
v Subroutine (chng trnh con).
Chng trnh con cng l 1 on code thc hin 1 chc nng c bit no .
Tuy nhin khc vi Macro, mi khi gi chng trnh con, con tr chng trnh
nhy n chng trnh con thc thi chng trnh con v sau quay v chng
trnh chnh. Nh th chng trnh con ch c bin dch 1 ln v c th s dng
nhiu ln, n lm gim dung lng chong trnh. y l u im v cng l im
khc bit ln nht gia chng trnh con v Macro. Tuy nhin cn ch l vic
nhy n chng trnh con v nhy v chng trnh chnh cn vi chu k my, c
th lm chm chng trnh, y l nhc im ca chng trnh con so vi macro.
Chng trnh con cho AVR lun c bt u bng 1 Label, cng l tn v
a ch ca chng trnh con. Chng trnh con thng c kt thc vi cu lnh
RET (Return). Chng ta bit v chng trnh con qua v d ca bi 1, trong
DELAY l 1 chng trnh con.
gi chng trnh con t 1 v tr no trong chng trnh, chng ta c th
dng lnh CALL hoc RCALL(Relative CALL) (xem li v d bi 1 v cch s
dng RCALL). Mi khi cc lnh ny c gi, b m chng trnh c t ng
c PUSH vo stack v khi chng trnh con kt thc bng lnh RET, b m
chng trnh c POP tr ra v quay v chng trnh chnh. Lnh CALL c th
gi 1 chng trnh con bt k v tr no trong khi RCALL ch gi trong khong
b nh 4KB, nhng RCALL cn t chu k xung clock hn khi thc thi.
Hai instruction khc c th c dng gi chng trnh con l JMP
(Jump) v RJMP (Relative Jump). Khc vi cc lnh call, cc lnh jump khng cho
php quay li v khng t ng PUSH b m chng trnh vo Stack, s dng
cc lnh ny gi chng trnh con bn cn mt s lnh jump khc cui chng
trnh con.
Tm li bn nn vit 1 chng trnh con ng chun v dng CALL hoc
RCALL gi chng cc chng trnh ny, ch nhng trng hp c bit hoc
bn hiu rt r v chng th c th dng cc lnh jump.
V. V d minh ha.
Nu bn c v hiu n thi im ny th bn c th hiu ht hot ng

ca chng trnh v d trong bi 1, tht s v d rt n gin v d hiu. Tuy
nhin, bn c th ti u ha v d theo hng lm gim dung lng chng
trnh v tt nhin, chng trnh s kh hiu hn cho ngi khc. Cc phn khi
ng v tr b nh, stack v chng trnh con DELAY chng ta khng thay i, ch
thay i phn chng trnh chnh, 1 trong nhng cch vit chng trnh chnh nh
cch sau:
; CHUONG TRINH CHINH , BAI 1, VI DU 1, VERSION 2///////////////////////////////
LDI R16,
$1 ;LOAD
GIA
TRI
KHOI
DONG
CHO
R16
MAIN:
OUT PORTB, R16 ; XUAT GIA TRI TRONG R16 RA PORTB
RCALL DELAY ;
GOI
CHUONG
TRINH
CON
DELAY
ROL R16 ; XOAY THANH GHI R16 SANG TRAI 1 VI TRI
RJMP MAIN ; NEU R16 0, NHAY VE MAIN, TIEP TUC QUET
;/////////////////////////////////////////////////////////////////////////////////////////
C th khng cn gii thch bn cng c th hiu on code trn, y ch l
1 trong nhng cch c th, bn hy vit li theo cch ca ring bn vi yu cu l
chng trnh phi thc hin ng chc nng v ngn gn.
By gi chng ta s thc hin mt v d minh ha cho nhng g chng ta
hc trong bi 2 ny. Ni dung ca v d th hin trong mch in hnh 9. Hot
ng ca mch in t nh sau: 1 chip ATMega8 c s dng nh mt counter,
c th dng m ln v m xung, 2 button trong mch in tc ng nh 2
kicker, nhn button 1 m ln v button m xung, gi tr m nm trong
khong t 0 n 9. Gi tr m c hin th trn 1 LED 7 on loi anod chung
(dng chung), chip 7447 c dng gii m t gi tr BCD xut ra bi
ATMega8 sang tn hiu cho LED 7 on anod chung, chng ta cn s dng 7447 v
tn hiu xut ra t chip ATMega8 l dng nh phn hoc BCD , tn hiu ny khng
th hin th trc tip trn cc LED 7 on, chip 7447 c nhim v chuyn 1 d liu
dng digit BCD sang m ph hp cho LED 7 on.
thc hin v d, trc ht bn hy v mch in nh trong hnh 9 bng
phn mm Proteus (xem cch v mch in bng Proteus), mch in ch c 5 loi
linh kin l chip ATMega8 (t kha mega8), 1 LED 7 on anod chung vi tn y
trong Proteus l 7SEG-COM-AN-GRN (t kha 7SEG), 1 chip 7447 (t kha
7447), 1 in tr 10 v 2 button (t kha button).
Hnh 9. V d cho bi 2.
S dng AVRStudio to 1 project mi vi tn gi avr2 (xem li cch to
Project mi trong AVRStudio). Vit li phn code bn di vo vo file avr2.asm
List 1. V d cu trc AVR
1 .INCLUDE "M8DEF.INC"
2 .CSEG.
3 .ORG 0x0000
4
RJMP BATDAU
5 .ORG 0x0020
6 BATDAU:
7 ;KHOI DONG STACK POINTER
8
9
10
OUT SPL, R16
11
OUT SPH,R17
12 ; KHOI DONG CAC PORT
13
CLR R16 ; XOA R16, R16=0
14
OUT DDRB, R16 ; DDRB=0, PORTB LA NGO NHAP
15
LDI R16, 0xFF ; SET TAT CA CAC BIT CUA R16 LEN 1
16
OUT PORTB,R16 ;DDRB=0, PORTB =0xFF, KEO LEN CAC CHAN PORTB
17
OUT DDRD, R16 ;DDRD=0xFF, PORTD LA NGO XUAT
18
CLR R25 ;XOA R25, R25 LA THANH GHI DUNG CHUA SO DEM
19
SER R20 ; R20 LA THANH GHI TAM CHUA GIA TRI TRUOC DO CUA PINB
20 MAIN:
21
IN R21,PINB ;DOC GIA TRI TU PINB, TUC TU CAC BUTTON
22
RCALL SOSANH ;GOI CHUONG TRINH CON SOSANH
23
OUT PORTD, R25 ;XUAT GIA TRI DEM RA PORTD
24
SBRS R21,0 ;NEU BIT 0 CUA R21 (TUC CHAN PB0) =1 THI BO QUA DONG ;TIEP T
25
RCALL TANG ;NHAY DEN CHUONG TRINH CON TANG GIA TRI DEM
26
SBRS R21,1 ;NEU BIT 1 CUA R21 (TUC CHAN PB1) =1 THI BO QUA DONG ;TIEP T
27
RCALL GIAM ;NHAY DEN CHUONG TRINH CON GIAM GIA TRI DEM
28
MOV R20,R21 ;LUU LAI TRANG THAI PINB
29
RJMP MAIN
30 ;**********************CHUONG TRINH CON************************
31 ; **************subroutine kiem tra gioi hang (tu 0 den 9) cua so dem
32 SOSANH:
33
CPI R25, 10
34
BREQ RESET0 ;NEU GIA TRI DEM=10 THI TRA VE 0
35
CPI R25, 255
36
BREQ RESET9 ;NEU GIA TRI DEM =255 THI TRA VE 9
37
RJMP QUAYVE ;NHAY DEN NHAN QUAYVE
38 RESET0:
39
LDI R25,$0 ;TRA GIA TRI DEM VE 0
40
RJMP QUAYVE
41 RESET9:
42
LDI R25,$9 ;GAN 9 CHO GIA TRI DEM
43 QUAYVE:
44
RET
45 ; ************************************************************
46 ; **************subroutine tang so dem 1 don vi neu dieu kien thoa
47 TANG:
48
SBRS R20,0
49
RET
50
INC R25
51
RET
52 ; **************subroutine giam so dem 1 don vi neu dieu kien thoa
53 GIAM:
54
SBRS R20,1
55
RET
56
DEC R25
57
RET
Trong v ny ny, chng ta s dng 2 PORT ca chip ATMega8, PORTD dng
xut d liu (s m) ra chip 7447 v sau hin th trn LED 7 on. PORTB
dng nh ng nhp, tn hiu t cc button s c chip ATMega8 nhn thng qua 2
chn
PB0
v
PB1
ca
PORTB.
Hot ng ca cac PORT v vic xc lp 1 PORT nh cc ng xut chng ta
kho st trong bi 1. y chng ta kho st thm v xc lp PORT nh 1 ng
nhp, trc ht bn hy quan st mch in tng ng ca 1 chn trong cc

PORT xut nhp ca AVR trong hnh 10.
Hnh 10. Cu trc chn trong PORT ca AVR.

Trong mch in hnh 10, cc diode v t in ch c chc nng bo v chn
PORT, nhng in tr Rpu (R Pull up) ng vai tr quan trng nh l in tr ko
ln khi chn ca PORT lm nhim v nhn tn hiu (ng nhp). Tuy nhin trong
AVR, in tr ko ln ny khng phi lun kch hot, chng ta bit rng mi PORT
ca AVR c 3 thanh ghi: DDRx, PORTx v PINx, nu DDRx=0 th PORT x l ng
nhp, lc ny thanh ghi PINx l thanh ghi cha d liu nhn v, c bit thanh ghi
PORTx vn c s dng trong mode ny, l thanh ghi xc lp in tr ko ln,
nh th nu DDRx=0 v PORTx=0xFF th cc chn PORTx l ng nhp v c
ko ln bi 1 in tr trong chip, ngha l cc chn ca PORTx lun mc cao,
mun kch thay i trng thi chn ny chng ta cn ni chn trc tip vi
GND, y l l do ti sao cc button trong mch in ca chng ta c 1 u ni vi
chn ca chip cn u kia c ni vi GND. y cng l ngha ca khi nim
in tr ko ln (Pull up resistor) trong k thut in t. on code trong phn
KHOI DONG CAC PORT ca v d ny xc lp PORTD l ng xut
(DDRD=0xFF) , PORTB l ng nhp c s dng in tr ko ln (DDRB=0,
PORTB=0xFF).
Chng ta s gii thch hot ng ca on chng trnh chnh v cc on
chng trnh con. Trc ht, trong chng trnh ny, chng ta s dng 3 thanh ghi
chnh l R20, R21 v R25, trong R25 l thanh ghi cha s m, gi tr ca thanh
ghi R25 s c xut ra PORTD ca chip, thanh ghi R21 cha trng thi ca thanh
ghi PINB v cng l trng thi ca cc button, thanh ghi R20 kt hp vi thanh ghi
R21 to thnh 1 b m cnh xung ca cc button. hiu thu o hot ng
m (cng l hot ng chnh ca v d ny) chng ta xt trng thi chn PB0 nh
trong hnh 11.
Hnh 11. Thay i trng thi cc chn I/O.

Trong trng thi bnh thng (button khng c nhn), chn PB0 mc cao
(do in tr ko ln), b m khng hot ng, gi tr m khng thay i, by gi
nu nhn button, chn PB0 c ni trc tip vi GND, chn ny s b ko xung
mc thp, bng cch kim tra trng thi chn PB0, nu PB0=0 ta tng gi tr m 1
n v. tng nh th c v hp l, tuy nhin nu p dng th chng trnh s
hot ng khng ng chc nng, khi bn nhn 1 ln gi, tr m c th tng n
c trm hoc khng kim sot c, hiu ng ny tng t khi bn nhn v gi 1
phm trn bn phm my tnh, l do l v chng ta s dng phng php kim tra
mc m, thi gian qut ca chng trnh rt ngn so vi thi gian chng ta
gi button. khc phc, chng ta dng phng php kim tra cnh xung, ch
khi no pht hin chn PB0 thay i t 1 xung 0 th mi tng gi tr m 1 n v,
kt qu l mi ln nhn button th gi tr m ch tng 1 (ngay c khi ta nhn v gi
button), thanh ghi R20 c s dng lu trng thi trc ca PINB (cng l
trng
thi
ca
cc
button).
Trong chng trnh, ti s dng 2 istruction mi l SBRC v SBRS kim tra
trng thi cc chn ca PORTB (button). SBRC Skip if Bit in Register is Clear,
lnh ny s b qua 1 dng lnh ngay sau (ch b qua 1 dng duy nht) nu 1 bit
trong thanh ghi mc 0, SBRC Skip if Bit in Register is Set- hot ng tng t
SBRC nhng skip s xy ra nu bit trong thanh ghi mc 1. Da vo y chng ta
gii thch 4 dng sau:
SBRS R21,0 ;NEU BIT 0 CUA R21 (TUC CHAN PB0) =1 THI BO QUA
DONG ;TIEP THEO
RCALL TANG ;NHAY DEN CHUONG TRINH CON TANG GIA TRI DEM
SBRS R21,1 ;NEU BIT 1 CUA R21 (TUC CHAN PB1) =1 THI BO QUA
DONG ;TIEP THEO
RCALL GIAM ;NHAY DEN CHUONG TRINH CON GIAM GIA TRI DEM
Dng 1 dng kim tra trng thi bit 0 trong R21 (ch R21 cha gi tr ca
PINB), nu bit ny bng 1 (set), tc chn PB0=1 hay button khng c nhn, th
nhy b qua dng lnh tip theo n dng 3. dng 3 chng trnh kim tra
trng thi chn PB1 (button th 2). Quay li dng 1, nu chng trnh kim tra
pht hin chn PB0=0 (button th nht c nhn) th dng lnh th 2 c thc
thi, kt qu l chng trnh nhy n chng trnh con TANG.
TANG:
SBRS R20,0
RET
INC R25
RET
Dng u tin ca chng trnh con TANG l kim tra trng thi trc ca
chn PB0 (c lu bit 0 trong thanh ghi R20), nu trng thi ny bng 0, ngha
l khng c s chuyn t 1 xung 0 chn PB0, dng 2 (lnh RET) s c thc
thi quay v chng trnh chnh. Nhng nu PB0 trc bng 1, ngha l c s
thay i t 1->0 chn ny, gi tr m s c tng thm 1 nh INC R25, sau
quay
v
chng
trnh
chnh.
Tm li mun tng gi tr m thm 1 n v cn tha mn 2 iu kin: chn PB0
hin ti =0 (button ang c nhn) v trng thi trc ca PB0 phi l 1 (trnh
trng hp tng lin tc). Phng php ny c th p dng cho rt nhiu trng
hp
m
dng
m
xung.
Qu trnh gim gi tr m c hiu tng t, phn cn li ca v d ny bn
c hy t gii thch theo nhng gi trn.
Bi 3 - Ngt ngoi
5
( 138 Votes )
Ni dung
1.
Ngt trn AVR.
Cu trc AVR.
2.
Ngt ngoi.
WinAVR.
3.
V d ngt ngoi vi C.
C cho AVR.
Download v d
M phng vi Proteus.
I. Ngt trn AVR.
Interrupts, thng c gi l ngt, l mt tn hiu khn cp gi n b x l,
yu cu b x l tm ngng tc khc cc hot ng hin ti nhy n mt ni
khc thc hin mt nhim v khn cp no , nhim v ny gi l trnh phc v
ngt isr (interrupt service routine ). Sau khi kt thc nhim v trong isr, b m
chng trnh s c tr v gi tr trc b x l quay v thc hin tip cc
nhim v cn dang d. Nh vy, ngt c mc u tin x l cao nht, ngt
thng c dng x l cc s kin bt ng nhng khng tn qu nhiu thi
gian. Cc tn hiu dn n ngt c th xut pht t cc thit b bn trong chip (ngt
bo b m timer/counter trn, ngt bo qu trnh gi d liu bng RS232 kt
thc) hay do cc tc nhn bn ngoi (ngt bo c 1 button c nhn, ngt bo
c 1 gi d liu c nhn).
Ngt l mt trong 2 k thut bt s kin c bn l hi vng (Polling) v ngt.
Hy tng tng bn cn thit k mt mch iu khin hon chnh thc hin rt
nhiu nhim v bao gm nhn thng tin t ngi dng qua cc button hay keypad
(hoc keyboard), nhn tn hiu t cm bin, x l thng tin, xut tn hiu iu
khin, hin th thng tin trng thi ln cc LCD(bn hon ton c th lm c
vi AVR), r rng trong cc nhim v ny vic nhn thng tin ngi dng (start,
stop, setup, change,) rt him xy ra (so vi cc nhim v khc) nhng li rt
khn cp, c u tin hng u. Nu dng Polling ngha l bn cn vit 1 on
chng trnh chuyn thm d trng thi ca cc button (ti tm gi on chng
trnh l Input()) v bn phi chn on chng trnh Input() ny vo rt nhiu v
tr trong chng trnh chnh trnh trng hp b st lnh t ngi dng, iu
ny tht lng ph thi gian thc thi. Gii php cho vn ny l s dng ngt, bng
cch kt ni cc button vi ng ngt ca chip v s dng chng trnh Input()
lm trnh phc v ngt - isr ca ngt , bn khng cn phi chn Input() trong lc
ang thc thi v v th khng tn thi gian cho n, Input() ch c gi khi ngi
dng nhn cc button. l tng s dng ngt.
Hnh 1 minh ha cch t chc ngt thng thng trong cc chip AVR. S lng
ngt trn mi dng chip l khc nhau, ng vi mi ngt s c vector ngt, vector
ngt l cc thanh ghi c a ch c nh c nh ngha trc nm trong phn u
ca b nh chng trnh. V d vector ngt ngoi 0 (external interrupt 0) ca chip
atmega8 c a ch l 0x001 (theo datasheet t Atmel). Trong lc chng trnh
chnh ang thc thi, nu c mt s thay i dn n ngt xy ra chn INT0 (chn
4), b m chng trnh (Program Counter) nhy n a ch 0x001, gi s ngay

ti a ch 0x001 chng ta c t 1 lnh RJMP n mt trnh phc v ngt (IRS1
chng hn), mt ln na b m chng trnh nhy n IRS1 thc thi trnh phc
v ngt, kt thc ISR1, b m chng trnh li quay v v tr trc trong
chng trnh chnh, qu trnh ngt kt thc. Khng mang tnh bt buc nhng ti
khuyn bn nn t chc chng trnh ngt theo cch ny trnh nhng li lin
quan n a ch chng trnh.
Hnh 1. Ngt.
Bng 1 tm tt cc vector ngt c trn chip atmega8, cho cc chip khc bn hy
tham kho datasheet bit thm.
Bng 1 cc vector ngt v Reset trn chip Atmega8.
II. Ngt ngoi (External Interrupt).

Phn ny ti dnh gii thiu cc bn cch ci t v s dng ngt ngoi v y
l loi ngt duy nht c lp vi cc thit b ca chip, cc ngt khc thng gn
vi hot ng ca 1 thit b no nh Timer/Counter, giao tip ni tip USART,
chuyn i ADCchng ta s kho st c th khi tm hiu v hot ng ca cc

thit b ny.
Ngt ngoi l cch rt hiu qu thc hin giao tip gia ngi dng v chip.
Trn chip atmega8 c 2 ngt ngoi c tn l INT0 v INT1 tng ng 2 chn s 4
(PD2) v s 5 (PD3). Nh ti cp trong bi AVR2, khi lm vic vi cc thit
b ngoi vi ca AVR, hu nh chng ta ch thao tc trn cc thanh ghi chc nng
c bit - SFR (Special Function Registers) trn vng nh IO, mi thit b bao gm
mt tp hp cc thanh ghi iu khin, trng thi, ngtkhc nhau, iu ny ng
ngha chng ta phi nh tt c cc thanh ghi ca AVR. Lc ny datasheet pht huy
tc dng, bn phi nhanh chng download file datasheet ca chip mnh ang s
dng, c rt nhiu ni download nh ti www.atmel.comhay trn cc trang web
chuyn cung cp IC datasheet min ph (www.alldatasheet.com l 1 v d). Quay
v vi ngt ngoi, c 3 thanh ghi lin quan n ngt ngoi l MCUCR, GICR v
GIFR. C th cc thanh ghi c trnh by bn di.
Thanh ghi iu khin MCU MCUCR (MCU Control Register) l thanh ghi
xc lp ch ngt cho ngt ngoi, quan st hnh 2 trc khi tm hiu thanh ghi
ny.
Hnh 2. Kt ni ngt ngoi cho atmega8.

Gi s chng ta kt ni cc ngt ngoi trn AVR mega8 nh pha tri hnh 2,
cc button dng to ra cc ngt. C 4 kh nng (tm gi l cc MODES) c th xy
ra khi chng ta nhn v th cc button. Nu khng nhn, trng thi cc chn INT l
HIGH do in tr ko ln, khi va nhn 1 button, s c chuyn trng thi t HIGH
sang LOW, chng ta gi l cnh xung - Falling Edge, khi button c nhn v
gi, trng thi cc chn INT c xc nh l LOW v cui cng khi th cc
button, trng thi chuyn t LOW sang HIGH, gi l cnh ln Rising Edge.
Trong nhng trng hp c th, 1 trong 4 MODES trn u hu ch, v d trong
cc ng dng m xung (m encoder ca servo motor chng hn) th 2 MODE
cnh phi c dng. Thanh ghi MCUCR cha cc bits cho php chng ta chn
1 trong 4 MODE trn cho cc ngt ngoi. Di y l cu trc thanh ghi MCUCR
c trch ra t datasheet ca chip atmega8.
MCUCR l mt thanh ghi 8 bit nhng i vi hot ng ngt ngoi, chng ta

ch quan tm n 4 bit thp ca n (4 bit cao dng cho Power manager v Sleep
Mode). Bn bit thp l cc bit Interrupt Sense Control (ISC) trong 2 bit
ISC11:ISC10 dng cho INT1 v 2 bit ISC01:ISC00 dng cho INT0. Hy nhn vo
bng tm tt bn di bit chc nng ca cc bit trn, y l bng chn tr ca
2 bit ISC11, ISC10. Bng chn tr cho cc bit ISC01, ISC00 hon ton tng t.
Bng 2: INT1 Sense Control
Tht d dng hiu chc nng ca cc bit Sense Control, v d bn mun set
cho INT1 l ngt cnh xung (Falling Edge) trong khi INT0 l ngt cnh ln
(Rising Edge), hy t dng lnh MCUCR =0x0B (0x0B = 00001011 nh phn)
trong chng trnh ca bn.
Thanh ghi iu khin ngt chung GICR (General Interrupt Control Register)
(ch trn cc chip AVR c, nh cc chip AT90Sxxxx, thanh ghi ny c tn l
thanh ghi mt n ngt thng thng GIMSK, bn tham kho thm datasheet ca
cc chip ny nu cn s dng n). GICR cng l 1 thanh ghi 8 bit nhng ch c 2
bit cao (bit 6 v bit 7) l c s dng cho iu khin ngt, cu trc thanh ghi nh
bn di (trch datasheet).
Bit 7 INT1 gi l bit cho php ngt 1(Interrupt Enable), set bit ny bng 1
ngha bn cho php ngt INT1 hot ng, tng t, bit INT0 iu khin ngt INT0.
Thanh ghi c ngt chung GIFR (General Interrupt Flag Register) c 2 bit
INTF1 v INTF0 l cc bit trng thi (hay bit c - Flag) ca 2 ngt INT1 v INT0.
Nu c 1 s kin ngt ph hp xy ra trn chn INT1, bit INTF1 c t ng set
bng 1 (tng t cho trng hp ca INTF0), chng ta c th s dng cc bit ny
nhn ra cc ngt, tuy nhin iu ny l khng cn thit nu chng ta cho php
ngt t ng, v vy thanh ghi ny thng khng c quan tm khi lp trnh ngt
ngoi. Cu trc thanh ghi GIFR c trnh by trong hnh ngay bn di.
Sau khi xc lp cc bit sn sng cho cc ngt ngoi, vic sau cng chng ta
cn lm l set bit I, tc bit cho php ngt ton cc, trong thanh ghi trng thi
chung ca chip (thanh ghi SREG, xem li bi AVR2). Mt ch khc l v cc
chn PD2, PD3 l cc chn ngt nn bn phi set cc chn ny l Input (set
thanh ghi DDRD). Qu trnh thit lp ngt ngoi c trnh by trong hnh 10.
Hnh 3. Thit lp ngt ngoi.
Ngt ngoi vi ASM: Di y ti trnh by cch vit chng trnh s dng

ngt ngoi bng ngn ng ASM, i vi cc ngt khc bn ch cn thm cc
DIRECTIVE nh v cc vector ngt tng ng v vit chng trnh phc v
ngt tng ng.
List 1. Ngt vi ASM.
1
.CSEG
2
.INCLUDE "M8DEF.INC"
3
.ORG 0x000 ; nh v v tr u tin
4
RJMP BATDAU
5
6 .ORG 0x001; nh v vector ngt ngoi 0 - INT0 (xem bng vector)
7
RJMP INT0_ISR ; Nhy n INT0_ISR nu c ngt INT0 xy ra
8 .ORG 0x002 ; nh v vector ngt ngoi 1 INT1 (xem bng vector)
9
RJMP INT1_ISR ; Nhy n INT1_ISR nu c ngt INT1 xy ra
10
11 ;Tng t, nh v cc vector ngt khc y..
12 ;..
13 .ORG 0x020 ; nh v chng trnh chnh
14 BATDAU:
15 ; khi to Stack
16
17
18
OUT SPH, R16
19
OUT SPL, R17
20
21 ; set chn PD2 v PD3 nh cc chn input
LDI R16, 0Bxxxx00xx
; x l trng thi do bn t chn, 0 hoc 1
22
OUT DDRD, R16
; PD2 v PD3 l input
23
LDI R16, 0Bxxxx11xx
; x l trng thi do bn t chn, 0 hoc 1
24
OUT PORTD, R16
; mc in tr ko ln cho PD2, PD3
25
26
27 ; khi ng ngt
28
LDI R16, $0B
; $0B=00001011, INT1: ngt cnh xung, INT0: ngt cnh ln
29
OUT MCUCR, R16 ; xut gi tr iu khin ra thanh ghi MCUCR
30
LDI R16, $C0
;$C0=11000000: Enable INT1 v INT0
31
OUT GICR, R16 ;xut gi tr iu khin ra thanh ghi GICR
32
SEI ;set bit cho php ngt ton cc
33 ; Chng trnh chnh
34
MAIN:
35 ;cc cng vic m chng trnh chnh cn thc hin
36 ;.
RJMP MAIN
37
38
;v y l nh ngha trnh phc v ngt INT0_ISR
39
INT0_ISR:
40
; cc cng vic cn thc hin khi c ngt
41
;.
42
RETI ; phi dng lnh RETI quay v chng trnh chnh
43
44 ;v y l nh ngha trnh phc v ngt INT1_ISR
45 INT1_ISR:
46 ; cc cng vic cn thc hin khi c ngt
47 ;.
RETI ; phi dng lnh RETI quay v chng trnh chnh
Bn thy cc cc ngt c nh v nm gia v tr 0x0000, khi mi khi ng,
ti v tr 0x000 l lnh RJMP BATDAU, nh th cc lnh RJMP ti cc vector
ngt v cc ISR u khng c thc hin, chng ch c thc hin mt cch t
ng khi c ngt.
Ngt ngoi vi C: Avr-libc h tr mt th vin hm cho ngt kh hon ho,
s dng ngt trong chng trnh vit bng C (avr-gcc) bn ch cn include file
interrupt.h nm trong th mc con avr l xong. file header interrupt.h cha
nh ngha cc hm v phng thc phc v cho vit trnh phc v ngt, cc vector
ngt khng c nh ngha trong file ny m trong file iom8.h (cho atmega8).
Nu bn v tnh tm thy 1 chng trnh ngt no khng include file interrupt.h
m include file signal.h th bn ng ngc nhin, l cch vit c trong avr-gcc,
tht ra bn hon ton c th s dng cch vit c v cc phin bn mi ca avr-libc
(i cng vi cc bn WinAVR mi) vn h tr cch vit ny nhng khng khuyn
khch bn dng.
Trong C, cc trnh phc v ngt c dng l ISR(vector_name). Trong cc
phin bn c trnh phc v ngt c tn SIGNAL(vector_name), nhng cng nh
file header signal.h, cch vit ny vn c h tr trong phin bn mi nhng
khng c khuyn khch.
List 2. Ngt vi C.
1 #include <avr/interrupt.h>
2
3
4
5
6
ISR (vector_name)
{
//user code here
}
Trong vector_name l tn ca cc vector ngt nh ngha sn avr-libc, ISR l

tn bt buc, bn khng c dng cc tn khc ty (nhng c th dng
SIGNAL nh trnh by trn). c bit, bn c th t ISR trc hoc sau
chng trnh chnh u khng nh hng v tht ra, c kh nhiu cng on
c thc hin khi bn gi ISR (nhng bn khng thy v cng khng cn quan
tm). ISR lun c trnh bin dch t ngoi vng vector ngt nh cch chng
ta thc hin trong ASM, nh th mt chng trnh s dng nhiu loi ngt s phi
c s lng trnh ISR tng ng nhng vi vector_name khc nhau, mi khi c
ngt xy ra, ty thuc vo gi tr ca vector_name m 1 trong cc trnh ISR c
thc thi. i vi cc vector_name, bit c vector_name cho mi loi ngt,
bn cn tham kho ti liu avr-libc manual. Bng 10 tm tt cc vector_name
ca mt s ngt thng dng trn atmega8, bn ch rng cc vector_name trong
avr-libc c nh ngha rt khc nhau cho tng loi chip, bn nht thit phi s
dng ti liu avr-libc manual bit chnh xc cc vector_name cho loi chip m
bn ang dng.
Bng 3: vector_name cho atmega8.
Vector name
Old vector name
Description
ADC_vect
SIG_ADC
ADC Conversion Complete
ANA_COMP_vect
SIG_COMPARATOR
Analog Comparator
EE_RDY_vect
SIG_EEPROM_READY
EEPROM Ready
INT0_vect
SIG_INTERRUPT0
External Interrupt 0
INT1_vect
SIG_INTERRUPT1
External Interrupt Request
SPI_STC_vect
SIG_SPI
Serial Transfer Complete
SPM_RDY_vect
SIG_SPM_READY
Store Program Memory Re
TIMER0_OVF_vect
SIG_OVERFLOW0
Timer/Counter0 Overflow
TIMER1_CAPT_vect
SIG_INPUT_CAPTURE1
Timer/Counter Capture Eve
TIMER1_COMPA_vect
SIG_OUTPUT_COMPARE1A
Timer/Counter1 Compare M
TIMER1_COMPB_vect
SIG_OUTPUT_COMPARE1B
TIMER1_OVF_vect
SIG_OVERFLOW1
TIMER2_COMP_vect
SIG_OUTPUT_COMPARE2
TIMER2_OVF_vect
SIG_OVERFLOW2
TWI_vect
SIG_2WIRE_SERIAL
2-wire Serial Interface
USART3_UDRE_vect
SIG_USART3_DATA
USART3 Data register Emp
III. V d ngt ngoi vi C.

thc hin v d s dng ngt ngoi bng C, ti s vit li chng trnh v d
ca bi "cu trc AVR" nhng bng ngn ng C v s dng ngt. Trong chng
trnh v d ca bi AVR2, chng ta thc hin vic m ln v m xung dng 2
button, chng ta s vn thc hin trn tng ny nhng c cht thay i trong kt
ni, trc ht bn v 1 mch in m phng trong Proteus nh hnh 4.
Hnh 4. Mch in m phng ngt.

Kt ni button m ln vi ngt INT0, button m xung vi INT1, PORTB
c chn lm PORT xut. Hy chyProgrammer Notepad, to 1 Project mi tn
AVR2-INT, type on code bn di vo 1 file new v lu vi tn main.c, add file
ny vo Project ca bn, sau to mt Makefile cho Project.
List 3. v d ngt ngoi bng C.
1
2
3
4
5
6
7
8
#include <avr/io.h>
#include <avr/interrupt.h>
#include <avr/delay.h>
volatile int8_t val=0;
int main(void){
DDRD=0x00;
//khai bo 1 bin val 8 bit, c du v gi tr khi to bng 0.
//khai bo PORTD l Input s dng 2 chn ngt.
9
PORTD=0xFF; //s dng in tr ni ko ln.
10 DDRB=0xFF; //PORTB l Output xut LED 7 on
11
12 MCUCR|=(1<<ISC11)|(1<<ISC01); //c 2 ngt l ngt cnh xung
13 GICR |=(1<<INT1)|(1<<INT0); //cho php 2 ngt hot ng
14 sei();
//set bit I cho php ngt ton cc
15
16 DDRC=0xFF;
//PORTC l Output
17 while (1){
//vng lp v tn
18
PORTC++;
//qut PORTC
19
_delay_loop_2(60000);
20 }
21 return 0;
22 }
23
24 //Trnh phc v ngt ca INT0
25 ISR(INT0_vect){
26 val++;
//nu c ngt INT0 xy ra, tng val thm 1
27 if (val>9) val=0;
//gii hn khng vt qu 9
28 PORTB=val;
29 }
30
31 //Trnh phc v ngt ca INT1
32 ISR(INT1_vect){
33 val--;
//nu c ngt INT1 xy ra, gim val i 1
34 if (val<0) val=9;
//gii hn khng nh hn 0
35 PORTB=val;
36 }
C l on code ny kh d hiu nu cc bn theo di t u bi hc, ti ch
gii thch nhng nt c bn v mi. tng l chng ta s dng 1 bin tm 8
bit, c du lu gi tr m, tn bin val, mi khi c ngt trn chn INT0, tng
val 1 n v v ngc li khi c ngt trn INT1, gim val i 1, l ni dung ca 2
trnh phc v ngt. Trong chng trnh chnh, trc ht chng ta thc hin vic xc
lp hot ng cho 2 ngt, sau a chng trnh vo 1 vng lp v tn while(1),
PORTC c dng kim tra rng chng trnh trong vng lp v tn vn ang
hot ng. C l phn kh hiu nht trong on code l cch m ti dng khai
bo cho 2 thanh ghi iu khin ngt MCUCR v GICR.
Nu xem li bng tm tt cc ton t ca C, ton t << c gi l ton t

dch tri dng trn dng nh phn ca cc con s, nu bn thy x=5<<3 ngha l
dch cc bit nh phn ca 5 sang tri 3 v tr v gn cho x, nh m t nh sau:
Bn thy ton b cc bit ca 5 dch sang tri 3 v tr v gi tr ca s mi

thu c l x=40, ch 40=5x8=5x2^3 . Hy nhn cu lnh MCUCR|
=(1<<ISC11)|(1<<ISC01), gi th bn hiu (1<<ISC11) ngha l dch s 1
sang tri ISC11 v tr, v (1<<ISC01) l dch s 1 sang tri ISC01 v tr, nhng
ISC11 v ISC01 u ra v gi tr ca chng l bao nhiu? Bn ch , khi bn
include file io.h th file iom8.h c chn vo, v trong file ny cha khai
bo a ch cc thanh ghi ca chip atmega8, cc tn bit cng c khai bo sn
trong file ny, nu bn m file iom8.h (thng nm trong th mc
~\WinAVR\avr\include\avr) bng 1 chng trnh text editor nh notepad, dng
chc nng find bn s thy cc dng nh ngha nh sau:
/* MCUCR */
#define SE
#define SM2
#define SM1
#define SM0
#define ISC11
#define ISC10
#define ISC01
#define ISC00
7
6
5
4
3
2
1
0
y l nh ngha v tr cc bit trong thanh ghi MCUCR, vy l r,

ISC11=3, ISC01=1, do : (1<<ISC11) tng ng (1<<3) = 00001000
(Binary) v (1<<ISC01) = 00000010, bn hy tng tng rng bn mang
s 1 n cc v tr ca ISC11 v ISC01 trong thanh ghi MCUCR. By gi n
lt ton t OR bitwise |.
(1<<ISC11)
= 00001000
(1<<ISC01)
= 00000010
-------------------------------------------------(1<<ISC11)|(1<<ISC01) = 00001010
Gn gi tr ny cho MCUCR, i chiu vi bng cc gi tr ca cc bit ISC

(bng 9) bn s thy chng ta ang set cho 2 ngt l falling edge. iu cui cng
ca cu lnh set MCUCR l cch rt gn cu lnh MCUCR|=(1<<ISC11)|
(1<<ISC01) thc cht l MCUCR= MCUCR| ((1<<ISC11)|(1<<ISC01)), y l
cch set mt s bit trong mt thanh ghi m khng mun lm nh hng n cc bit
khc (nhng bn phi tht cn thn vi cch lm ny v c th s phn tc dng
nu bn khng nm r), bn c th gn trc tip MCUCR=(1<<ISC11)|
(1<<ISC01), hay nhanh hn MCUCR=0x0A (0x0A=00001010). Vy l do no
khin ti bin 1 cu lnh gn n gin thnh mt bi ton kh hiu, cu tr li
chnh l tnh tng qut. Trong cc chip AVR khc nhau, v tr cc bit trong cc
thanh ghi l rt khc nhau, cu lnh MCUCR=0x0A ng cho atmega8 nhng
khng p dng c cho cc chip khc trong khi cu lnh MCUCR=(1<<ISC11)|
(1<<ISC01) th hot ng tt, mt l do khc l cch vit gin tip ny gip ngi
khc (hay chnh bn sau ny) khi c code c th d dng hiu c ngi
vit
Ti ngh bn qu hiu dng lnh tip theo, GICR |=(1<<INT1)|(1<<INT0).
Ti dng gii thch on code y v cng dng bi AVR3, bn hy thc tp
bng cch vit li on code trn bng ASM.
Bi 4 - Timer - Counter
5
( 352 Votes )
Ni dung
1.
Gii thiu.

Cu trc AVR.
2.
Tng quan Timer/Counter trn AVR.
3.
S dng Timer/Counter.
WinAVR.
1.
Timer/Counter0
C cho AVR.
2.
Timer/Counter1
M phng vi Proteus.
Download v d
I. Gii thiu.
Trong bi 3 ti gii thiu khi qut phng php lp trnh bng ngn ng C
cho AVR vi WinAVR v cch s dng ngt trong AVR. Bi 4 ny chng ta s
kho st cc ch hot ng ca phng php iu khin cc b nh thi, m
(Timer/Counter) trong AVR. Cng c phc v cho bi ny vn l b cng c
WinAVR v phn mm m phng Proteus. Ti vn dng chip Atmega8 lm v
d. Mt iu khng may mn l khng phi tt c cc b Timer/Counter trn tt c
cc dng chip AVR l nh nhau, v th nhng g ti trnh by trong bi ny c th
s khng ng vi cc dng AVR khc nh AT90STuy nhin ti cng s c gng
ch ra mt s im khc bit c bn cc bn c th t mnh iu khin cc chip
khc. Ni dung bi hc ny bao gm:
Nm bt c bn cc b Timer/Counter c trn AVR.
S dng cc Timer/Counter nh cc b nh thi.
S dng cc Timer/Counter nh cc b m.
S dng cc Timer/Counter nh cc b to xung iu rng PWM.
Vit mt v d iu khin ng c RC servo bng PWM.

II. Tng quan cc b Timer/Counter trn chip Atmega8.
Timer/Counter l cc module c lp vi CPU. Chc nng chnh ca cc b

Timer/Counter, nh tn gi ca chng, l nh th (to ra mt khong thi gian,
m thi gian) v m s kin. Trn cc chip AVR, cc b Timer/Counter cn
c thm chc nng to ra cc xung iu rng PWM (Pulse Width Modulation),
mt s dng AVR, mt s Timer/Counter cn c dng nh cc b canh chnh
thi gian (calibration) trong cc ng dng thi gian thc. Cc b Timer/Counter
c chia theo rng thanh ghi cha gi tr nh thi hay gi tr m ca chng,
c th trn chip Atmega8 c 2 b Timer 8 bit (Timer/Counter0 v Timer/Counter2)
v 1 b 16 bit (Timer/Counter1). Ch hot ng v phng php iu khin ca
tng Timer/Counter cng khng hon ton ging nhau, v d chip Atmega8:
Timer/Counter0: l mt b nh thi, m n gin vi 8 bit. Gi l n gin
v b ny ch c 1 ch hot ng (mode) so vi 5 ch ca b
Timer/Counter1. Ch hoat ng ca Timer/Counter0 thc cht c th coi nh 2
ch nh (v cng l 2 chc nng c bn) l to ra mt khong thi gian v
m s kin. Ch l trn cc chip AVR dng mega sau ny nh
Atmega16,32,64chc nng ca Timer/Counter0 c nng ln nh cc b
Timer/Counter1
Timer/Counter1: l b nh thi, m a nng 16 bit. B Timer/Counter ny
c 5 ch hot ng chnh. Ngoi cc chc nng thng thng, Timer/Counter1
cn c dng to ra xung iu rng PWM dng cho cc mc ch iu khin.
C th to 2 tn hiu PWM c lp trn cc chn OC1A (chn 15) v OC1B (chn
16) bng Timer/Counter1. Cc b Timer/Counter kiu ny c tch hp thm kh
nhiu trong cc chip AVR sau ny, v d Atmega128 c 2 b, Atmega2561 c 4
b
Timer/Counter2: tuy l mt module 8 bit nh Timer/Counter0 nhng
Timer/Counter2 c n 4 ch hot ng nh Timer/Counter1, ngoi ra n n
cn c s dng nh mt module canh chnh thi gian cho cc ng dng thi
gian thc (ch asynchronous).
Trong phm vi bi 4 ny, ti ch yu hng dn cch s dng 4 ch hot
ng ca cc Timer/Counter. Ch asynchronous ca Timer/Counter2 s c b
qua v c th ch ny khng c s dng ph bin.
Trc khi kho st hot ng ca cc Timer/Counter, chng ta thng nht cch gi
tt tn gi ca cc Timer/Counter l T/C, v d T/C0 ch Timer/Counter0
II. S dng Timer/Counter.
C mt s nh ngha quan trng m chng ta cn nm bt trc khi s dng
cc T/C trong AVR:
BOTTOM: l gi tr thp nht m mt T/C c th t c, gi tr ny lun

l 0.
MAX: l gi tr ln nht m mt T/C c th t c, gi tr ny c quy

nh bi bi gi tr ln nht m thanh ghi m ca T/C c th cha c. V d vi
mt b T/C 8 bit th gi tr MAX lun l 0xFF (tc 255 trong h thp phn), vi b
T/C 16 bit th MAX bng 0xFFFF (65535). Nh th MAX l gi tr khng i
trong mi T/C.
TOP: l gi tr m khi T/C t n n s thay i trng thi, gi tr ny

khng nht thit l s ln nht 8 bit hay 16 bit nh MAX, gi tr ca TOP c th
thay i bng cch iu khin cc bit iu khin tng ng hoc c th nhp tr
tip thng qua mt s thanh ghi. Chng ta s hiu r v gi tr TOP trong lc kho
st T/C1.
1. Timer/Counter0:
Thanh ghi: c 4 thanh ghi c thit k ring cho hot ng v iu khin
T/C0, l:
TCNT0 (Timer/Counter Register): l 1 thanh ghi 8 bit cha gi tr vn hnh

ca T/C0. Thanh ghi ny cho php bn c v ghi gi tr mt cch trc tip.
TCCR0 (Timer/Counter Control Register): l thanh ghi iu khin hot ng

ca T/C0. Tuy l thanh ghi 8 bit nhng thc cht ch c 3 bit c tc dng l
CS00, CS01 v CS02.
Cc bit CS00, CS01 v CS02 gi l cc bit chn ngun xung nhp cho T/C0
(Clock Select). Chc nng cc bit ny c m t trong bng 1.
Bng 1: chc nng cc bit CS0X
TIMSK (Timer/Counter Interrupt Mask Register): l thanh ghi mt n cho

ngt ca tt c cc T/C trong Atmega8, trong ch c bit TOIE0 tc bit s 0 (bit
u tin) trong thanh ghi ny l lin quan n T/C0, bit ny c tn l bit cho php
ngt khi c trn T/C0. Trn (Overflow) l hin tng xy ra khi b gi tr trong
thanh ghi TCNT0 t n MAX (255) v li m thm 1 ln na.
Khi bit TOIE0=1, v bit I trong thanh ghi trng thi c set (xem li bi 3 v
iu khin ngt), nu mt trn xy ra s dn n ngt trn.
TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c

cc b T/C. Trong thanh ghi ny bit s 0, TOV0 l c ch th ngt trn ca T/C0.
Khi c ngt trn xy ra, bit ny t ng c set ln 1. Thng thng trong iu
khin cc T/C vai tr ca thanh ghi TIFR khng qu quan trng.
Hot ng: T/C0 hot ng rt n gin, hot ng ca T/C c kch bi
mt tn hiu (signal), c mi ln xut hin tn hiu kch gi tr ca thanh ghi
TCNT0 li tng thm 1 n v, thanh ghi ny tng cho n khi n t mc MAX l
255, tn hiu kch tip theo s lm thanh ghi TCNT0 tr v 0 (trn), lc ny bit c
trn TOV0 s t ng c set bng 1. Vi cch thc hot ng nh th c v
T/C0 v dng v c tng t 0 n 255 ri li quay v 0, v qu trnh lp li. Tuy
nhin, yu t to s khc bit chnh l tn hiu kch v ngt trn, kt hp 2 yu t
ny chng ta c th to ra 1 b nh thi gian hoc 1 b m s kin. Trc ht
bn hy nhn li bng 1 v cc bit chn xung nhp cho T/C0. Xung nhp cho T/C0
chnh l tn hiu kch cho T/C0. Xung nhp ny c th to bng ngun to dao ng
ca chip (thch anh, dao ng ni trong chip). Bng cch t gi tr cho cc bit
CS00, CS01 v CS02 ca thanh ghi iu khin TCCR0, chng ta s quyt nh bao
lu th s kch T/C0 mt ln. V d mch ng dng ca bn c ngun dao ng clk
= 1MHz tc chu k 1 nhp l 1us (1 micro giy), bn t thanh ghi TCCR0=5 (tc
SC02=1, CS01=0, CS00=1). Cn c theo bng 1, tn hiu kch cho T/C0 s bng
clk/1024 ngha l sau 1024us th T/C0 mi c kch 1 ln, ni cch khc gi tr
ca TCNT0 tng thm 1 sau 1024us (ch l tn s c chia cho 1024 th chu k
s tng 1024 ln). Quan st 2 dng cui cng trong bng 1 bn s thy rng tn hiu
kch cho T/C0 c th ly t bn ngoi (External clock source), y chnh l tng
cho hot ng ca chc nng m s kin trn T/C0. Bng cch thay i trng thi
chn T0 (chn 6 trn chip Atmega8) chng ta s lm tng gi tr thanh ghi TCNT0
hay ni cch khc T/C0 c th dng m s kin xy ra trn chn T0. Di y
chng ta s xem xt c th cch iu khin T/C0 theo 1 ch nh thi gian v
m.
1.1 B nh thi gian.
Chng ta c th to ra 1 b nh th ci t mt khong thi gian no . V
d bn mun rng c sau chnh xc 1ms th chn PB0 thay i trng thi 1 ln
(nhp nhy), bn li khng mun dng cc lnh delay nh trc nay vn dng v
nhc im ca delay l CPU khng lm g c trong lc delay, v th trong nhiu
trng hp cc lnh delay rt hn ch c s dng. By gi chng ta dng T/C0
lm vic ny, tng l chng ta cho b m T/C0 hot ng, khi n m
1ms th n s t kch hot ngt trn, trong trnh phc v ngt trn chng tat hay i
trng thi chn PB0. Ti minh ha tng nh trong hnh 1.
Hnh 1. So snh 2 cch lm vic.

(CPU nop: trong khong thi gian ny CPU khng lm g c)
Mt vn ny sinh lc ny, nh ti trnh by trong phn trc, T/C0 ch m
t 0 n 255 ri li quay v 0 (xy ra 1 ngt trn), nh th dng nh chng ta
khng th ci t gi tr mong mun bt k cho T/C0? Cu tr li l chng ta c
th bng cch gn trc mt gi tr cho thanh ghi TCNT0, khi y T/C0 s m t

gi tr m chng ta gn trc v kt thc 255. Tuy nhin do khi trn xy ra,
TCNT0 li c t ng tr v 0, do vic gn gi tr khi to cho TCNT0 phi
c thc hin lin tc sau mi ln xy ra trn, v tr tt nht l t trong trnh
phc v ngt trn.
Vic cn li v cng l vic quan trng nht l vic tnh ton gi tr chia
(prescaler) cho xung nhp ca T/C0 v vic xc nh gi tr khi u cn gn cho
thanh ghi TCNT0 c c 1 khong thi gian nh th chnh xc nh mong
mun. Trc ht chng ta s chn prescaler sao cho hp l nht (chn gi tr chia
bng cch set 3 bit CS02,CS01,CS00). Gi s ngun xung clock nui chip ca
chng ta l clkI/O=1MHz tc l 1 nhp mt 1us, nu chng ta prescaler=1, tc l
tn s ca T/C0 (tm gi l fT/C0) cng bng clkI/O=1MHz, c 1us T/C0 c
kch v TCNT0 s tng 1 n v. Khi gi tr ln nht m T/C0 c th t c l
256 x 1us=256us, gi tr ny nh hn 1ms m ta mong mun. Nu chn
prescaler=8 (xem bng 1) ngha l c sau 8 nhp (8us) th TCNT0 mi tng 1 n
v, kh nng ln nht m T/C0 m c l 256 x 8us=2048us, ln hn 1ms, vy ta
hon ton c th s dng prescaler=8 to ra mt khong nh th 1ms. Bc tip
theo l xc nh gi tr khi u ca TCNT0 T/C0 m ng 1ms (1000us). ng
vi prescaler=8 chng ta bit l c 8us th TCNT0 tng 1 n v, d dng tnh
c b m cn m 1000/8=125 ln ht 1ms, do gi tr ban u ca
TCNT0 phi l 256-125=131. Bn c th quan st hnh 2 hiu thu o hn.
Hnh 2. Qu trnh thc hin.

Hy to 1 Project bng Programmer Notepad vi tn gi TIMER0 v vit on
code cho Project ny nh trong list 1.
List 1. nh th 1ms vi T/C0.
1 #include <avr/io.h>
3 #include <util/delay.h>
4
5 int main(void){
6
DDRB=0xFF;
//PORTB la output PORT
7
PORTB=0x00;
8
9
TCCR0=(1<<CS01);// CS02=0, CS01=1, CS00=0: chon Prescaler = 8
10
TCNT0=131;
//gan gia tri khoi tao cho T/C0
11
TIMSK=(1<<TOIE0);//cho phep ngat khi co tran o T/C0
12
sei();
//set bit I cho phep ngat toan cuc
13
14
while (1){
//vng lp v tn
15
//do nothing
16
}
17
return 0;
18 }
19
20 //trinh phuc vu ngat tran T/C0
21 ISR (TIMER0_OVF_vect ){
22
TCNT0=131; //gan gia tri khoi tao cho T/C0
23
PORTB^=1; //doi trang thai Bit PB0
24 }
on code rt n gin, bn ch cn ch n 3 dng khai bo cho T/C0
(dng 9, 10, 11). Vi dng 9: TCCR0=(1<<CS01) l 1 cch set bit CS01 trong
thanh ghi iu khin TCCR0 ln 1, 2 bit CS02 v CS00 c gi tr 0 (bn xem
li bi 3 v cch set cc bit c bit trong cc thanh ghi), tm li dng ny tng
ng TCCR0=2, gi tr Prescaler c chn bng 8 (tham kho bng 1). Dng 10
chng ta gn gi tr khi to cho thanh ghi TCNT0. V dng 11 set bit TIOE0 ln 1
cho php ngt xy ra khi c trn T/C0. Trong trnh phc v ngt trn T/C0,
chng ta s thc hin i trng thi chn PB0 bng ton t XOR (^), ch n
ngha ca ton t XOR: nu XOR mt bit vi s 1 th bit ny s chuyn trng thi
(t 0 sang 1 v ngc li). Cui cng v quan trng l chng ta cn gn li gi tr
khi
to
cho
T/C0.
Bn c th v mt mch in m phng n gin dng 1 Oscilloscope nh
trong hnh 3 kim tra hot ng ca on code.
Hnh 3. M phng nh th ca T/C0.

1.2 B m s kin.
Nh ti trnh by trong phn hot ng ca T/C0, chng ta c th dng T/C0
nh mt b m (counter) m cc s kin (s thay i trng thi) xy ra trn
chn T0. Bng cch t gi tr cho thanh ghi TCCR0 = 6 (CS02=1, CS01=1,
CS00=0) cho php m cnh xung trn chn T0, nu TCCR0 = 7 (CS02=1,
CS01=1, CS00=1) th cnh ln trn chn T0 s c m. C s dng ngt hay
khng ph thuc vo mc ch s dng. Kho st 1 v d n gin gn ging vi v
d m trong bi AVR2 nhng s dng T/C0 v ch m 1 chiu tng. Kt ni
mch in nh trong hnh 4, mi ln Button 1 c nhn, gi tr m tng thm 1.
Button 2 dng reset gi tr m v 0. on code cho v d th 2 ny c trnh by
trong List 2.
Hnh 4. m 1 chiu bng T/C0.

List 2. m s kin vi T/C0
3
4 int main(void){
5
DDRB=0xFF;
6
PORTB=0x00;
7
DDRD=0x00; //khai bao PORTD la input de ket noi Button kich vao chan T0
8
PORTD=0xFF; //su dung dien tro keo len cho PORTD
9
10
TCCR0=(1<<CS02)|(1<<CS01);// CS02=1, CS01=1, CS00=0: xung nhip tu chan T0, do
11
TCNT0=0;
12
13
while (1){
//vng lp v tn
14
if (TCNT0==10) TCNT0=0;
15
PORTB=TCNT0; //xuat gia tri dem ra led 7 doan
16
if (bit_is_clear(PIND,7)) TCNT0=0; //Reset bo dem neu chan PD7=0
17
}
18
return 0;
19 }
Ni dung trong chng trnh chnh l khai bo cc hng giao tip cho cc
PORT, PORTB l ouput xut kt qu m ra led 7 on, PORTD c khi bo
input v cc button c ni vi PORT ny. T/C0 c khai bo s dng ngun
kch ngoi t T0, dng cnh xung thng qua dng TCCR0=(1<<CS02)|
(1<<CS01), bn cng c th khai bo tng ng l TCCR0=6 (tham kho bng
1). Gi tr ca b m s c xut ra PORTB kim tra. im ch trong on
chng trnh ny l macro bit_is_clear, y l mt macro c nh ngha trong
file sfr_defs.h dng kim tra 1 bit trong mt thanh ghi c bit c c xa
(bng 0) hay khng, trong trng hp ca on code trn:
if(bit_is_clear(PIND,7)) TCNT0=0; ngha l kim tra xem nu chn PD7 c
ko xung 0 (button 2 c nhn) th s reset b m v 0.
Nh vy vic s dng T/C0 l tng i n gin, bn ch cn khai bo cc
gi tr thch hp cho thanh ghi iu khin TCCR0 bng cch tham kho bng 1, sau
khi to gi tr cho TCNT0 (nu cn thit), khai bo c s dng ngt hay khng
bng cch set hay khng set bit TOIE0 trong thanh ghi TIMSK l hon tt.
2. Timer/Counter1:
Timer/Counter1 l b T/C 16 bits, a chc nng. y l b T/C rt l tng
cho lp trnh o lng v iu khin v c phn gii cao (16 bits) v c kh
nng to xung iu rng PWM (Pulse Width Modulation thng dng iu
khin ng c).
Thanh ghi: c kh nhiu thanh ghi lin quan n T/C1. V l T/C 16 bits trong
khi rng b nh d liu ca AVR l 8 bit (xem li bi 2) nn i khi cn dng
nhng cp thanh ghi 8 bits to thnh 1 thanh ghi 16 bit, 2 thanh ghi 8 bits s c tn
kt thc bng cc k t L v H trong L l thanh ghi cha 8 bits thp (LOW) v
H l thanh ghi cha 8 bits cao (High) ca gi tr 16 bits m chng to thnh.
TCNT1H v TCNT1L (Timer/Counter Register): l 2 thanh ghi 8 bit to

thnh thanh ghi 16 bits (TCNT1) cha gi tr vn hnh ca T/C1. C 2 thanh ghi
ny cho php bn c v ghi gi tr mt cch trc tip. 2 thanh ghi c kt hp
nh sau:
TCCR1A v TCCR1B (Timer/Counter Control Register): l 2 thanh ghi iu

khin hot ng ca T/C1. Tt c cc mode hot ng ca T/C1 u c xc nh
thng qua cc bit trong 2 thanh ghi ny. Tuy nhin, y khng phi l 2 byte cao v
thp ca mt thanh ghi m l 2 thanh ghi hon ton c lp. Cc bit trong 2 thanh
ghi ny bao gm cc bit chn mode hay chn dng sng (Waveform Generating
Mode WGM), cc bit quy nh dng ng ra (Compare Output Match COM),
cc bit chn gi tr chia prescaler cho xung nhp (Clock Select CS)Cu trc
ca 2 thanh ghi c trnh by nh bn di.
Nhn chung thuc ht cch phi hp cc bit trong 2 thanh ghi TCCR1A
v TCCR1B l tng i phc tp v T/C1 c rt nhiu mode hot ng, chng ta
s kho st chng trong phn cc ch hot ng ca T/C1 bn di. y,
trong thanh ghi TCCR1B c 3 bit kh quen thuc l CS10, CS11 v CS12. y l
cc bit chn xung nhp cho T/C1 nh truong T/C0. Bng 2 s tm tt cc ch
xung nhp trong T/C1.
Bng 2: chc nng cc bit CS12, CS11 v CS10.
OCR1A v OCR1B (Ouput Compare Register A v B): c mt s khi nim

mi m chng ta cn bit khi lm vic vi T/C1, mt trong s l Ouput
Compare (sorry, I dont wanna translate it to Vietnamese). Trong lc T/C hot
ng, gi tr thanh ghi TCNT1 tng, gi tr ny c lin tc so snh vi cc thanh
ghi OCR1A v OCR1B (so snh c lp vi tng thanh ghi), vic so snh ny trn
AVR gi l gi l Ouput Compare. Khi gi tr so snh bng nhau th 1 Match xy
ra, khi mt ngt hoc 1 s thay i trn chn OC1A (hoc/v chn OC1B) xy
ra (y l cch to PWM bi T/C1). Ti sao li c A v B? l v ngi thit k
AVR mun m rng kh nng ng dng T/C1 cho bn. A v B i din cho 2 knh
(channel) v B. Cng v iu ny m chng ta c th to 2 knh PWM bng T/C1.
Tm li, c bn 2 thanh ghi ny cha cc gi tr so snh, chc nng v cc ch
hot ng c th ca chng s c kho st trong cc phn sau.
ICR1 (InputCapture Register 1): khi nim mi th 2 ca T/C1 l Input

Capture. Khi c 1 s kin trn chn ICP1 (chn 14 trn Atmega8), thanh ghi
ICR1s capture gi tr ca thanh ghi m TCNT1. Mt ngt c th xy ra trong
trng hp ny, v th Input Capture c th c dng cp nht gi tr TOP
ca T/C1.
TIMSK (Timer/Counter Interrupt Mask Register): cc b T/C trn AVR

dng chung thanh ghi mt n ngt, v th TIMSK cng c dng quy nh ngt
cho T/C1. C iu lc ny chng ta ch quan tm n cc bit t 2 n 5 ca
TIMSK. C tt c 4 loi ngt trn T/C1 (nh li T/C0 ch c 1 loi ngt trn)
Bit 2 trong TIMSK l TOIE1, bit quy nh ngt trn cho thanh T/C1 (tng t
trng hp ca T/C0).
Bit 3, OCIE1B l bit cho php ngt khi c 1 Match xy ra trong vic so snh
TCNT1 vi OCR1B.
Bit 4, OCIE1A l bit cho php ngt khi c 1 Match xy ra trong vic so snh
TCNT1 vi OCR1A.
Bit 5, TICIE1 l bit cho php ngt trong trng hp Input Capture c dng.
Cng vi vic set cc bit trn, bit I trong thanh ghi trng thi phi c set nu
mun s dng ngt (xem libi 3 v iu khin ngt).
TIFR (Timer/Counter Interrupt Flag Register): l thanh ghi c nh cho tt c

cc b T/C. Cc bit t 2 n 5 trong thanh ghi ny l cc c trng thi ca T/C1.
Cc mode hot ng: c tt c 5 ch hot ng chnh trn T/C1. Cc ch

hot ng c bn c quy nh bi 4 bit Waveform Generation Mode (WGM13,
WGM12, WGM11 WGM10) v mt s bit ph khc. 4 bit Waveform Generation
Mode li c b tr nm trong 2 thanh ghi TCCR1A v TCCR1B (WGM13 l bit
4, WGM12 l bit 3 trong TCCR1B trong khi WGM11 l bit 1 v WGM10 l bit 0
trong thanh ghi TCCR1A) v th cn phi hp 2 thanh ghi TCCR1 trong lc iu
khin T/C1. Cc ch hot ng ca T/C1 c tm tt trong bng sau 3:
Bng 3: cc bit WGM v cc ch hot ng ca T/C1.
2.1
Normal
mode
(Ch
thng).
y l ch hot ng n gin nht ca T/C1. Trong ch ny, thanh ghi
m TCNT1 c tng gi tr t 0 (BOTTOM) n 65535 hay 0xFFFF (TOP) v
quay v 0. Ch ny hon ton ging cch m Timer0 hot ng ch c khc l

gi tr m cao nht l 65535 thay v 255 nh trong timer0. Nhn vo bng 3, set
T/C1 Normal mode chng ta cn set 4 bit WGM v 0, v 0 l gi tr mc nh ca
cc thanh ghi nn thc t chng ta khng cn tc ng n cc bit WGM. Duy nht
mt vic quan trng cn lm l set cc bit Clock Select (CS12, SC11, CS10) trong
thanh ghi TCCR1B (xem thm bng 2). Bn c th tham kho v d ca Timer0.
on code trong list 3 l 1 v d to 1 khong thi gian 10ms bng T/C1, normal
mode:
List 3. nh th 10ms vi T/C1.
4
5 int main(void){
6
DDRB=0xFF;
7
PORTB=0x00;
8
9
TCCR1B=(1<CS10);// CS12=0, CS11=0, CS10=1: chon Prescaler =1
10
// thanh ghi TCCR1B duoc dung thay vi TCCR0 cua Timer0
11
TCNT1=55535;
//gan gia tri khoi tao cho T/C1
12
TIMSK=(1<<TOIE1);//cho phep ngat khi co tran o T/C1
13
sei();
14
15
while (1){
//vng lp v tn
16
//do nothing
17
}
18
return 0;
19 }
20 //trinh phuc vu ngat tran T/C1
21 ISR (TIMER1_OVF_vect ){
22
TCNT1=55535; //gan gia tri khoi tao cho T/C1
23
PORTB ^=1; //doi trang thai Bit PB0
24 }
2.2 Clear Timer on Compare Match (xa timer nu xy ra bng trong so snh)CTC.
Mt cch gi tt ca ch hot ng ny l CTC, mt ch hot ng mi
trn T/C1. Nhn vo bng 3 bn s thy c 2 mode CTC (mode 4 v mode 12). Ti
ly v d mode 4 gii thch hot ng ca CTC. Khi bn set cc bit Waveform
Generation Mode tuong ng: WGM13=0, WGM12=1, WGM11=0, WGM10=0 th
mode 4 c chn. Trong mode ny, thanh ghi OCR1A cha gi tr TOP (gi tr so
snh do ngi dng t), thanh ghi m TCNT1 tng t 0, khi TCNT1 bng gi tr
cha trong OCR1A th mt Compare Match xy ra. Khi , mt ngt c th xy
ra nu chng ta cho php ngt Compare Match (set bit OCF1A trong thanh ghi
TIMSK ln 1). Mode ny cng tng i n gin, mt ng dng c bn ca mode
ny l n gin ha vic m cc s kin bn ngoi. V d bn kt ni 1 sensor
m s ngi i vo 1 cn phng vi chn T1 (chn counter source ca T/C1), bn
mun rng c sau khi m 5 ngi th s thng bo 1 ln. List 4 l on code m t
v d ny:
List 4. Phi hp CTC vi m s kin.
4 volatile usigned char val=0; //khai bao 1 bien tam val va khoi tao =0
5 int main(void){
6
DDRB=0xFF;
7
PORTB=0x00;
8
TCCR1B=(1<<WGM12)|(1<<CS12)|(1<<CS11); //xung nhip tu chan T1, canh xuong
9
OCR1A=4;
//gan gia tri can so sanh
10
TIMSK=(1<OCIE1A);//cho phep ngat khi gia tri dem bang 4
11
sei();
12
13
while (1){
//vng lp v tn
14
//do nothing
15
}
16
return 0;
17 }
18 //trinh phuc vu ngat compare match
19 ISR (TIMER1_COMPA_vect){
20
val++;
21
if (val==10) val=0; //gioi han bien val tu 0 den 9
22
PORTB =val;
//xuat gia tri ra PORTB
23 }
Ti ch gii thch nhng im mi trong List 4. Th nht l attribute volatile
dng trc khai bo bin val, bin val c khai bo l unsigned char (8 bit, khng
du) dng cha gi tr tm thi xut ra PORTB khi c ngt xy ra. iu c bit
l t kha volatile t trc n, volatile l mt thuc tnh (attribute) ca b bin
dch gcc-avr, n ni vi trnh dch rng bin val s c dng trong chng trnh
chnh v c trong cc trnh phc v ngt. Nu bn mun cp nhp gi tr 1 bin
ton cc trong cc trnh phc v ngt m bin khng c ch nh thuc tnh
volatile trc th qu trnh cp nht tht bi. Mt cch d hiu hn, bn xem trnh
ISR trong v d trn, c mi ln c ngt Compare Match xy ra, bin val c tng
thm 1 (dng 21) sau kim tra iu kin bng 10 hay khng v cui cng l gn
cho PORTB. Nu trong khai bo ca val (dng 4) chng ta khng ch nh volatile
th gi tr xut ra PORTB s lun l 1 khi c ngt. Ch l iu ny ch ng it
nht l vi phin bn WinAVR thng 12 nm 2007, cc phin bn sau c th khng
cn dng volatile (ti s cp nht sau).
Dng 8 set cc bit iu khin: TCCR1B=(1<<WGM12)|(1<<CS12)|
(1<<CS11); bn thy ti ch set bit WGM12 trong 4 bit WGM v ti mun chn
mode CTC 4 (xem bng 3). Hai bit CS12 v CS11 c set bng 1 trong khi CS10
c gi 0 chn xung clock l t bn ngoi, chn T1 (xem bng 2). Trong
dng 10, OCR1A=4; l gi tr cn so snh, chng ta bit rng TCNT1 tng ln t 0,
v th m 5 s kin th cn t gi tr so snh l 4 (0, 1, 2, 3, 4). Dng 11 set bit
cho php ngt khi c Compare match xy ra (dng cho channel A).
Mode 12 ca CTC (WGM13=1, WGM12=1, WGM11=0, WGM10=0) cng
tng t mode 4 nhng ci khc l gi tr cn so snh c cha trong thanh ghi
ICR1 (khng phi OCR1A hay OCR1B). Khi nu mun dng ngt th bn phi
dng ngt Input capture. C th dng 8 trong list 4 i thnh:
TCCR1B=(1<<WGM13)|( (1<<WGM12)|(1<<CS12)|(1<<CS11); dng 10:
ICR1=4 v dng 20: ISR (TIMER1_CAPT_vect ){
Mt kh nng khc ca CTC l xut tn hiu xung vung trn chn OC1A
(chn 15 trn Atmega8) bng cch set cc bit Compare Output Mode trong thanh
ghi TCCR1A. Tuy nhin vic to cc tn hiu output trong mode CTC khng tht
s th v. V vy chng ta s kho st cch to tn hiu output trong 1 ch
chuyn nghip v th v hn, ch PWM.
Trc khi bt u lm vic vi cc ch PWM ti ngh cn thit gii thiu
th no l PWM v nhc li cc khi nim gi tr m ca Timer1 (hay bt k timer
no khc) trn AVR. Trc ht, PWM hay Pulse Width Modulation c hiu theo
ngha ting Vit l xung iu rng l khi nim ch tn hiu xung m thng th
chu k (Time period) ca n c c nh, duty cycle (thi thi gian tn hiu
mc HIGH) ca n c th c thay i. Bn xem 1 v d v PWM trong hnh 5.
Hnh 5. V d v tn hiu PWM.

To ra PWM tc l to ra nhng tn hiu xung m ta c th iu khin duty
cycle (v c tn s ~ Time period nu cn thit). Timer 1 trsn Atmega8 l 1
module l tng to ra cc tn hiu dng ny. Nhng PWM dng lm g v
cch m n c s dng nh th no? Ti ly mt v d nh trong hnh 6: mt
ng c DC v mt switch button.
Hnh 6. Motor v switch.

Nu nhn button th ng c hot ng, th button th ng c dng. Tuy
nhin do tc nhn v th ca con ngi c hn, bn s thy ng c hot ng
hi sng (ripple). iu g xy ra nu bn nhn v th button vi vn tc 5000
ln/giy. Cu tr li l tay bn s b gy v button s b hng (^^). 5000 ln/s l
iu khng tng, tuy nhin nu bn lm c nh th th tng thi gian cho 1 ln
nhn+th l 1:5000=0.0002s = 200us. C s khc bit no khng gia trng hp
thi gian nhn = 150us, thi gian th 50us v trng hp thi gian nhn l 50us
cn thi gian th l 150us. Bn s d dng tm cu tr li, trong trng hp 1 ng
c s quay vi vn tc nhanh hn trng hp 2. l tng c bn s dng
PWM iu khin vn tc ng c (v iu khin nhiu th khc na). bin ci
khng tng trn (5000 ln/s) thnh hin thc, chng ta s thay th ci button c
kh kia bng 1 cng tc in t (electronics switch). Thng th cc chip MOSFET
c dng lm cc kha in t. MOSFET thng c 3 chn G (gate), D (drain) v
S (source). V d 1 MOSFET knh N trng thi thng thng 2 chn D v S ko
c dng in chy qua, nu in p chn G ln hn chn S khong 3V tr ln th
dng in c th chy t D sang S. hy xem cch m t tng ng 1 MOSFET
vi 1 button trong hnh 7.
Hnh 7. MOSFET v button.

Vic kch cc MOSFET c th thc hin bng cc tn hiu PWM. V th
tng iu khin ng c trong hnh 6 c th c thc hin li thng qua PWM
nh trong hnh 8.
Hnh 8. M hnh iu khin tc ng c bng PWM n gin.

Nh vy l xong phn gii thiu v PWM, by gi chng ta sang cc khi
nim s m trong Timer. Hnh 9 minh ha cch b tr cc s m trong Timer1
trn h trc m.
Hnh 9: cc mc gi tr ca T/C1.
BOTTOM lun c c nh l 0 (gi tr nh nht), MAX lun l 0xFFFF
(65535). TOP l gi tr nh do ngi dng nh ngha, gi tr ca TOP c th c
c nh l 0xFF (255), 0x1FF (511), 0x3FF 91023) hoc nh ngha bi cc thanh
ghi ICR1 hoc OCR1A. thc cht i vi ng dng PWM th TOP chnh l Time
period ca PWM. Do mc ch s dng m c th chn TOP l cc gi tr c nh
hay cc thanh ghi, ring vi ti, cho mc ch to tn hiu PWM ti chn TOP nh
ngha bi thanh ghi ICR1. Ouput Compare l gi tr so snh ca b Timer. Trong
ch PWM th Output Compare quy nh Duty cycle. Vi T/C1, Output Comapre
l gi tr trong cc thanh ghi OCR1A v OCR1B. Do c 2 thanh ghi c lp A v
B, tng ng chng ta c th to ra 2 tn hiu PWM trn 2 chn OC1A v OC1B
bng T/C1. n lc chng ta tm hiu cch to PWM trn AVR.
2.3
Fast
PWM
(PWM
tn
s
cao).
Trong ch Fast PWM, 1 chu k c tnh trong 1 ln m t BOTTOM ln
TOP (single-slope), v th m ch ny gi l Fast PWM (PWM nhanh). C tt

c 5 mode trong Fast PWM tng ng vi 5 cch chn gi tr TOP khc nhau
(tham kho bng 3). Vic xc lp ch hot ng cho Fast PWM thc hin thng
qua 4 bit WGM v cc bit chn dng xung ng ra, Compare Output Mode trong
thanh ghi TCCR1A, nhn li 2 thanh ghi TCCR1A v TCCR1B.
Ch cc bit COM1A1, COM1A0 v COM1B1, COM1B0 l cc bit chn

dng tn hiu ra ca PWM (Compare Output Mode bits). COM1A1, COM1A0
dng cho knh A v COM1B1, COM1B0 dng cho knh B. Hy i chiu bng 4.
Bng 4: m t cc bit COM trong ch fast PWM.
Ti s gii thch hot ng ca Fast PWM knh A thng qua 1 trng hp c

th, mode 14 (WGM13=1, WGM12=1, WGM11=1, WGM10=0). Trong mode 14,
gi tr TOP (cng l chu k ca PWM) c cha trong thanh ghi ICR1, khi hot
ng thanh ghi TCNT1 tng gi tr t 0, gi s cc bit ph COM1A=1,
COM1A0=0, lc ny trng thi ca chn OC1A (chn 15) l HIGH (5V), khi
TCNT1 tng n bng gi tr ca thanh ghi OCR1A th chn OC1A c xa v
mc LOW (0V), thanh ghi m TCNT1 vn tip tc tng n khi no n bng gi
tr TOP cha trong thanh ghi ICR1 th TCNT1 t ng reset v 0 v chn OC1A
tr v trng thi HIGH, ci ny gi l Clear OC1A/OC1B on Compare Match, set
OC1A/OC1B at TOP m bn thy trong hng 4 bng 4. Hnh 10 m t cch to
xung PWM trn chn OC1A mode 14.
Hnh 10: Fast PMW mode 14.
R rng chng ta c th iu khin c time period v duty cycle ca PWM

bng 2 thanh ghi ICR1 v OCR1A. Thng thng gi tr ca ICR1 c tnh ton
v gn c nh, gi tr ca OCR1A c thay i thc hin mc ch iu khin
(nh thay i vn tc ng c). Ch l nu chng ta set cc bit ph ngc li:
COM1A=0, COM1A0=1, th tn hiu PWM trn chn OC1A s c phn LOW t
0 n OCR1A v HIGH t OCR1A n ICR1, y gi l set OC1A/OC1B on
Compare Match, clear OC1A/OC1B at TOP (ngc vi tn hiu trn hnh 10).
Hot ng ca fast PWM knh B hon ton tng t, trong thanh ghi ICR1
cng cha TOP ca PWM knh B v thanh ghi ICR1B cha duty cycle. Nh vy 2
knh A v B c cng tn s hay Time period v duty cycle c iu khin c
lp. Chn xut tn hiu PWM ca knh B l chn OC1B (chn 16 trn Atmega8).
Cc mode 5, 6 v 7 ca Fast PWM hot ng hon ton tng t mode 14. im
khc nhau c bn l gi tr TOP(Time period). Trong cc mode ny gi tr TOP
khng do thanh thi ICR1 nh ngha m l cc hng s khng i. Vi mode 5, tc
mode 8 bits, (WGM13=0, WGM12=1, WGM11=0, WGM10=1) gi tr TOP l 1
hng s, TOP = 255 (s 8 bits ln nht). Vi mode 6, tc mode 9 bits, (WGM13=0,
WGM12=1, WGM11=1, WGM10=0) gi tr TOP l 1 hng s, TOP = 511 (s 9
bits ln nht). V vi mode 7, tc mode 10 bits, (WGM13=0, WGM12=1,
WGM11=1, WGM10=1) TOP =1023 (s 10 bits ln nht). Mode 15 cng l Fast
PWM trong TOP do OCR1A quy nh, v th m tn hiu ra knh A hu nh
khng phi l 1 xung, n ch thay i trng thi trong 1 clock. Theo ti, s dng
Fast PWM bn nn dng mode 14 c gii thch trn. Cc mode 5, 6, 7 cng
c
th
dng
nhng
khng
nn
dng
mode
15.
Chng ta tin hnh vit 1 v d minh ha dng 2 knh ch fast PWM iu
khin 2 ng c RC servo (gi tt l Servo). Mch in minh ha nh trong hnh
11.
Hnh 11: iu khin 2 RC servo bng PWM.
Hai button c ni vi 2 ng ngt ngoi INT0 v INT1 iu khin gc

xoay ca 2 Servo. Tn ca Servo trong phn mm Proteus l MOTORPWMSERVO. Trc khi vit code iu khin cc Servo, bn cn bit cch iu
khin chng, ti gii thiu ngn gn nh sau:
RC servo l mt t hp gm 1 ng c DC cng sut nh, hp gim tc v b
iu khin gc quay. C 2 loi chnh l Servo thng v digital Servo, trong v d
ny ti gii thiu Servo thng (ph bin). Servo thng c 3 dy, dy mu en l
dy GND, dy l dy ngun (thng l 5V) v 1 dy trng hoc vng v dy
iu khin (c mt s loi Servo c mu dy khc, bn cn tham kho datasheet
ca chng). V cc Servo c sn mch iu khin gc quay bn trong nn chng
ta khng cn bt c gii thut g m ch cn cp tn hiu PWM cho dy iu khin
l Servo c th xoay n 1 v tr no (ch l Servo thng ch xoay na vng,
iu khin servo l iu khin gc xoay ch khng phi iu khin cn tc xoay).
Hnh 12 l hnh nh servo v cch iu khin servo.
Hnh 12. Servo v cch iu khin.

Bn xem hnh 12b, iu khin servo bn cn cp cho dy iu khin mt tn
hiu PWM c Time Period khong 20ms, duty cycle ca PWM s quyt nh gc
xoay ca servo. Vi Duty cycle l 1ms, servo xoay v v tr 0o, khi duty cycle
=2ms, gc xoay s l 180o, t bn c th tnh c duty cycle cn thit khi bn
mun servo xoay n 1 v tr bt k gia 0o v 180o. Sau khi hiu cch iu khin
servo, chng ta c th d dng vit code iu khin chng, ch cn to cc xung
PWM bng T/C1. on code cho v d ny c trnh by trong list 5.
List 5. iu khin Servo bng PWM.
3
4 int main(void){
5
DDRB=0xFF;
6
PORTB=0x00;
7
8
MCUCR|=(1<<ISC11)|(1<<ISC01); //ngat canh xuong
9
GICR |=((1<<INT1)|(1<<INT0); //cho php 2 ngat hoat dong
10
11
TCCR1A=(1<<COM1A1)|(1<<COM1B1)|(1<<WGM11);
12
TCCR1B=(1<<WGM13)|(1<<WGM12)|(1<<CS10);
13
OCR1A=1000;
//Duty cycle servo1=1000us=1ms (0 degree)
14
OCR1B=1500;
//Duty cycle servo2=1500us=1.5ms (90 degree)
15
ICR1=20000;
//Time period = 20000us=20ms
16
17
sei();
18
while (1){
//vng lp v tn
19
//do nothing
20
}
21
return 0;
22 }
23
24 //trinh phuc vu ngat ngoai
25 ISR (INT0_vect ){
26
if (OCR1A==1000) OCR1A=1500; //thay doi goc xoay servo1 den 90 do
27
else OCR1A = 1000; // thay doi goc xoay servo1 den 0 do
28 }
29 ISR (INT1_vect ){
30
if (OCR1B==1000) OCR1B=1500; //thay doi goc xoay servo1 den 90 do
31
else OCR1B = 1000; // thay doi goc xoay servo1 den 0 do
32 }
Vi v d ny ti ch cn gii thch cc dng t 11 n 15 lin quan n vic
xc lp ch hot ng Fast PWM mode 14 inverse, phn cn li bn c t i
chiu vi cc bi trc. Dng 11 v 12 thc hin set cc bit iu khin Timer1,
trc ht l cc bit COM. Bn thy ti ch set 2 bit COM1A1 v COM1B1:
(1<<COM1A1)|(1<<COM1B1). Hai bit COM1A0 v COM1B0 khng set tc mc
nh bng 0. i chiu vi bng 4 bn thy chng ta s dng Clear OC1A/OC1B
on Compare Match, set OC1A/OC1B at TOP cho tt c 2 knh A v B. Chng ta
set 3 bit WGM13, WGM12 (thanh ghi TCCR1B, dng 12) v WGM11 (thanh ghi
TCCR1A, dng 11) nh th thu c t hp (WGM13=1, WGM12=1, WGM11=1,
WGM10=0) tc l mode 14 c chn (bng 3). Cn li chng ta set bit CS10

khai bo rng ngun xung clock cho Timer1 bng clock cho vi iu khin
(prescaler=1) tc l 1us trong tng hp f=1Mhz. (nu bn dng cc trnh bin
dch khc khng h tr nh ngha tn cc bit th 2 dng 11 v 12 tng ng:
TCCR1A=0xA2; TCCR1B=0x19).
Dng 15 chng ta khai nhp gi tr cho ICR1 cng l Time period cho PWM,
ICR1=20000 chng ta thu c Time period =20000 us = 20ms tha yu cu ca
servo. Hai dng 13 v 14 khai bo gi tr ban u ca cc duty cycle ca 2 knh
PWM, cc gi tr ny nh v tr gc xoay ca cc servo. Trong 2 trnh phc v
ngt, cc gi tr ny c thay i khi cc button c nhn.
2.3
Phase
correct
PWM
(PWM
vi
pha
chnh
xc).
Phase correct PWM cung cp mt ch to xung PWM c phn gii cao
(high resolution) nn c gi l Phase correct PWM. Tng t Fast PWM, cng
c 5 mode hot ng thuc Phase correct PWM l cc mode 1, 2, 3, 10 v 11
(xem bng 3). Nm mode ny tng ng cc mode 5, 6, 7, 14 v 15 ca fast PWM.
V cch iu khin, Phase correct hu nh ging fast PWM, ngha l nu bn
bit cch s dng cc mode ca fast PWM th bn s hon ton iu khin c
Phase correct PWM. Khc nhau c bn ca 2 ch ny l trong cch hot ng,
nu Fast PWM c chu k hot ng trong 1 single-slope (mt sn) th Phase
correct PWM li dual-slope (hai sn). Ly v d mode 10 ca Phase correct PWM
tng ng vi mode 14 ca Fast PWM, trong mode ny thanh ghi ICR1 cha TOP
v OCR1A (hoc OCR1B i vi knh B) cha gi tr so snh. Khi hot ng,
thanh ghi TCNT1 tng t 0, khi TCNT1 bng vi OCR1A th chn OC1A c
xa xung mc LOW (ti ang ni trng hp COM1A1=1, COM1A0=0),
TCNT1 tip tc tng n TOP, khi TCNT1=TOP th TCNT1 KHNG c t
ng reset v 0 nh trng hp Fast PWM m TCNT1 bt u m ngc, tc
gim tng gi tr t TOP v 0. Trong lc TCNT1 gim, n 1 lc n s bng gi tr
ca OCR1A ln th 2, v ln ny, chn OC1A c set ln mc HIGH, TCNT1
tip tc gim n 0 th 1 chu k hon tt. R rng 1 chu k l qu trnh m trong 2
sn nn ta gi Phase correct PWM l dual-slope. Cng v tnh cht dual-slope
m tn hiu PWM trong ch ny c tnh i xng, thch hp cho cc ng dng
iu khin ng c. Hnh 13 m t cch m Phase correct PWM hot ng tron
mode 10 vi ng ra o (COM1A1=1, COM1A0=0).
Hnh 13. Phase correct PWM mode 10.

Vic vit code cho ch Phase correct PWM gn nh tng t fast PWM,
bn ch cn thay i t hp cc bit WGM da theo bng 3 v sau nhp cc gi
tr ph hp cho ICR1 v ORC1A, OCR1B l c.
2.3
Phase
correct
and
frequency
correct
PWM.
Ch ny c 2 mode l 8 v 9. V hu ht cc phng din, 2 mode ny
ging vi 2 mode 10 v 11 ca Phase correct PWM. Ci khc nhau duy nht l thi
im m thanh ghi OCR1A v OCR1B c cp nht d liu nu c s thay i.
Vic ny, nhn chung khng nh hng n hu ht ngi dng PWM iu
khin. Bn s rt kh thy s khc bit nu bn khng phi ang vit 1 ng
dng m sai s trong 1 micro giy l iu t hi. V th ti khng cp chi tit
ch ny, bn c c th tham kho datasheet ca chip hiu r hn nu cn
thit.
Ngoi ra trn chip atmega8 cn c b timer2 8 bits c PWM v asynchronous
operation. V mt chc nng timer2 ging nh phin bn 8 bit ca timer1 ( phn
gii thp hn nhng c cng ch v phng thc hot ng). im khc bit v
cng l im c bit ca Timer2 l kh nng hot ng khng ng b vi chip,
n ging nh vic bn tch timer2 ra thnh 1 chip timer ring, v th cn cung cp
1 ngun xung clock khc cho timer ny (1 thch anh khc). Ch ny c th
c dng calip (calibrate), canh chnh sai s v b cho ngun xung clock
chnh trn chip.
Bi 5 - Giao tip UART
5
( 139 Votes )
Ni dung
Cc bi cn tham kho t
1.
Gii thiu.
2.
Truyn thng ni tip khng ng b.
Cu trc AVR
3.
Truyn thng ni tip khng ng b vi AVR (UART).
WinAVR
1.
Thanh ghi.
C cho AVR.
2.
S dng UART.
M phng vi Prot
Download v d
I. Gii thiu.
Bi ny gip cc bn bit cch s dng cch truyn thng ni tip UART trn
AVR. Cng c chnh cng l 2 b phn mm quen thuc WinAVR v Proteus
nhng trong bi ny (v cc bi sau na) chng ta s s dng chip Atmega32 lm
chip minh ha. V c bn vic thay i chip minh ha khng nh hng ln n
tnh mch lc ca lot bi v s khc bit ca hai chip Atmega8 v Atmega32 l
khng ng k. Tuy nhin, nu c s khc bit ln phn no ti s k ra cho
bn tin so snh.
Sau bi ny, ti hy vng bn c th hiu v thc hin c:
Nguyn l truyn thng ni tip ng b v khng ng b.
Module truyn thng ni tip USART trn AVR.
Truyn thng a x l bng UART.

II. Truyn thng ni tip khng ng b.
Thut ng USART trong ting anh l vit tt ca cm t: Universal

Synchronous & Asynchronous serial Reveiver and Transmitter, ngha l b truyn
nhn ni tip ng b v khng ng b. Cn ch rng khi nim USART (hay
UART nu ch ni n b truyn nhn khng ng b) thng ch thit b phn
cng (device, hardware), khng phi ch mt chun giao tip. USART hay UART
cn phi kt hp vi mt thit b chuyn i mc in p to ra mt chun giao
tip no . V d, chun RS232 (hay COM) trn cc my tnh c nhn l s kt
hp ca chip UART v chip chuyn i mc in p. Tn hiu t chip UART
thng theo mc TTL: mc logic high l 5, mc low l 0V. Trong khi , tn hiu
theo chun RS232 trn my tnh c nhn thng l -12V cho mc logic high v
+12 cho mc low (tham kho hnh 1). Ch l cc gii thch trong ti liu ny theo
mc logic TTL ca USART, khng theo RS232.
Hnh 1. Tn hiu tng ng ca UART v RS232.

Truyn thng ni tip: gi s bn ang xy dng mt ng dng phc tp cn
s dng nhiu vi iu khin (hoc vi iu khin v my tnh) kt ni vi nhau.
Trong qu trnh lm vic cc vi iu khin cn trao i d liu cho nhau, v d tnh
hung Master truyn lnh cho Slaver hoc Slaver gi tn hiu thu thp c v
Master x lGi s d liu cn trao i l cc m c chiu di 8 bits, bn c th
s ngh n cch kt ni n gin nht l kt ni 1 PORT (8 bit) ca mi vi iu
khin vi nhau, mi line trn PORT s chu trch nhim truyn/nhn 1 bit d liu.
y gi l cch giao tip song song, cch ny l cch n gin nht v d liu c
xut v nhn trc tip khng thng qua bt k mt gii thut bin i no v v th
tc truyn cng rt nhanh. Tuy nhin, nh bn thy, nhc im ca cch
truyn ny l s ng truyn qu nhiu, bn hy tng tng nu d liu ca bn

c gi tr cng ln th s ng truyn cng s nhiu thm. H thng truyn thng
song song thng rt cng knh v v th km hiu qu. Truyn thng ni tip s
gii quyt vn ny, trong tuyn thng ni tip d liu c truyn tng bit trn 1
(hoc mt t) ng truyn. V l do ny, cho d d liu ca bn c ln n u
bn cng ch dng rt t ng truyn. Hnh 2 m t s so snh gia 2 cch truyn
song song v ni tip trong vic truyn con s 187 thp phn (tc 10111011 nh
phn).
Hnh 2. Truyn 8 bit theo phng php song song v ni tip.

Mt hn ch rt d nhn thy khi truyn ni tip so vi song song l tc
truyn v chnh xc ca d liu khi truyn v nhn. V d liu cn c chia
nh thnh tng bit khi truyn/nhn, tc truyn s b gim. Mt khc, m
bo tnh chnh xc ca d liu, b truyn v b nhn cn c nhng tha hip hay
nhng tiu chun nht nh. Phn tip theo trong chng ny gii thiu cc tiu
chun trong truyn thng ni tip khng ng b.
Khi nim ng b ch s bo trc trong qu trnh truyn. Ly v d
thit b 1 (tb1) kt vi vi thit b 2 (tb2) bi 2 ng, mt ng d liu v 1
ng xung nhp. C mi ln tb1 mun send 1 bit d liu, tb1 iu khin ng
xung nhp chuyn t mc thp ln mc cao bo cho tb2 sn sng nhn mt bit.
Bng cch bo trc ny tt c cc bit d liu c th truyn/nhn d dng vi t
ri ro trong qu trnh truyn. Tuy nhin, cch truyn ny i hi t nht 2 ng
truyn cho 1 qu trnh (send or receive). Giao tip gia my tnh v cc bn phm
(tr bn phm kt ni theo chun USB) l mt v d ca cch truyn thng ni tip
ng b.
Khc vi cch truyn ng b, truyn thng khng ng b ch cn mt
ng truyn cho mt qu trnh. Khung d liu c chun ha bi cc thit
b nn khng cn ng xung nhp bo trc d liu n. V d 2 thit b ang
giao tip vi nhau theo phng php ny, chng c tha thun vi nhau rng
c 1ms th s c 1 bit d liu truyn n, nh th thit b nhn ch cn kim tra v
c ng truyn mi mili-giy c cc bit d liu v sau kt hp chng li
thnh d liu c ngha. Truyn thng ni tip khng ng b v th hiu qu hn

truyn thng ng b (khng cn nhiu lines truyn). Tuy nhin, qu trnh
truyn thnh cng th vic tun th cc tiu chun truyn l ht sc quan trng.
Chng ta s bt u tm hiu cc khi nim quan trng trong phng php truyn
thng ny.
Baud rate (tc Baud): nh trong v d trn v vic truyn 1 bit trong 1ms,
bn thy rng vic truyn v nhn khng ng b xy ra thnh cng th cc thit
b tham gia phi thng nht nhau v khong thi dnh cho 1 bit truyn, hay ni
cch khc tc truyn phi c ci t nh nhau trc, tc ny gi l tc
Baud. Theo nh ngha, tc baud l s bit truyn trong 1 giy. V d nu tc
baud c t l 19200 th thi gian dnh cho 1 bit truyn l 1/19200 ~
52.083us.
Frame (khung truyn): do truyn thng ni tip m nht l ni tip khng
ng b rt d mt hoc sai lch d liu, qu trnh truyn thng theo kiu ny phi
tun theo mt s quy cch nht nh. Bn cnh tc baud, khung truyn l mt
yu tc quan trng to nn s thnh cng khi truyn v nhn. Khung truyn bao
gm cc quy nh v s bit trong mi ln truyn, cc bit bo nh bit Start v bit
Stop, cc bit kim tra nh Parity, ngoi ra s lng cc bit trong mt data cng
c quy nh bi khung truyn. Hnh 1 l mt v d ca mt khung truyn theo
UART, khung truyn ny c bt u bng mt start bit, tip theo l 8 bit data,
sau l 1 bit parity dng kim tra d liu v cui cng l 2 bits stop.
Start bit: start l bit u tin c truyn trong mt frame truyn, bit ny c
chc nng bo cho thit b nhn bit rng c mt gi d liu sp c truyn ti.
module USART trong AVR, ng truyn lun trng thi cao khi ngh (Idle), nu
mt chip AVR mun thc hin vic truyn d liu n s gi mt bit start bng cch
ko ng truyn xung mc 0. Nh vy, vi AVR bit start l mang gi tr 0 v
c gi tr in p 0V (vi chun RS232 gi tr in p ca bit start l ngc li).
start l bit bt buc phi c trong khung truyn.
Data: data hay d liu cn truyn l thng tin chnh m chng ta cn gi v
nhn. Data khng nht thit phi l gi 8 bit, vi AVR bn c th quy nh s
lng bit ca data l 5, 6, 7, 8 hoc 9 (tng t cho hu ht cc thit b h tr
UART khc). Trong truyn thng ni tip UART, bit c nh hng nh nht (LSB
Least Significant Bit, bit bn phi) ca data s c truyn trc v cui cng l
bit c nh hng ln nht (MSB Most Significant Bit, bit bn tri).
Parity bit: parity l bit dng kim tra d liu truyn ng khng (mt cch
tng i). C 2 loi parity l parity chn (even parity) v parity l (odd parity).
Parity chn ngha l s lng s 1 trong d liu bao gm bit parity lun l s chn.
Ngc li tng s lng cc s 1 trong parity l lun l s l. V d, nu d liu
ca bn l 10111011 nh phn, c tt c 6 s 1 trong d liu ny, nu parity chn
c dng, bit parity s mang gi tr 0 m bo tng cc s 1 l s chn (6 s
1). Nu parity l c yu cu th gi tr ca parity bit l 1. Hnh 1 m t v d ny

vi parity chn c s dng. Parity bit khng phi l bit bt buc v v th chng
ta c th loi bit ny khi khung truyn (cc v d trong bi ny ti khng dng bit
parity).
Stop bits: stop bits l mt hoc cc bit bo cho thit b nhn rng mt gi d
liu c gi xong. Sau khi nhn c stop bits, thit b nhn s tin hnh kim
tra khung truyn m bo tnh chnh xc ca d liu. Stop bits l cc bits bt
buc xut hin trong khung truyn, trong AVR USART c th l 1 hoc 2 bits
(Trong cc thit b khc Stop bits c th l 2.5 bits). Trong v d hnh 1, c 2
stop bits c dng cho khung truyn.Gi tr ca stop bit lun l gi tr ngh (Idle)
v l ngc vi gi tr ca start bit, gi tr stop bit trong AVR lun l mc cao (5V).
(Ch v gi : khung truyn ph bin nht l : start bit+ 8 bit data+1
stop bit)
Sau khi nm bt cc khi nim v truyn thng ni tip, phn tip theo chng
ta s kho st cch thc hin phng php truyn thng ny trn chip AVR (c th
l chip Atmega32).
III. Truyn thng ni tip khng ng b vi AVR (UART).
Vi iu khin Atmega32 c 1 module truyn thng ni tip USART. C 3 chn
chnh lin quan n module ny l chn xung nhp - XCK (chn s 1), chn
truyn d liu TxD (Transmitted Data) v chn nhn d liu RxD (Reveived
Data). Trong chn XCK ch c s dng nh l chn pht hoc nhn xung gi
nhp trong ch truyn ng b. Tuy nhin bi ny chng ta khng kho st ch
truyn thng ng b, v th bn ch cn quan tm n 2 chn TxD v RxD. V
cc chn truyn/nhn d liu ch m nhim 1 chc nng c lp (hoc l truyn,
hoc l nhn), kt ni cc chip AVR vi nhau (hoc kt ni AVR vi thit b h
tr UART khc) bn phi u cho 2 chn ny. TxD ca thit b th nht kt ni
vi RxD ca thit b 2 v ngc li. Module USART trn chip Atmega32 hot
ng song cng (Full Duplex Operation), ngha l qu trnh truyn v nhn d
liu c th xy ra ng thi.
1. Thanh ghi:
Cng nh cc thit b khc trn AVR, tt c hot ng v trng thi ca
module USART c iu khin v quan st thng qua cc thanh ghi trong vng
nh I/O. C 5 thanh ghi c thit k ring cho hot ng v iu khin ca
USART, l:
UDR: hay thanh ghi d liu, l 1 thanh ghi 8 bit cha gi tr nhn c v
pht i ca USART. Thc cht thanh ghi ny c th coi nh 2 thanh ghi TXB
(Transmit data Buffer) v RXB (Reveive data Buffer) c chung a ch. c UDR
thu c gi tr thanh ghi m d liu nhn, vit gi tr vo UDR tng ng t

gi tr vo thanh ghi m pht, chun b gi i. Ch trong cc khung truyn s
dng 5, 6 hoc 7 bit d liu, cc bit cao ca thanh ghi UDR s khng c s dng
UCSRA (USART Control and Status Register A): l 1 trong 3 thanh ghi iu
khin hot ng ca module USART.
Thanh ghi UCSRA ch yu cha cc bit trng thi nh bit bo qu trnh nhn
kt thc (RXC), truyn kt thc (TXC), bo thanh ghi d liu trng (UDRE),
khung truyn c li (FE), d liu trn (DOR), kim tra parity c li (PE)Bn ch
mt s bit quan trng ca thanh ghi ny:
* UDRE (USART Data Register Empty) khi bit by bng 1 ngha l thanh ghi d
liu UDR ang trng v sn sng cho mt nhim v truyn hay nhn tip theo. V
th nu bn mun truyn d liu u tin bn phi kim tra xem bit UDRE c bng
1 hay khng, sau khi chc chn rng UDRE=1 hy vit d liu vo thanh ghi UDR
truyn i.
* U2X l bit ch nh gp i tc truyn, khi bit ny c set ln 1, tc
truyn so cao gp 2 ln so vi khi bit ny mang gi tr 0.
* MPCM l bit chn ch hot ng a x l (multi-processor).
UCSRB (USART Control and Status Register B): y l thanh ghi quan
trng iu khin USART. V th chng ta s kho st chi tit tng bit ca thanh ghi
ny.
* RXCIE (Receive Complete Interrupt Enable) l bit cho php ngt khi qu trnh
nhn kt thc. Vic nhn d liu truyn bng phng php ni tip khng ng b
thng c thc hin thng qua ngt, v th bit ny thng c set bng 1 khi
USART
c
dung
nhn
d
liu.
* TXCIE (Transmit Complete Interrupt Enable) bit cho php ngt khi qu trnh
truyn
kt
thc.
* UDRIE (USART Data Register Empty Interrupt Enable) l bit cho php ngt khi
thanh
ghi
d
liu
UDR
trng.
* RXEN (Receiver Enable) l mt bit quan trng iu khin b nhn ca USART,
kch hot chc nng nhn d liu bn phi set bit ny ln 1.
* TXEN (Transmitter Enable) l bit iu khin b pht. Set bit ny ln 1 bn s
khi
ng
b
pht
ca
USART.
* UCSZ2 (Chracter size) bit ny kt hp vi 2 bit khc trong thanh ghi UCSRC
quy nh di ca d liu truyn/nhn. Chng ta s kho st chi tit khi tm hiu
thanh
ghi
UCSRC.
* RXB8 (Receive Data Bit 8) gi l bit d liu 8. Bn nh li rng USART trong
AVR c h tr truyn d liu c di ti a 9 bit, trong khi thanh ghi d liu l
thanh ghi 8 bit. Do , khi c gi d liu 9 bit c nhn, 8 bit u s cha trong
thanh ghi UDR, cn c 1 bit khc ng vai tr bit th chn, RXD8 l bit th chn
ny. Bn ch l cc bit c nh s t 0, v th bit th chn s c ch s l 8, v
l m bit ny c tn l RXD8 (khng phi RXD9).
* TXB8 (Transmit Data Bit 8), tng t nh bit RXD8, bit TXB8 cng ng vai
tr bit th 9 truyn thng, nhng bit ny c dung trong lc truyn d liu.
UCSRC (USART Control and Status Register C): thanh ghi ny ch yu

quy nh khung truyn v ch truyn. Tuy nhin, c mt rc ri nho nh l
thanh ghi ny li c cng a ch vi thanh ghi UBRRH (thanh ghi cha byte cao
dng xc lp tc baud), ni mt cch khc 2 thanh ghi ny l 1. V th bit 7
trong thanh ghi ny, tc bit URSEL l bit chn thanh ghi. Khi URSEL=1, thanh ghi
ny c chip AVR hiu l thanh ghi iu khin UCSRC, nhng nu bit URSEL=0
th thanh ghi UBRRH s c s dng.
Cc bit cn li trong thanh ghi UCSRC c m t nh sau:

* UMSEL (USART Mode Select) l bit la chn gia 2 ch truyn thng ng
b v khng ng b. Nu UMSEL=0, ch khng ng b c chn, ngc
li nu UMSEL=1, ch ng b c kch hot.
* Hai bit UPM1 v UPM0( Parity Mode) c dng quy nh kim tra pariry.
Nu UPM1:0=00, parity khng c s dng (mode ny kh thng dng),
UPM1:0=01 khng c s dng, UPM1:0=10 th parity chn c dng,
UPM1:0=11 parity l c s dng (xem thm bng 1).
Bng 1: chn kim tra parity.
* USBS (Stop bit Select), bit Stop trong khung truyn bng AVR USART c th l
1 hoc 2 bit, nu USBS=0 th Stop bit ch l 1 bit trong khi USBS=1 s c 2 Stop
bit c dng.
* Hai bit UCSZ1 v UCSZ2 (Character Size) kt hp vi bit UCSZ2 trong thanh
ghi UCSRB to thnh 3 bit quy nh di d liu truyn. Bng 2 tm tt cc gi
tr c th c ca t hp 3 bit ny v di d liu truyn tng ng.
Bng 2: di d liu truyn.
* UCPOL (Clock Pority) l bit ch cc ca xung kch trong ch truyn thng

ng b. nu UCPOL=0, d liu s thay i thay i cnh ln ca xung nhp, nu
UCPOL=1, d liu thay i cnh xung xung nhp. Nu bn s dng ch
truyn thng khng ng b, hy set bit ny bng 0..
UBRRL v UBRRH (USART Baud Rate Register): 2 thanh ghi thp v cao
quy nh tc baud.
Nhc li l thanh ghi UBRRH dng chung a ch thanh ghi UCSRC, bn phi
set bit ny bng 0 nu mun s dng thanh ghi UBRRH. Nh bn quan st trong
hnh trn, ch c 4 bit thp ca UBRRH c dng, 4 bit ny kt hp vi 8 bit
trong thanh ghi UBRRL to thnh thanh ghi 12 bit quy nh tc baud. Ch l
nu bn vit gi tr vo thanh ghi UBRRL, tc baud s tc th c cp nht, v
th bn phi vit gi tr vo thanh ghi UBRRH trc khi vit vo thanh ghi
UBRRL.
Gi tr gn cho thanh ghi UBRR khng phi l tc baud, n ch c
USART dng tnh tc baud. Bng 3 hng dn cch tnh tc baud da
vo gi tr ca thanh ghi UBRR v ngc li, cch tnh gi tr cn thit gn cho
thanh ghi UBRR khi bit tc baud.
Bng 3: tnh tc baud.
Trong cc cng thc trong bng 3, fOSC l tc tn s xung nhp ca h thng

(thch anh hay ngun xung ni). tin cho bn theo di, ti nh km bng v
d cch t gi tr cho UBRR theo tc baud mu.
Bng 4: mt s tc baud mu.
2. S dng UART:.
Thng thng, s dng module USART trn AVR bn phi thc hin 3 vic
quan trng, l: ci t tc baud (thanh ghi UBRR), nh dng khung truyn
(UCSRB, UCSRC) v cui cng kch hot b truyn, b nhn, ngtNh
cp, trong ti liu ny ti ch yu cp n phng php truyn thng khng
ng b, vic xc lp cc thng s hot ng ch yu da trn ch ny. Trong
hu ht cc ng dng, tc baud v khung truyn thng khng i, trong trng
hp ny chng ta c th khi to trc tip USART phn u trong main v sau
ch cn truyn hoc nhn d liu m khng cn thay i cc ci t. Tuy nhin,
nu trng hp giao tip linh hot v d bn ang ch to mt thit b c kh
nng giao tip vi mt thit b u cui khc (nh my tnh chng hn), lc ny
bn nn cho php ngi dng thay i tc baud hoc cc thng s khc ph
hp vi thit b u cui. i vi nhng ng dng kiu ny bn nn vit 1 chng
trnh con khi ng USART v c th gi li nhiu ln khi cn thay i. Phn
tip theo chng ta s vit mt s chng trnh v d minh ha cch s dng module
truyn thng USART t n gin n phc tp. Cc v d s c thc hin cho
chip Atmega32 vi gi s ngun xung nhp h thng l 8MHz.
2.1 Truyn d liu.
Trc ht chng ta s thc hin mt v d rt n gin hiu cch khi ng
USART v truyn cc gi d liu 8 bit. Mch in m phng trong hnh 3. Gi s
chng ta mun nh dng cho khung truyn gm 1 bit start, 8 bit d liu, khng
kim tra parity v 1 bit stop. Tc baud 57600 (57.6k). D liu cn truyn l cc
gi tr lin tc ca bng m ASCII. on code trong list 1 trnh by cch thc hin
v d ny.
List 1. Khi ng v truyn d liu khng ng b bng USART
2 #include <avr/delay.h>
3
4 //chuong trinh con phat du lieu
5 void uart_char_tx(unsigned char chr){
6
while (bit_is_clear(UCSRA,UDRE)) {}; //cho den khi bit UDRE=1
7
UDR=chr;
8 }
9
10 int main(void){
11 //set baud, 57.6k ung voi f=8Mhz, xem bang 70 trang 165, Atmega32 datasheet
12 UBRRH=0;
13 UBRRL=8;
14
15 //set khung truyen va kich hoat bo nhan du lieu
16 UCSRA=0x00;
17 UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0);
18 UCSRB=(1<<TXEN);
19
20 while(1){
21
for (char i=32; i<128; i++){
22
uart_char_tx(i); //phat du lieu
23
_delay_ms(100);
24
}
25 }
26 }
Trc ht ti s gii thch cch khi ng USART trong cc dng code t 12
n 18. Nu bn xem li bng 3 trong trang 9 ca ti liu ny (hoc bng 70, trang
165 datasheet ca chip atmega32), ng vi tn s xung nhp 8Hhz, khng s dng
ch nhn i tc (U2X=0), t c tc b baud 57600 th gi tr cn gn
cho thanh ghi UBRR l 8 (xem ct 2, bng 3). Hai dng 12 v 13 trong list 1 thc
hin gn 8 cho thanh ghi UBRR thng qua 2 thanh ghi UBRRH v UBRRL. Trong
dng 16, thanh ghi UCSRA c gn bng 0. Nu bn xem li phn gii thch bn
s thy thanh ghi UCSRA ch yu cha cc bit trng thi, ring 2 bit U2X v
MPCM l 2 bit iu khin, 2 bit ny bng 0 ngha l chng ta khng s dng ch
nhn i tc v khng s dng truyn thng a x l. Phn quan trng nht
chnh l t gi tr cho 2 thanh ghi USCRB v UCSRC. Vi thanh ghi UCSRC
(dng 17) trc ht chng ta phi set bit URSEL bo rng chng ta khng mun
truy cp thanh ghi UBRRH m l thanh ghi UCSRC (2 thanh ghi ny c cng a
ch), tip theo chng ta ch set 1 cho 2 bit UCSZ1 v UCSZ0, bn xem li bng 2
thy rng nu UCSZ1=1, UCSZ0=1 cng vi vic bit UCSZ2=0(nm trong
thanh ghi UCSRB) th di d liu truyn c chn l 8 bit. Cc bit trong thanh
ghi UCSRC khng c set s mc nh mang gi tr 0, bao gm UMSEL = 0 (ch
truyn thng khng ng b), UPM1:0=00 ( khng s dng kim tra parity,
xem bng 1), USBS=0 (1 bit stop) v UCPOL=0 (bit ny khng s dng khi
truyn khng ng b). Sau cng, trong dng 18, chng ta ch set bit TXEN =1
ngha l ch kch hot b pht d liu, cc thnh phn khc nh b nhn, cc
ngtkhng c s dng trong v d ny.
Trong cc bi trc ti gii thiu bn v trnh phc v ngt v trong phn
ny ti s trnh by cch vit mt chng trnh con bng ngn ng C trong
WinAVR, l on chng trnh uart_char_tx dng 5. Chng trnh con l 1
on code bao gm cc cu lnh cng thc hin mt nhim v chung c th no
. Trong trng hp ny l nhim v truyn 1 tham s 8 bit ra ng TxD ca
USART thng qua thanh ghi UDR. Nh trnh by trong phn m t bit UDRE ca
thanh ghi UCSRA, qu trnh truyn ch c bt u khi bit UDRE bng 1, v th
dng code 6 lm nhim v kim tra bit UDRE, cu
lnh while (bit_is_clear(UCSRA,UDRE)) {}; c hiu l qu trnh lp s ln
qun nu bit UDRE bng 0 (bit_is_clear). Khi bit UDRE bng 1 th dng code 7
s xut bin chr ra thanh ghi UDR cng l xut ra chn TxD ca module USART.
Trong ngn ng C c 2 cch c bn vit chng trnh con. Vi cch 1 chng
trnh con c khai bo v vit trc tip pha trc chng trnh chnh main nh
cch m ti thc hin trong v d 1 ny. Cch vit ny hiu v thch hp cho cc
on chng trnh con ngn nhng chng c th lm tng quan chng trnh ca
bn tr nn rc ri khi c qu nhiu chng trnh con vit trc main. Bn c th
khc phc nhc im ny bng cch t cc chng trnh con pha sau main nh
cch m chng ta lm vi cc trnh phc v ngt. Nu theo ng quy cch ca
ngn ng C, khi t chng trnh con sau main bn phi khai bo tn chng trnh
pha trc main, nu bn t chng trnh con uart_char_tx pha sau main th phn
trc main bn s t dng khai bo trc: void uart_char_tx(unsigned
char chr);. Tuy WinAVR cho php bn b qua khai bo trc ny nhng ti
khuyn bn nn vit ng cch to thi quen v cng nh d chuyn chng
trnh sang cc trnh bin dch C khc sau ny nu cn thit. Phn cui cng trong
on code l gi li chng trnh uart_char_tx truyn cc d liu l cc s t 32

n 127.
thc hin m phng bng proteus bn hy v mt mch in n gin nh
trong hnh 3. Chip Atmega32 c th c tm vi t kha mega32. Trong mch
in m phng c mt thit b u cui o (Virtual Terminal) l mt thit b kt ni
v hin th kt qu truyn thng khng ng b, chng ta dng kim tra d liu
c truyn bng chip AVR. Bn c th tm thit b ny trong trong danh sch cc
d c o (virtual instruments), nhn vo nt cng c v sau chn terminal
trong danh sch chn thit b u cui o. Kt ni thit b o vi chip Atmega32
nh trong hnh 3, ch l phi u cho 2 chn TxD v RxD. Bn cnh vic gn
chng trnh cho chip AVR, bn phi set thng s cho thit b o trc khi thc
hin m phng. Hy m hp thoi edit component ca thit b o (bng cch
right click ri left click trn thit b o). Theo mc nh thit b u cui c nh
dng khung truyn l 1 bit start+8 bit d liu+1 bit stop tng t nh cch chng ta
ci t cho AVR trong v d 1, v th bn ch cn thay i tc baud thnh 57600
trong hp thoi edit component l hon tt (xem hnh 4). Khi chy m phng,
thit b u cui o s hin th cc k t ASCII ca cc s t 32 n 127.
Hnh 3. M phng v d 1.
Hnh 4. Ci t thng s cho thit b o.

2.2 Nhn d liu.
Qu trnh nhn d liu ch xy ra khi bit RXEN trong thanh ghi UCSRB c
set bng 1 v tt nhin chn nhn d liu RxD phi c ni vi mt ngun pht
(chn TxD ca mt chip UART khc chng hn). Cc thng s truyn thng nh
tc baud v khung truyn trong b nhn phi c ci t nh ca b pht. Nu
khng c li trong qu trnh truyn v nhn d liu, sau khi nhn d liu s c
cha trong thanh ghi UDR v bit RXC (Reveice Complete) trong thanh ghi
UCSRA s t ng c set ln 1. Sau khi thanh ghi UDR c c, bit RXC li
t ng reset v 0 chun b cho qu trnh nhn d liu k tip. Nh th v c
bn chng ta c 2 cch c d liu nhn v. Cch th nht l cch hi vng
(polling), kim tra nu bit RXC = 1 th c gi tr thanh ghi UDR (v c c bit
RXB8 trong thanh ghi UCSRB nu frame truyn 9 bit c dng). Cch th hai l
s dng ngt nhn hon tt (Receive Complete Interrupt), bng cch set bit cho
php ngt nhn hon tt, tc bit RXCIE trong thanh ghi UCSRB, v bit cho php
ngt ton cc (bit I, xem li bi 3) th mt ngt s xy ra khi d liu c nhn
v cha trong thanh ghi UDR, chng ta ch cn c gi tr ca thanh ghi UDR
trong trnh phc v ngt l xong. Theo kinh nghim, s dng ngt l phng php
tt nht cho a s cc trng hp nhn d liu UART, v chng ta khng cn quan
tm thi im m d liu gi n, trnh lng ph thi gian dnh cho vic hi
vng. V th trong phn tip theo ti s trnh by mt v d minh ha qu trnh
nhn d liu bng phng php ngt. phc v cho v d ny, chng ta s kho
st mt mch m phng gm 2 chip Atmega32 ni vi nhau qua cc ng TxD v

RxD. Chip th l chip pht d liu, nhim v ca chip ny l pht chui d liu t
32 n 127 nh chip Atmega32 trong v d 1. Chn pht TxD ca chip 1 s c
ni vi chn nhn RxD ca chip th 2 (chip th 2 c gi l chip nhn d liu).
Chip th 2 sau khi nhn d liu s pht d liu ny ra chn TxD ca chnh n c
th hin th ln thit b u cui o cho chng qua quan st v so snh kt qu. Bn
xem mch in m phng trong hnh 5 hiu r hn. Chng ta s dng on
code trong v d 1 cho chip th nht v th ch cn vit on code nhn v pht li
d liu cho chip th hai. List 2 trnh by on code cho chip th hai..
List 2. Nhn d liu USART khng ng b bng phng php ngt.
4 //chuong trinh con phat du lieu
5 void uart_char_tx(unsigned char chr){
6
while (bit_is_clear(UCSRA,UDRE)) {}; //cho den khi bit UDRE=1
7
UDR=chr;
8 }
9 volatile unsigned char u_Data;
10
11 int main(void){
12 //set baud, 57.6k ung voi f=8Mhz, xem bang 70 trang 165, Atmega32 datasheet
13
UBRRH=0;
14
UBRRL=8;
15 //set khung truyen va kich hoat bo nhan du lieu
16
UCSRA=0x00;
17
UCSRC=(1<<URSEL)|(1<<UCSZ1)|(1<<UCSZ0);
18
UCSRB=(1<<RXEN)|(1<<TXEN)|(1<<RXCIE);//cho phep ca 2 qua trinh nhan va//truyen
19 phep ngat sau khi nhan xong
20
sei(); //cho phep ngat toan cuc
21
22
while(1){
23
}
24 }
25 ISR(SIG_UART_RECV){ //trinh phuc vu ngat USART hoan tat nhan
26
u_Data=UDR;
27
uart_char_tx(u_Data);
28 }
on code trong v d nhn v pht d liu khng khc on code trong v

d 1 l my. dng th 3 ti include file header interrupt.h v chng ta s s
dng ngt nhn d liu. Chng ta khai bo mt bin u_Data dng 8 bit
khng du lu d liu nhn c, do bin ny s c truy cp trong trnh
phc v ngt nn chng ta t attribute volatile (dng 9). im quan trng khi
khi ng UART trong v d ny l dng code 18, nu trong v d 1 chng ta
ch khi ng duy nht b pht bng cch set bit TXEN trong thanh ghi UCSRB
(UCSRB=(1<<TXEN);) th trong v d ny chng ta set thm 2 bit cho php
nhn RXEN v cho php ngt RXCIE trong thanh ghi UCSRB. Bit RXEN khi
ng b nhn v bit RXCIE khi ng ch ngt khi d liu nhn trong
UDR, tuy nhin c th s dng ngt, chng ta cn set them bit I trong thanh
ghi trng thi bng dng code 20 (sei();). Phn quan trng nht trong on code
trn l trnh phc ngt nhn d liu ISR. Khi d liu c nhn y trong
UDR, trnh ngt ISR(SIG_UART_RECV) s c thc hin, chng ta s c
gi tr va nhn c vo bin u_Data (dng 26) v sau pht gi tr ny ra
chn TxD hin th ln thit b u cui o bng dng lnh 27.
Phn mch in m phng c trnh by trong hnh 5. Chng trnh cho
chip TRANSMITTER l chng trnh trong v d 1 v chng trnh cho chip
RECEIVER l chng trnh trong on code trn. Bn phi set xung clock cho
c 2 chip l 8MHz v set tc baud cho thit b u cui o l 56700. Nu khi
chy m phng, thit b u cui hin th cc k t ASCII ca cc s t 32 n
127 nh trong hnh 5 th mi th c thc hin chnh xc.
Hnh 5. Truyn v nhn bng UART.
Bi 5.1 - Giao tip UART ch Multi-Processor
5
( 30 Votes )
Ni dung
1.
Ch Multi-Processor trong AVR UART.

Cu trc AVR
WinAVR.
2.
S dng Multi-Processor.
Download v d
C cho AVR.
M phng vi Proteus.
Giao tip UART
I. Ch Multi-Processor trong AVR UART.

AVR h tr mt kh nng giao tip UART ch a x l (Multiprocessor) hay Master-Slaves. iu u tin bn cn bit l ch ny khng phi
l chun ca UART m ch c bit trn cc chip AVR (v c th trn mt s chip
khc ca Atmel). Bit MPCM (bit 0) trong thanh ghi UCSRA l nhn t quan trng
nht quyt nh ch hot ng ny. Cu hnh mng Master-Slave dng
UART c tm tt nh sau:
- Trn mng ny ch c 1 Master v c th c nhiu Slaves, cc ng TxD v
RxD ca cc Slaves c ni chung vi nhau (ni song song). Cc Slaves v
Master c ni vi nhau theo kiu bt cho, TxD chung ca Slaves ni vi
RxD ca Master v ngc li. Mi Slave mang 1 a ch ring do ngi dng gn,
c bit c th c nhiu Slave trng a ch vn khng nh hng n hot ng
ca mng.
- Cc Slaves v Master phi c ci t khung truyn v baudrate nh nhau
(cng nh truyn thng UART thng thng). Khung truyn trong ch MasterSlaves c th 5, 6, 7,8 hay 9 bit nhng thng thng khung 9 bit c chn. Bi
ny cng hng dn da trn khung 9 bit. Trong khung truyn 9 bit, 8 bit u tin
c cha trong thanh ghi d liu UDR nh thng thng v bit th cao nht l bit
TXB8 trong thanh ghi USCRB (trng hp pht) hay bit RXB8 trong thanh ghi
UCSRB (trng hp thu).
- Bit MPCM (bit 0) trong thanh ghi UCSRA cho php mt chip lm vic ch
Master-Slave. Tuy nhin bit ny ch c tc dng chip Slaves, mt chip lm
vic nh mt Slave (ch lnh t Master) th bit MPCM ca chip ny phi c set
ln 1. Bit MPCM ca Master khng cn set.
C ch lm vic ca ch Master-Slaves c gii thch nh sau: lc u, cc

bit MPCM trn tt c cc Slaves u c set ln 1, ngt nhn d liu RXCIE ca
cc Slaves c kch hot v chng ang ch ch lnh t Master. Khi chip
Master mun thc hin mt cuc gi vi mt Slave no , n s pht ra mt
gi a ch bao gm 8 bits cha a ch ca Slave cn gi v bit cao nht (TXB8)
lun bng 1 (xem hnh 1).
Hnh 1. Gi a ch.
Khi tt c 9 bit c cc Slaves nhn, bit cao nht s c Slaves cha trong bit
RXB8. Nu bit ny bng 1 cc Slaves bit rng y l gi a ch, ngt RXCIE s
xy ra trn tt c cc Slaves. Qu trnh ny c chip thc hin mt cch hon ton
t ng. Trong trnh phc v ngt RXCIE (SIG_UART_RECV) ngi lp trnh s
thc hin so snh gi tr 8 bits a ch nhn v vi a ch ca tng Slave. Nu mt
Slave nhn thy a ch m Master gi khp vi a ch ca n, ngi lp trnh cn
reset bit MPCM v 0 tch Slave ny ra khi ch ch (ch a ch). Tip theo
Master s gi lin tip cc gi d liu trn ng truyn. Khc vi gi a ch,
bit cao nht (TXB8) trong gi d liu bng 0 ch khng bng 1. Trn chip Master,
ngi lp trnh cn vit 2 on chng trnh pht gi a ch v gi d liu ring
bit. i vi cc Slaves, do bit cao nht nhn v RXB8=0, ngt RXCIE ch duy
nht xy ra trn Slave c bit MPCM=0. Nh th, tt c cc Slaves khc s b qua
gi ny (ngt RXCIE khng xy ra, khng nh hng n cc vic khc) ch duy
nht Slave c a ch trng trc nhn d liu. Mt ch rt quan trng l sau
khi byte d liu cui cng c nhn, Slave (chip c chn) phi set li
bit MPCM ln 1 (do ngi lp trnh thc hin) a Slave tr li trng thi ch
cc
cuc
gi
tip
theo.
Nh vy, bng cch no Slave phi bit trc c s lng bytes d liu
m Master mun gi kp thi set bitMPCM ln 1 sau byte cui. C mt s cch
bit trc s lng bytes m Master s gi nh tha thun trc s bytes c
nh cho mi cuc gi; hoc n gin Master dng byte d liu u tin (sau byte
a ch) bo s lng bytes s gi tip theo; hoc hay hn c th ghp thng s
ch lng bytes cn truyn vo gi a ch nu nh khng c qu nhiu Slaves trn

mng v s lng bytes truyn cng khng qu ln. Nhng d cch no i na,
cn c s tha thun khi lp trnh cho Master v Slave. C mt du hiu khc
c th c dng phn bit gia gi d liu v gi a ch l trng thi bit
RXB8, bng vic kim tra trng thi bit ny chng ta s bit c gi no l d
liu (RXB8=0) v gi no l a ch (RXB8=1). Tuy nhin cch ny khng nhn
bit c byte d liu cui cng c gi v vy khng c s dng set
bit MPCM ln 1.
II. S dng Multi-Processor.

Trong v d bi ny ti dng phng php n gin l tha thun trc gia
Master v Slave s lng bytes trong mt ln truyn, c th chng ta s thit lp
mt mng Master-Slaves vi 1 Master v 2 Slaves. Cc Slave c a ch ln lt l
1 v 2, chng ta dng 2 chn PC0 v PC1 set a ch cho Slaves (vic ny gip
chng ta c th s dng 1 chng trnh chung cho 2 Slaves). Master ch n gin
gi n mi Slave 1 gi a ch v 2 bytes d liu. Cc Slaves s hin th 2 bytes
d liu ln 2 dng ca LCD. Mch in m phng v d trnh by trong hnh 2.
Hnh 2. V d mng Master-Slaves dng UART.

Chng ta cn vit 2 on chng trnh ring cho Master v Slaves. on chng
trnh
cho
Master
c
trnh
by
trong
List1.
List 1. Chng trnh cho Master.
Vi chip Master, nh trnh by chng ta cn vit ring 2 on chng trnh

con phc v pht gi d liu v gi a ch. Trong list 1, hai on chng trnh ny
c tn uart_char_tx v uart_address_tx nm t dng 38 n 48. y ch on
code pht uart thng thng (xem bi AVR5 Giao tip UART) cng thm vi
vic set v reset bit TXB8. Trong on chng trnh pht gi d liu, bit TXB8
c reset v 0 bng cu lnh UCSRB &= ~(1<<TXB8); trong khi on chng
trnh pht gi a ch bit ny c set ln 1, UCSRB |= (1<<TXB8); (ch bit
TXB8
nm
trong
thanh
ghi
USCRB).
Phn ci t cho UART (t dng 14 n dng 20) bn c hy xem li bi
AVR5. Ch n cc dng t 24 n 30. y l phn gi a ch v d liu n
cc Slave. Trc khi mun gi d liu n Slave1, chng ta cn gi chng trnh
con pht a ch uart_address_tx(1) nh trong dng 24, tip theo l pht 2 bytes d
liu theo cch thng thng (v d byte1=200, byte2=123). Tng t chng ta c
th pht2 bytes d liu n Slave2 theo cch ny (dng 28, 29 v 30).
List
2.
Chng
trnh
cho
Slaves.
Do chng ta s dng TextLCD hin th kt qu nhn v t Master, cn

include th vin myLCD.h (dng 6). Th vin stdio.h cha cc hm x l chui k
t gip ch cho vic hin th LCD (chng ta s dng hm sprintf) nn cng cn
c include vo (dng 5). Bin my_address cha a ch ca Slave, u_data cha
gi tr nhn v t UART, bin ind l ch s ch s bytes nhn v. Gi d liu nhn
v cha trong mng alldata[3], mng dis[5] l mng k t tm thi hin th ln
LCD (xem cc khai bo bin trong 2 dng 14. 15). a ch Slave do 2 chn PC0 v
PC1 quyt nh, vic c a ch ny c thc hin vi dng lnh
my_address=PINC & 0x03. Bng cch chn a ch ng nh th chng ta
khng
cn
vit
ring
chng
trnh
cho
mi
Slave.
Cc dng lnh t 24 n 30 ci t thng s cho UART, ch cn cho php
ngt RXCIE xy ra dng 29 v 30). Phn ni dung quan trng nht c vit trong
trnh phc v ngt ISR(SIG_UART_RECV) (t dng 44 n 60). Khi mt ngt
RXCIE vic u tin cn lm l c gi tr nhn v vo bin u_data (dng 45), nu
y l byte u tin nhn v (tc ind=0, byte a ch) th chng ta cn so snh xem
a ch c khp khng (dng 47). Nu ng l a ch ca Slave ny th cn reset
bit MPCM v 0 sn sng nhn d liu (dng 48), tng bin ind ln 1. Nu byte
nhn v khng phi l byte u tin m l byte d liu (bin ind khc 0) chng ta
s gn byte nhn v vo mng alldata v tng bin ch s ind (cc dng t 52 n
54). V trong v d ny chng ta tha thun trc Master ch gi 2 bytes d liu
n mi Slave nn khi bin ind bng 3, tc l nhn 2 bytes d liu chng ta
cn set li bit MPCM kt thc qu trnh nhn, a Slave v li trng thi ch,
ng thi tr bin ch s ind v 0 (lm li t u) (xem cc dng 55 n 57).
Khi m phng, bn hy np chng trnh trong List 1 cho chip Master v list2
cho 2 Slaves. Cn set xung clock 8MHz. Nu bn thc hin ng kt qu s hin
th nh trong hnh 1.
Bi 6 - Chuyn i ADC
( 95 Votes )
Ni dung
1.
Bn s i n u.
2.
Chuyn i tn hiu tng t sang tn hiu s (ADC).
3.
B chuyn i ADC trn AVR.
Download v d
Cc bi cn tham kho tr
Cu trc AVR
WinAVR
C cho AVR.
M phng vi Proteu
I. Bn s i n u.
Bi hc ny, nh tn ca n, s gii thiu cch s dng b chuyn i tng t
- s (analog to digital converter - ADC). Cng c chnh cng l 2 b phn mm
quen thuc WinAVR v Proteus.
Nguyn l chuyn i AD.
Chuyn i ADC n knh trn AVR.
S dng chuyn i ADC n knh trn AVR, hin th s 4 digit bng LED
7 on.
II. Chuyn i d liu tng t (analog) sang d liu s (digital).
Trong cc ng dng o lng v iu khin bng vi iu khin b chuyn i
tng t-s (ADC) l mt thnh phn rt quan trng. D liu trong th gii ca
chng ta l cc d liu tng t (analog). V d nhit khng kh bui sng l
25oC v bui tra l 32oC, gia hai mc gi tr ny c v s cc gi tr lin tc m
nhit phi i qua c th t mc 32oC t 25oC, i lng nhit nh th
gi l mt i lng analog. Trong khi , r rng vi iu khin l mt thit b s
(digital), cc gi tr m mt vi iu khin c th thao tc l cc con s ri rc v
thc cht chng c to thnh t s kt hp ca hai mc 0 v 1. V d chng ta
mun dng mt thanh ghi 8 bit trong vi iu khin lu li cc gi tr nhit t
0oC n 255 oC, nh chng ta bit, mt thanh ghi 8 bit c th cha ti a 256
(28) gi tr nguyn t 0 n 255, nh th cc mc nhit khng nguyn nh
28.123 oC s khng c ghi li. Ni cch khc, chng ta s ha (digitalize)
mt d liu analog thnh mt d liu digital. Qu trnh s ha ny thng c
thc hin bi mt thit b gi l b chuyn i tng t - s hay n gin l ADC

(Analog to Digital Converter).
C rt nhiu phng php chuyn i ADC, ti khng c nh gii thch c
th cc nguyn l chuyn i ny trong bi hc v AVR, tuy nhin ti s gii thiu
mt cch chuyn i rt c bn v ph bin cc bn phn no nm c cch
m mt b ADC lm vic. Phng php chuyn i m ti ni l phng php
chuyn i trc tip (direct converting) hoc flash ADC. Cc b chuyn i ADC
theo phng php ny c cu thnh t mt dy cc b so snh (nh opamp),
cc b so snh c mc song song v c kt ni trc tip vi tn hiu analog
cn chuyn i. Mt in p tham chiu (reference) v mt mch chia p c s
dng to ra cc mc in p so snh khc nhau cho mi b so snh. Hnh 1 m
t mt b chuyn i flash ADC c 4 b so snh, Vin l tn hiu analog cn chuyn
i v gi tr sau chuyn i l cc con s to thnh t s kt hp cc mc nh
phn trn cc chn Vo. Trong hnh 1, bn thy rng do anh hng ca mch chia p
(cc in tr mc ni tip t in p +15V n ground), in p trn chn m (chn
-) ca cc b so snh s khc nhau. Trong lc chuyn i, gi s in p Vin ln
hn in p V- ca b so snh 1 (opamp pha thp nht trong mch) nhng li
nh hn in p V- ca cc b so snh khc, khi ng Vo1 mc 1 v cc ng
Vo khc mc 0, chng ta thu c mt kt qu s. Mt cch tng t, nu tng
in p Vin ta thu c cc t hp s khc nhau. Vi mch in c 4 b so snh
nh trong hnh 1, s c tt c 5 trng hp c th xy ra, hay ni theo cch khc
in p analog Vin c chia thnh 5 mc s khc nhau. Tuy nhin, bn ch l
cc ng Vo khng phi l cc bit ca tn hiu s ng ra, chng ch l i din t
hp thnh tn hiu s ng ra, d hiu hn chng ta khng s dng c cc bit Vo
trc tip m cn mt b gii m (decoder). Trong bng 1 ti trnh by kt qu sau
khi gii m ng vi cc t hp ca cc ng Vo.
Hnh 1. Mch flash ADC vi 4 b so snh.

Bng 1 Gi tr s ng ra sau khi gii m.
phn gii (resolution): nh trong v d trn, nu mch in c 4 b so

snh, ng ra digital s c 5 mc gi tr. Tng t nu mch in c 7 b so snh th
s c 8 mc gi tr c th ng ra digital, khong cch gia cc mc tn hiu
trong trng hp 8 mc s nh hn trng hp 4 mc. Ni cch khc, mch
chuyn i vi 7 b so snh c gi tr digital ng ra mn hn khi ch c 4 b,
mn cng cao tc phn gii (resolution) cng ln. Khi nim phn gii
c dng ch s bit cn thit cha ht cc mc gi tr digital ng ra. Trong

trng hp c 8 mc gi tr ng ra, chng ta cn 3 bit nh phn m ha ht cc
gi tr ny, v th mch chuyn i ADC vi 7 b so snh s c phn gii l 3
bit. Mt cch tng qut, nu mt mch chuyn i ADC c phn gii n bit th s
c 2n mc gi tr c th c ng ra digital. to ra mt mch chuyn i flash
ADC c phn gii n bit, chng ta cn n 2n-1 b so snh, gi tr ny rt ln khi
thit k b chuyn i ADC c phn gii cao, v th cc b chuyn i flash
ADC thng c phn gii t hn 8 bit. phn gii lin quan mt thit n cht
lng chuyn i ADC, vic la chn phn gii phi ph hp vi chnh xc
yu cu v kh nng x l ca b iu khin. Trong 2 m t mt v d s ha
mt hm sin analog thnh dng digital.
Hnh 2. Analog v digital ca hm sin.

in p tham chiu (reference voltage): Cng mt b chuyn i ADC
nhng c ngi mun dng cho cc mc in p khc nhau, v d ngi A mun
chuyn i in p trong khong 0-1V trong khi ngi B mun dng cho in p
t 0V n 5V. R rng nu hai ngi ny dng 2 b chuyn i ADC u c kh
nng chuyn i n in p 5V th ngi A ang ph phm tnh chnh xc ca
thit b. Vn s c gii quyt bng mt i lng gi l in p tham chiu Vref (reference voltage). in p tham chiu thng l gi tr in p ln nht m
b ADC c th chuyn i. Trong cc b ADC, Vref thng l thng s c t
bi ngi dng, n l in p ln nht m thit b c th chuyn i. V d, mt b
ADC 10 bit ( phn gii) c Vref=3V, nu in p ng vo l 1V th gi tr s
thu c sau khi chuyn i s l: 1023x(1/3)=314. Trong 1023 l gi tr ln
nht m mt b ADC 10 bit c th to ra (1023=210-1). V in p tham chiu nh
hng n chnh xc ca qu trnh chuyn i, chng ta cn tnh ton chn
1 in p tham chiu ph hp, khng c nh hn gi tr ln nht ca input
nhng cng ng qu ln.
II. Chuyn i ADC trn AVR.
Chip AVR ATmega32 ca Atmel c tch hp sn cc b chuyn i ADC vi

phn gii 10 bit. C tt c 8 knh n (cc chn ADC0 n ADC7), 16 t hp
chuyn i dng so snh, trong c 2 knh so snh c th khuych i. B
chuyn i ADC trn AVR khng hot ng theo nguyn l flash ADC m ti
cp phn trn, ADC trong AVR l loi chuyn i xp x ln lt (successive
approximation ADC).
ADC trn AVR cn c nui bng ngun in p ring chn AVCC, gi
tr in p cp cho AVCC khng c khc ngun nui chip (VCC) qu +/-0.3V.
Nhiu (noise) l vn rt quan trng khi s dng cc b ADC, gim thiu sai
s chuyn i do nhiu, ngun cp cho ADC cn phi c lc (filter) k cng.
Mt cch n gin to ngun AVCC l dng mt mch LC kt ni t ngun
VCC ca chip nh minh ha trong hnh 3, y l cch c gi bi nh sn xut
AVR.
Hnh 3. To ngun AVCC t VCC.

in p tham chiu cho ADC trn AVR c th c to bi 3 ngun: dng in
p tham chiu ni 2.56V (c nh), dng in p AVCC hoc in p ngoi t trn
chn VREF. Mt ln na, bn cn ch n noise khi t in p tham chiu, nu
dng in p ngoi t trn chn VREF th in p ny phi c lc tht tt, nu
dng in p tham chiu ni 2.56V hoc AVCC th chn VREF cn c ni vi
mt t in. Vic chn in p tham chiu s c cp chi tit trong phn s
dng ADC.
Cc chn trn PORTA ca chip ATmega32 c dng cho b ADC, chn PA0
tng ng knh ADC0 v chn PA7 tng ng vi knh ADC7.
1. Thanh ghi.
C 4 thanh trong b ADC trn AVR trong c 2 thanh ghi data cha d liu
sau khi chuyn i, 2 thanh ghi iu khin v cha trng thi ca ADC.
- ADMUX (ADC Multiplexer Selection Register): l 1 thanh ghi 8 bit iu
khin vic chn in p tham chiu, knh v ch hot ng ca ADC. Chc
nng ca tng bit trn thanh ghi ny s c trnh by c th nh sau:
Bit 7:6- REFS1:0 (Reference Selection Bits): l cc bit chn in p tham

chiu cho ADC, 1 trong 3 ngun in p tham chiu c th c chn l: in p
ngoi t chn VREF, in p tham chiu ni 2.56V hoc in p AVCC. Bng 2
tm tt gi tr cc bit v in p tham chiu tng ng.
Bng 2: Chn in p tham chiu
Bit 5-ADLAR (ADC Left Adjust Result): l bit cho php hiu chnh tri kt
qu chuyn i. S d c bit ny l v ADC trn AVR c phn gii 10 bit, ngha
l kt qu thu c sau chuyn i l 1 s c di 10 bit (ti a 1023), AVR b
tr 2 thanh ghi data 8 bit cha gi tr sau chuyn i. Nh th gi tr chuyn i
s khng lp y 2 thanh ghi data, trong mt s trng hp ngi dng mun 10
bit kt qu nm lch v pha tri trong khi cng c trng hp ngi dng mun
kt qu nm v pha phi. Bit ADLAR s quyt nh v tr ca 10 bit kt qu trong
16 bit ca 2 thanh ghi data. Nu ADLAR=0 kt qu s c hiu chnh v pha
phi (thanh ghi ADCL cha trn 8 bit thp v thanh ghi ADCH cha 2 bit cao
trong 10 bit kt qu), v nu ADLAR=1 th kt qu c hiu chnh tri (thanh ghi
ADCH cha trn 8 bit cao nht, cc bit t 9 n 2, v thanh ADCL cha 2 bit thp
nht trong 10 bit kt qu (bn xem hnh cch b tr 2 thanh ghi ADCL v ADCH
bn di hiu r hn).
Bits 4:0-MUX4:0 (Analog Channel and Gain Selection Bits): l 5 bit cho
php chn knh, ch v c h s khuych i cho ADC. Do b ADC trn AVR
c nhiu knh v cho php thc hin chuyn i ADC kiu so snh (so snh in
p gia 2 chn analog) nn trc khi thc hin chuyn i, chng ta cn set cc bit
MUX chn knh v ch cn s dng. Bng 3 tm tt cc ch hot ng
ca ADC thng qua cc gi tr ca cc bit MUX. Trong bng ny, ng vi cc gi
tr t 00000 n 00111 (nh phn), cc knh ADC c chn ch n knh
(tn hiu input ly trc tip t cc chn analog v so snh vi 0V), gi tr t 01000
n 11101 tng ng vi ch chuyn i so snh.
Bng 3: Chn ch chuyn i.
- ADCSRA (ADC Control and Status RegisterA): l thanh ghi chnh iu

khin hot ng v cha trng thi ca module ADC.
Tng bit ca thanh ghi ADCSRA c m t nh bn di:
Bit 7 - ADEN(ADC Enable): vit gi tr 1 vo bit ny tc bn cho php

module ADC c s dng. Tuy nhin khi ADEN=1 khng c ngha l ADC
hot ng ngay, bn cn set mt bit khc ln 1 bt u qu trnh chuyn i,
l bit ADSC.
Bit 6 - ADSC(ADC Start Conversion): set bit ny ln 1 l bt u khi ng

qu trnh chuyn i. Trong sut qu trnh chuyn i, bit ADSC s c gi
nguyn gi tr 1, khi qu trnh chuyn i kt thc (t ng), bit ny s c tr v
0. V vy bn khng cn v cng khng nn vit gi tr 0 vo bit ny bt k tnh
hung no. thc hin mt chuyn i, thng thng chng ta s set bit
ADEN=1 trc v sau set ADSC=1.
Bit 4 ADIF(ADC Interrupt Flag): c bo ngt. Khi mt chuyn i kt

thc, bit ny t ng c set ln 1, v th ngi dng cn kim tra gi tr bit ny
trc khi thc hin c gi tr chuyn i m bo qu trnh chuyn i thc
s hon tt.
Bit 3 ADIE(ADC Interrupt Enable): bit cho php ngt, nu bit ny c

set bng 1 v bit cho php ngt ton cc (bit I trong thanh ghi trng thi ca chip)
c set, mt ngt s xy ra khi mt qu trnh chuyn i ADC kt thc v cc gi
tr chuyn i c cp nht (cc gi tr chuyn i cha trong 2 thanh ghi
ADCL v ADCH).
Bit 2:0 ADPS2:0(ADC Prescaler Select Bits): cc bit chn h s chia xung
nhp cho ADC. ADC, cng nh tt c cc module khc trn AVR, cn c gi
nhp bng mt ngun xung clock. Xung nhp ny c ly t ngun xung chnh
ca chip thng qua mt h s chia. Cc bit ADPS cho php ngi dng chn h s
chia t ngun clock chnh n ADC. Tham kho bng 4 bit cch chn h s
chia.
Bng 4: H s chia xung nhp cho ADC.
- ADCL v ADCH (ADC Data Register): 2 thanh ghi cha gi tr ca qu

trnh chuyn i. Do module ADC trn AVR c phn gii ti a 10 bits nn cn
2 thanh ghi cha gi tr chuyn i. Tuy nhin tng s bt ca 2 thanh ghi 8 bit
l 16, con s ny nhiu hn 10 bit ca kt qu chuyn i, v th chng ta c
php chn cch ghi 10 bit kt qu vo 2 thanh ghi ny. Bit ADLAR trong thanh
ghi ADMUX quy nh cch m kt qu c ghi vo.
ADLAR=0:
ADLAR=1:
Thng thng, 2 thanh ghi data c sp xp theo nh dng ADLAR=0,

ADCL cha 8 bit thp v 2 bit thp ca ADCH cha 2 bit cao nht ca gi tr thu
c. Ch th t c gi tr t 2 thanh ghi ny, trnh c sai kt qu, bn cn
c thanh ghi ADCL trc v ADCH sau, v sau khi ADCH c c, cc thanh
ghi data c th c cp nht gi tr tip theo.
- SFIOR(Special FunctionIO Register C): thanh ghi chc nng c bit, 3 bit
cao trong thanh ghi ny quy nh ngun kch ADC nu ch Auto Trigger c
s dng. l cc bit ADTS2:0 (Auto Trigger Source 2:0). Cc loi ngun kch
c trnh by trong bng 5.
Bng 5: Ngun kch ADC trong ch Auto Trigger.
2. S dng ADC- Chuyn i n knh.

Khi nim n knh c hiu l i lng cn chuyn i l cc in p t
trc tip trn cc chn analog ca chip, gi tr in p ny c so snh vi 0V ca
chip, hay ni mt cch khc, in p cn chuyn i v chip AVR c mass
chung. Chng ta s minh ha cch s dng ADC trn AVR ch n knh
bng v d c v hin th gi tr ADC trn cc LED 7 on. Nh minh ha trong
hnh 4, chng ta s dng 4 LED hin th 4 ch s ca kt qu, do chng ta u
bit ADC trn AVR c phn gii 10 bit nn kt qu chuyn i ti a l 1023, 4
LED l hin th kt qu ny. 4 chip 7447 c dng iu khin 4 LED,
chng ta cn 16 ng xut d liu hin th ln 4 LED v th PORTB v
PORTC s c dng cho mc ch ny. 4 bit cao ca PORTC(PC4:7) cha ch s
hng nghn ca kt qu, 4 bit thp PC0:3 cha ch s hng trm, 4 bit cao ca
PORTB(PB4:7) dng xut ch s hng chc v 4 bit PB0:3 dnh cho ch s hng
n v. i lng cn chuyn i l in p trn chn ADC0 (knh 0 ca ADC,
chn 0 trong PORTA chip ATmega32), in p c to ra bng mt bin tr RV1.
Thay i gi tr bin tr, in p ri trn ADC0 thay i v c cp nht trc tip
trn cc LED. Gi tr hin th trn LED khng phi l gi tr in p m l gi tr
tng i sau khi chuyn i. Trong v d ny, ti s trnh by dng tng qut, vic
c ADC v hin th LED c vit trong cc chng trnh con tng ng. Bng
cch ny, cc bn c th d dng sa i v m rng v d sau ny.
Hnh 4. c ADC n knh.

List 1 trnh by on code minh ha c ADC n knh v hin th kt qu trn
LED 7 on.
List 1. c ADC n knh v hin th bng LED 7 on.
Ti tm thi chia on chng trnh thnh 4 phn, phn 1 l cc nh ngha

(dng 4 n 7), phn 2 l chng trnh con c ADC n knh (dng 10 n 14),
phn 3 l chng trnh con hin th mt gi tr 4 ch s ln 4 LED 7 on (t dng
17 n 30) v phn 4 l chng trnh chnh. Chng ta s tm hiu theo tng phn.
- Phn 1: ba dng 4, 5 v 6 chng ta nh ngha 3 bin i din tn ca 3 mode
in p tham chiu c th dng cho ADC. Xem li bng 2 chng ta bit rng in
p tham chiu c chn thng qua 2 bit REFS trong thanh ghi ADMUX, c 3 loi
in p c th c chn. Bin AREF_MODE tng ng vi trng hp chng ta
mun ly in p trn chn AREF lm in p tham chiu, i chiu bng 2 chng
ta cn set 2 bit REFS bng 0, v dng 4 #define AREF_MODE
0 thc
hin vic ny. Tng t, bin INT_MODE i din cho trng hp in p tham
chiu ni 2.56V v c nh ngha cho php set 1 bit REFS ln 1 #define
INT_MODE
(1<<REFS1)|(1<<REFS0). Bin AVCC_MODE i din trng
hp in p tham chiu ly t chn AVCC. Cui cng, bin ADC_VREF_TYPE
c nh ngha l bin chn mode m chng ta thc s mun dng cho ADC,
trong v d ny ti chn in p tham chiu ly t chn AVCC v th ti nh ngha
#define ADC_VREF_TYPE AVCC_MODE. Bit ADC_VREF_TYPE s c
gn cho thanh ghi ADMUX khi khi ng ADC trong chng trnh chnh.
- Phn 2-chng trnh con c ADC n knh uint16_t
read_adc(unsigned char adc_channel): tn chng trnh l read_adc v
adc_channel l tham s cn truyn cho chng trnh con, tham s ny l ch s
knh mun c (t knh 0 n knh 7). Gi tr tr v l mt s nguyn khng du
16 bit (kiu unsigned int ca C), tuy nhin trong v d ny ti dng kiu d liu
uint16_t thay cho unsigned int, uint16_t l mt cch nh ngha kiu d liu
nguyn khng du 16 bit ca ring th vin gcc-avr. Dng u tin ca on
chng trnh con (dng 11) l khai bo knh mun c bng cch ghp gi tr knh
cho thanh ghi ADMUX ADMUX =adc_channel | ADC_VREF_TYPE ;. Xem li
cu trc thanh ghi ADMUX, trong thanh ghi ny, ngoi cc bit chn ngun in p
tham chiu REFS th 5 bit thp MUX4:0 cho php chn knh ADC cn c. Tham
kho thm bng 3 chng ta thy rng 8 gi tr u tin ca cc bit MUX4:0 (t
00000 n 00111 nh phn) tng ng vi 8 knh n ADC0:7. Chnh s sp xp
ny cho php chng ta ghp trc tip gi tr knh mun c vo thanh ghi
ADMUX thng qua dng lnh ADMUX =adc_channel | ADC_VREF_TYPE.
Chng ta dng php OR "|" ghp gi tr knh mun c v ch tham chiu
ca ADC trc khi gn cho thanh ghi ADMUX. Mt ch quan trng l gi tr ca
tham s adc_channel ch trong khong t 0 n 7 tng ng vi 8 ch c n
knh ADC trong bng 3. Sau khi knh c chn, dng 12 set bit ADCS trong
thanh ghi ADCSRA bt u qu trnh chuyn i ADCSRA|=(1<<ADSC);.
Nh cp trong khi kho st chc nng ca bit ADIF trong thanh ghi
ADCSRA, sau khi qu trnh chuyn i kt thc bit ADIF s c t ng set ln

1, v th dng code 13 c dng ch cho bit ny ln 1, tc ch cho qu trnh
chuyn i kt thc. Cu lnh loop_until_bit_is_set(ADCSRA,ADIF); c hiu
l lp cho n khi bit ADIF trong thanh ghi ADCSRA c set ln 1, lnh
loop_until_bit_is_set ny c nh ngha sn trong th vin gcc-avr. Nu qu
trnh chuyn i kt thc, kt qu chuyn i s c cha trong 2 thanh ghi
ADCL v ADCH, 2 thanh ghi ny c t ng gp thnh thanh ghi 16 bit ADCW
(ADC WORD), dng 14 return ADCW tr v kt qu chuyn i.
- Phn 3-chng trnh con hin th s c 4 ch s ln 4 LED 7 on void
LED7_out(uint16_t val) : val l s cn hin th, chng ta khai bo 4 bin tm
dvi, chuc, tram, nghin i din cho cc ch s n v, chc, trm v nghn
dng 18. ng thi, mt bin tm temp_val c dng lu gi tr tm thi ca
s val nh trong dng 19 temp_val=val;, cch lm ny nhm trnh thay i gi
tr ca bn thn val trong qu trnh thao tc. Cc dng code t 21 n 26 thc hin
qu trnh tch s val ra thnh 4 cc ch s hng n v, chc, trm v nghn. y
ch l phng php i s thng thng nn ti s khng gii thch thm cho on
ny. Hai dng 28 v 29 xut gi tr ra 4 LED 7 on. Bn LED 7 on c iu
khin bi cc IC chuyn m 7447, gi tr input choc cc IC 7447 l cc s BCD 4
bit. V th, xut 4 ch s ra 4 LED thng qua 7447 chng ta cn 4x4=16 bit,
trong v d ny ti dng PORTB v PORTC cho nhim v ny. Bn bit cao ca
PORTC s cha ch s hng nghn, bn bit thp cha ch s hng trm, bn bit
cao ca PORTB cha ch s hng chc v bn bit thp PORTB cha s n v.
Dng code 28 PORTB=(chuc<<4)+dvi; xut 2 ch s chc v n v ra PORTB,
trong hm chuc<<4 ngha l dch ch s hng chc sang tri 4 v tr a
ch s ny ln 4 bit cao ca PORTB, sau cng ch s n v vo 4 bit thp v
cui cng l xut ra PORTB. Tng t chng ta c th xut 2 ch s hng nghn v
hng trm ra PORTC thng qua dng code 29 PORTC=(nghin<<4)+tram.
- Phn 4-chng trnh chnh: do hu ht cc nhim v c thc hin
trong cc on chng trnh con nn chng trnh chnh trong v d ny kh n
gin. Hai dng code 32 v 33 set cc thng s cho ADC, dng 32
ADCSRA=(1<<ADEN)|(1<<ADPS2)|(1<<ADPS0); set cc bit trong thanh ghi
iu khin ADCSRA, ADC c cho php hot ng bi bit ADEN, cc bit
ADPS2:0 chn prescaler xung clock (xem li phn m t thanh ghi ADCSRA),
trong v d ny ti chn prescaler = 32 (bn c th chn gi tr khc). Dng 33
ADMUX=ADC_VREF_TYPE; cho php chn in p tham chiu bng cch
gn bin ADC_VREF_TYPE m chng ta nh ngha trong dng code 7 cho
thanh ghi ADMUX. Bn cn ch l sau khi thc hin 2 dng code ny, ADC ch
mi t th sn sng nhng vn cha hot ng, ADC s hot ng khi chng ta
gi chng trnh con c adc. Trong vng lp while ca chng trnh chnh chng
ta ln lt c gi tr ADC knh 0 bng cch gi chng trnh con read_adc(0)

dng lnh 39 ADC_val=read_adc(0); sau hin th ra LED 7 on dng 40
LED7_out(ADC_val); v cui cng l delay 1 khong thi gian nh (100ms)
trc khi lp li qu trnh c v hin th.
M phng v d: To 1 project bng Programmer Notepad v type on code trn
vo file source (xem phn to Project vi WinAVR). Bin dch v chy m phng
vi mch in trong hnh 4. iu chnh gi tr bin tr RV1 thay i gi tr in
p input ca ADC knh 0 v xem gi tr hin th trn cc LED 7 on. Hy thay i
gi tr bin ADC_VREF_TYPE trong dng code 7 sang cc mode khc nh
INT_MODE, bin dch v m phng li chng trnh, quan st v so snh s khc
nhau gia cc mode in p tham chiu. Bn s d dng nhn thy rng khi chn
in p tham chiu ni 2.56V, khi tng bin tr n khong gia th kt qu chuyn
i s l 1023(gi tr ln nht ca s 10 bit) v nu tip tc tng bin tr gi tr ny
s khng thay i. iu ny c ngha l nu in p input ln hn in p tham
chiu th kt qu chuyn i s l 1023.
Phn chuyn i ADC ch so snh s c trnh by trong 1 dp khc
phn ng dng.
Bi 7 - Giao tip SPI
5
( 76 Votes )
Ni dung
1.
Gii thiu.

Cu trc AVR.
AVRStudio.
2.
Chun truyn thng SPI.
C cho AVR.
3.
Truyn thng SPI trn AVR.
M phng vi Proteus.
Download v d
Text LCD
I. Gii thiu.
Bi ny gip cc bn bit cch s dng cch truyn thng ni tip ng b SPI.
Cng c chnh cng l 2 b phn mm AVRStudio (+gcc-avr) v Proteus. Thc
cht ngn ng lp trnh vn l gcc-avr nhng ti khng dng Programmer Notepad
bit code nh thng thng, thay vo ti dng AVRStudio lm trnh bin tp,
bn tham kho thm phn Lp trnh C bng AVRStudio trong bi hng dn s
dng AVRStudio bit thm cch thc hin. Ti s dng chip ATmega32 lm
minh
ha.
Nguyn l truyn thng ni tip SPI.
S dng module SPI trong AVR cc ch Master v Slave.

II. Chun truyn thng SPI,
SPI (Serial Peripheral Bus) l mt chun truyn thng ni tip tc cao do
hang Motorola xut. y l kiu truyn thng Master-Slave, trong c 1 chip
Master iu phi qu trnh tuyn thng v cc chip Slaves c iu khin bi
Master v th truyn thng ch xy ra gia Master v Slave. SPI l mt cch truyn
song cng (full duplex) ngha l ti cng mt thi im qu trnh truyn v nhn c
th xy ra ng thi. SPI i khi c gi l chun truyn thng 4 dy v c 4
ng giao tip trong chun ny l SCK (Serial Clock), MISO (Master Input
Slave Output), MOSI (Master Ouput Slave Input) v SS (Slave Select). Hnh 1 th
hin mt kt SPI gia mt chip Master v 3 chip Slave thng qua 4 ng.
SCK: Xung gi nhp cho giao tip SPI, v SPI l chun truyn ng b nn
cn 1 ng gi nhp, mi nhp trn chn SCK bo 1 bit d liu n hoc i. y
l im khc bit vi truyn thng khng ng b m chng ta bit trong chun
UART. S tn ti ca chn SCK gip qu trnh tuyn t b li v v th tc

truyn ca SPI c th t rt cao. Xung nhp ch c to ra bi chip Master.
MISO Master Input / Slave Output: nu l chip Master th y l ng
Input cn nu l chip Slave th MISO li l Output. MISO ca Master v cc
Slaves
c
ni
trc
tip
vi
nhau..
MOSI Master Output / Slave Input: nu l chip Master th y l ng
Output cn nu l chip Slave th MOSI l Input. MOSI ca Master v cc Slaves
c ni trc tip vi nhau.
SS Slave Select: SS l ng chn Slave cn giap tip, trn cc chip Slave
ng SS s mc cao khi khng lm vic. Nu chip Master ko ng SS ca
mt Slave no xung mc thp th vic giao tip s xy ra gia Master v Slave
. Ch c 1 ng SS trn mi Slave nhng c th c nhiu ng iu khin SS
trn Master, ty thuc vo thit k ca ngi dng.
.
Hnh 1. Giao din SPI.
Hot ng: mi chip Master hay Slave c mt thanh ghi d liu 8 bits. C
mi xung nhp do Master to ra trn ng gi nhp SCK, mt bit trong thanh ghi
d liu ca Master c truyn qua Slave trn ng MOSI, ng thi mt bit
trong thanh ghi d liu ca chip Slave cng c truyn qua Master trn ng
MISO. Do 2 gi d liu trn 2 chip c gi qua li ng thi nn qu trnh truyn
d liu ny c gi l song cng. Hnh 2 m t qu trnh truyn 1 gi d liu

thc hin bi module SPI trong AVR, bn tri l chip Master v bn phi l Slave.
Hnh 2. Truyn d liu SPI.

Cc ca xung gi nhp, phase v cc ch hot ng: cc ca xung gi nhp
(Clock Polarity) c gi tt l CPOL l khi nim dng ch trng thi ca chn
SCK trng thi ngh. trng thi ngh (Idle), chn SCK c th c gi mc
cao (CPOL=1) hoc thp (CPOL=0). Phase (CPHA) dng ch cch m d liu
c ly mu (sample) theo xung gi nhp. D liu c th c ly mu cnh ln
ca SCK (CPHA=0) hoc cnh xung (CPHA=1). S kt hp ca SPOL v CPHA
lm nn 4 ch hot ng ca SPI. Nhn chung vic chn 1 trong 4 ch ny
khng nh hng n cht lng truyn thng m ch ct sao cho c s tng
thch gia Master v Slave.
III. Truyn thng SPI trn AVR.
Module SPI trong cc chip AVR hu nh hon ton ging vi chun SPI m t
trong phn trn. V th, nu hiu cch truyn thng SPI th s khng qu kh
thc hin vic truyn thng ny vi AVR. Phn bn di ti trnh by mt s im
quan trng khi iu khin SPI trn AVR.
Cc chn SPI: Cc chn giao tip SPI cng chnh l cc chn PORT thng thng,
v th nu mun s dng SPI chng ta cn xc lp hng cho cc chn ny. Trn
chip ATmega32, cc chn SPI nh sau:
SCK PB7 (chn 8)
MISO PB6 (chn 7)
MOSI PB5 (chn 6)
SS
PB4 (chn 5)
Khi chip AVR c s dng lm Slave, bn cn set cc chn SCK input, MOSI
input, MISO output v SS input. Nu l Master th SCK output, MISO output,
MOSI input v khi ny chn SS khng quan trng, chng ta c th dng chn ny
iu khin SS ca Slaves hoc bt k chn PORT thng thng no.
Thanh ghi: SPI trn AVR c vn hnh bi 3 thanh ghi bao gm thanh ghi
iu khin SPCR , thanh ghi trng thi SPSR v thanh ghi d liu SPDR.
SPCR (SPI Control Register): l 1 thanh ghi 8 bit iu khin tt c hot ng
ca SPI.
* Bit 7- SPIE (SPI Interrupt Enable) bit cho php ngt SPI. Nu bit ny c
set bng 1 v bit I trong thanh ghi trng thi c set bng 1 (sei), 1 ngt s xy ra
sau khi mt gi d liu c truyn hoc nhn. Chng ta nn dng ngt (nht l
i vi chip Slave) khi truyn nhn d liu vi SPI.
* Bit 6 SPE (SPI Enable). set bit ny ln 1 cho php b SPI hot ng. Nu
SPIE=0 th module SPI dng hot ng.
* Bit 5 DORD (Data Order) bit ny ch nh th t d liu cc bit c
truyn v nhn trn cc ng MISO v MOSI, khi DORD=0 bit c trng s ln
nht ca d liu c truyn trc (MSB) ngc li khi DORD=1, bit LSB c
truyn trc. Tht ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan
trng nhng phi m bo cc bit DORD ging nhau trn c Master v Slaves.
* Bit 4 MSTR (Master/Slave Select) nu MSTR =1 th chip c nhn din l
Master, ngc li MSTR=0 th chip l Slave..
* Bit 3 v 2 CPOL v CPHA y chnh l 2 bit xc lp cc ca xung gi nhp
v cnh sample d liu m chng ta kho st trong phn u. S kt hp 2 bit
ny to thnh 4 ch hot ng ca SPI. Mt ln na, chn ch no khng
quan trng nhng phi m bo Master v Slave cng ch hot ng. V th c
th 2 bit ny bng 0 trong tt c cc chip. Hnh 3 trnh by cch sample d liu
trong 4 ch ca SPI trn AVR.
ra khi giao tip gia 2 AVR vi nhau, th t ny khng quan

trng nhng phi m bo cc bit DORD ging nhau trn c
Master v
Slaves.
CPHA=0
CPHA=1
Hnh 3. Cc ch hot ng ca SPI.

* Bit 1:0 CPR1:0 hai bit ny kt hp vi bit SPI2X trong thanh ghi SPSR
cho php chn tc giao tip SPI, tc ny c xc lp da trn tc ngun
xung clock chia cho mt h s chia. Bng 1 tm tt cc tc m SPI trong AVR
c th t. Thng thng, tc b ny khng c ln hn 1/4 tc xung nhp cho
chip.
SPSR (SPI Status Register): l 1 thanh ghi trng thi ca module SPI. Trong
thanh ghi ny ch c 3 bit c s dng. Bit 7 SPIF l c bo SPI, khi mt gi
d liu c truyn hoc nhn t SPI, bit SPIF s t ng c set len 1. Bit 6
WCOL l bt bo va chm d liu (Write Colision), bit ny c AVR set ln 1
nu chng ta c tnh vit 1 gi d liu mi vo thanh ghi d liu SPDR trong khi
qu trnh truyn nhn trc cha kt thc. Bit 0 SPI2X gi l bit nhn i tc
truyn, bit ny kt hp vi 2 bit SPR1:0 trong thanh ghi iu khin SPCR xc lp
tc cho SPI.
SPDR (SPI Data Register): l thanh ghi d liu ca SPI. Trn chip Master, ghi
gi tr vo thanh ghi SPDR s kch qu trnh tuyn thng SPI. Trn chip Slave, d
liu nhn c t Master s lu trong thanh ghi SPDR, d liu c lu sn trong
SPDR s c truyn cho Master.
S dng SPI trn AVR: SPI trn AVR hot ng khng khc nguyn l chung
ca chun SPI l my. Vn hnh SPI trn AVR c thc hin da trn vic ghi v
c 3 cc thanh ghi SPCR, SPSR v SPDR. Trc khi truyn nhn bng SPI chng
ta cn khi ng SPI, qu trnh khi ng thng bao gm chn hng giao tip
cho cc chn SPI, chn loi giao tip: Master hay Slave, chn ch SPI (SPOL,
SPHA) v chn tc giao tip. Truyn thng SPI lun c khi xng bi chip
Master, khi Master mun giao tip vi 1 Slave no , n s ko chn SS ca Slave
xung mc thp (gi l chn a ch) v sau vit d liu cn truyn vo thanh
ghi d liu SPDR, khi d liu va c vit vo SPDR xung gi nhp s c t
ng to ra trn SCK v qu trnh truyn nhn bt u. i vi cc chip Slave, khi
chn SS b ko xung n s sn sng cho qu trnh truyn nhn. Khi pht hin
xung gi nhp trn SCK, Slave s bt u sample d liu n trn ng MOSI v
gi d liu di trn MISO.
minh ha cho cch truyn v nhn d liu SPI trn AVR, ti s thc hin
mt v d truyn nhn 1 chiu vi 1 chip Master v 3 chip Slaves. Tt c cc chip
c dng l ATmega32, chip Master s iu khin cc chip Slaves thng qua 3
ng chn chip PB0, PD1 v PD2. Cng vic thc hin trong v d ny nh sau:
Master s ln lt chn 1 trong 3 chip Slaves v gi cc gi d liu tng ng n
chng, chip Slave0 s nhn c cc con s t 0 n 80, Slave1 nhn 80 n 160
v Slave2 nhn d liu t 160 n 240. Cc Slave s hin th gi tr m mnh nhn
c trn cc Text LCD kt ni vi PORTD mi Slave. S mch in v bng
Proteus cho v d ny c trnh by trong hnh 4.
Hnh 4. M phng v d giao tip SPI trn AVR.

Trong bi ny, ti s dng phn mm AVRStudio kt hp vi gcc-avr trong
WinAVR lp trnh bng ngn ng C cho AVR. Bn hy tham kho thm bi
AVRStudio bit cch to 1 Project lp trnh C cho AVR bng AVRStudio. Hy

to 2 Project ring, 1 Project c tn SPI_Master cho chip Master v 1 Project c
tn SPI_Slave dng chung cho c 3 Slaves. Copy file myLCD.h dng cho iu
khin Text LCD c to trong bi Text LCD vo c 2 th mc cha 2 Projects
mi to. Vit on code trong list 0 vo file SPI_Master.c v on code trong list 1
vo file SPI_Slave.c.
List 1. on code cho SPI Master.
Ti s gii thch s lt mt s im chnh trong on code cho chip Master.

Cc phn nh ngha t dng th 10 n dng 17 ch c tc dng lm cho chng
trnh d c hiu hn v c tnh tng thch cao hn, v d nu bn mun s dng
v d ny cho cc chip khc bn ch cn thay i cc nh ngha ny m khng phi
thay i trong ni dung cc chng trnh con. Chng ta nh ngha chn
PORTB iu khin cc ng chn chip SS ca Slave (gi l cc ng a ch),
dng 18 nh ngha Slave(i) l th t chn trn PORT dng cho chip Slave th i.
D hiu hn, ng SS trn Slave0 s c kt ni v iu khin bi chn 0 ca
PORTB (chn PB0 v tng t cho cc Slaves cn li. Bin wData nh ngha trn
dng 20 l mt mng 3 phn t cha cc con s 8 bits s truyn n cc Slaves.
Chng trnh con void SPI_MasterInit(void): Chng trnh ny khi ng
cho chip Master, vic khi ng trc ht l set hng cho cc chn SPI. i vi
Master, cc chn to xung gi nhp SCK v chn truyn d liu MOSI cn c set
Output nh trong dng 24, cc chn SPI cn li l input. Dng 25 gip ko in tr
ko ln chn nhn d liu MISO ca Master. Dng lnh 26 SPCR=(1<<SPIE)|
(1<<SPE)|(1<<MSTR)|(1<<CPHA)|(1<<SPR1)|(1<<SPR0); tht s khi ng
SPI vi vic set bit SPIE: cho php ngt SPI=1, bit SPE=1 cho php SPI hot
ng, MSTR=1 xc lp chip l chip Master. CPHA=1 tc chn SCK s mc thp
khi SPI khng hot ng, trong khi CPOL=0 (khng set CPOL th mc nh l 0)
th d liu s c sample (ly mu) cnh xung ca xung SCK. Cui cng c 2
bit SPR1 v SPR0 u c set ln 1, tc SPI s bng tc ngun cung nui
chip chia cho 128 (xem bng 1). Dng code 29 set hng Output cho cc chn
dng lm chn a ch chn chip Slaves (cc chn PB0, PB1, PB2), sau ko cc
chn ny ln mc cao disable tt c cc Slaves (sau ny s kch hot sau).
Chng trnh con void SPI_Transmit(uint8_t i, uint8_t data): chng
trnh truyn d liu qua SPI ca chip Master, chng trnh c 2 tham s l a ch
chip Slave (bin i) v d liu cn truyn (bin data). Trc khi truyn d liu,
Master s thc hin vic chn Slave, dng 35 cbi(ADDRESS_PORT, Slave(i));
thc hin vic ny. Thc cht dng ny l ko chn i ca PORTB xung mc
thp, cng l ko chn SS ca Slave xung mc thp. Dng 36 gn gi tr cn
truyn cho thanh ghi d liu SPDR=data, sau khi gn gi tr cho SPDR, xung
clock s t ng c Master to ra trn SCK, qu trnh truyn bt u. Qu trnh
truyn kt thc th bit c SPIF trong thanh ghi trng thi SPSR c set ln 1,
dng 36 thc hin vic ch bit c SPIF kt thc qu trnh truyn. Khi kt thc
truyn 1 byte cho Slave, set chn SS ca Slave ln mc cao v hiu ha SPI,
dng 37.
Chng trnh chnh: chng trnh chnh cho chip Master SPI tng i n
gin, trc ht chng ta cn gi chng trnh con khi ng SPI dng 43. Trong
vng lp v tn while, ln lt gi cc gi tr n cc Slaves. Dng 46 gi chng
trnh con gi gi tr bin wData[0] n Slave0, dng 50 truyn bin wData[1] cho
Slave1 v dng 54 truyn bin wData[2] cho Slave2
List 2.on code cho Slave SPI.
on code trong list 2 l on code cho chip Slaves, ch dng 3 chng ta

include file header interrupt.h v vic nhn d liu SPI ca SLave c thc hin
bng ngt SPI. Cc nh ngha bin trong cc dng code t 8 n 15 tng t nh
trong chng trnh cho chip Master. Ti s tp trung gii thch cc im khc bit
cho Slaves.
Chng trnh con void SPI_SlaveInit(void): Chng trnh ny khi ng
cho chip Slave, cng ging nh trng hp ca Master, vic khi ng trc ht l
set hng cho cc chn SPI. i vi Slave, ch c chn truyn d liu MISO l cn
c set Output nh trong dng 19, cc chn SPI cn li l input. Dng 20 gip
ko in tr ko ln cc chn nhn d liu MOSI ca Slave, v chn chn Slave
SS. Vic tip theo l ci t cc thanh ghi SPI nh trong dng lnh 21,
SPCR=(1<<SPIE)|(1<<SPE)|(1<<CPHA)|(1<<SPR1)|(1<<SPR0); , nu quan st
dng lnh 26 trong List 1 chop chip Master, dng ny khng khc l my, qu trnh
khi ng SPI cho Slave tng t Master vi mt im khc duy nht l bit
MSTR, bit ny khng c set ln 1 i vi Slaves.
Trnh phc v ngt ISR(SPI_STC_vect): SPI trn AVR ch c duy nht
mt s kin gy ra ngt l khi qu trnh truyn-nhn kt thc. Tn vector ngt
SPI trong ngn ng lp trnh avr-gcc l SPI_STC_vect. Trong v d ny, khi mt
ngt SPI xy ra Slave, chng ta s c thanh ghi SPDR v sau hin th gi tr
c c trn LCD. Dng 37, rData=SPDR, gn thanh ghi SPDR cho bin rData.
T dng 38 n 42 l cch hin th gi tr c v trn Text LCD bng th vin
myLCD (xem bi Text LCD). Dng 39 chng ta khai bo 1 bin tm dng mng
ng, dis, lm buffer cha gi tr ascii ca cc k t cn hin th ln LCD. Ch l
gi tr nhn v l 1 con s 8 bit, mun hin th gi tr ny ln LCD chng ta khng
th hin th trc tip bng lnh putChar_LCD v hm putChar_LCD xem tham s
nhp vo l m Ascii, v d chng ta nhn v s rData=65, nu dng hm
putChar_LCD(rData) th trn LCD ch thy k t A v 65 l m Ascii ca k t
A. LCD hin th 65 chng ta xem 65 l mt chui cc k t, trc ht cn
chuyn s 65 thnh cc k t 6 v 5, hm sprintf(dis,"%i",rData) trong dng
code 40 thc hin vic nh dng li bin rData thnh chui cc k t v cha
trong buffer dis, %i l c nh dng, bo cho hm sprintf xem rData l mt s
nguyn. Sau dng 40, v d rData=65, th dis=65. Dng 42 in chui dis ln LCD:
print_LCD(dis);.
Chng trnh chnh: chng trnh chnh cho chip Slave khng lm nhiu
vic v cc vic chnh nh nhn v hin th c thc hin trong trnh phc v
ngt SPI. Dng 27 sei() cho php ngt ton cc, iu ny l cn thit ngt SPI
c th xy ra, dng 28 gi chng trnh con khi ng SPI cho Slave, sau khi
ng LCD dng 29 v kt thc. Khng c vic g cn thc hin trong vng lp

while().
Bi 8 - Giao tip TWI - I2C
5
( 41 Votes )
Ni dung
1.
Bn s i n u.
Cu trc AVR.
2.
Giao din TWI I2C.
WinAVR.
3.
TWI trn AVR.
4.
iu khin AVR TWI.
C cho AVR.
M phng vi Proteus.
Download v d
I. Bn s i n u.
Bi ny gii thiu cch giao tip bng truyn thng ni tip ng b Two-Wire
Serial (TWI) tng thch vi chun I2C. Trong bi ny chng ta s kho st 2 mode
truyn v nhn trn chip Master cng vi 2 mode truyn v nhn trn chip Slave.
Cng c chnh cng l 2 b phn mm WinAVR v Proteus. Vi iu khin
ATmega32 s c dng lm minh ha.
Nguyn l truyn thng ni tip TWI v I2C.

S dng module TWI trong AVR cc ch Master.
S dng module TWI trong AVR cc ch Slave.
V d giao tip gia cc AVR bng TWI.
II. Giao din TWI I2C.

TWI (Two-Wire Serial Intereafce) l mt module truyn thng ni tip ng b
trn cc chip AVR da trn chun truyn thng I2C. I2C l vit tc ca t InterIntegrated Circuit l mt chun truyn thng do hng in t Philips
Semiconductor sng lp v xy dng thnh chun nm 1990. Phin bn mi nht
ca I2C l V3.0 pht hnh nm 2007. hiu thm v I2C bn c th tham kho
cc ti liu I2C Specification t trang web ca NXP- http://www.nxp.com(lp
bi Philips). Trong phm vi bi hc ny ti ch gii thiu giao thc TWI c gii
thiu trong datasheet ca cc chip AVR t Atmel. Tuy nhin, v c bn TWI trong
AVR hon ton tng thch I2C, do tm hiu TWI ca AVR khng ch gip bn
giao tip gia cc AVR vi nhau m c th dng TWI iu khin bt k mt
thit b no theo chun I2C (cc chip nh, b chuyn i ADC, DCA, ng h thi
gian thc).
TWI (I2C) l mt truyn thng ni tip a chip ch (tm dch ca cm t
multi-master serial computer bus). Khi nim multi-master (ti s dng t ting
anh multi-master thay v dng a chip ch) c hiu l trong trn cng mt bus
c th c nhiu hn mt thit b lm Master, ng thi mt Slave c th tr thnh
mt Master nu n c kh nng. V d trong mt mng TWI ca nhiu AVR kt ni
vi nhau, bt k mt AVR no u c th tr thnh Master mt thi im no .
Tuy nhin nu mt mng dng mt AVR iu khin cc chip nh (nh EEPROM
AT24C1024 chng hn) th khi nim multi-master khng tn ti v cc chip nh
c thit k sn l Slave, khng c kh nng tr thnh master. TWI (I2C) c
thc hin trn 2 ng SDA (Serial DATA) v SCL (Serial Clock) trong SDA l
ng truyn/nhn d liu v SCL l ng xung nhp. Cn c theo chun I2C,
cc ng SDA v SCL trn cc thit b c cu hnh cc gp m (open-drain
hoc open-collector, tham kho cc mch s dng transistor hiu thm), ngha l
cn c cc in tr ko ln (pull-up resistor) cho cc ng ny. trng thi
ngh (Idle), 2 chn SDA v SCL mc cao. Hnh 1 m t mt m hnh mng TWI
(I2C) c bn.
Hnh 1. Mng TWI (I2C) vi nhiu thit b v 2 in tr ko ln cho SDA, SCL.

Tip theo chng ta tm hiu mt s khi nim v c im ca TWI. Cc
khi nim v c im ti cp di y c dng cho c TWI v I2C, nu c
s khc bit ti s gii thch thm.
Master: l chip khi ng qu trnh truyn nhn, pht i a ch ca thit b
cn giao tip v to xung gi nhp trn ng SCL.
Slave: l chip c mt a ch c nh, c gi bi Master v phc v yu cu
t Master.
SDA- Serial Data: l ng d liu ni tip, tt c cc thng tin v a ch
hay d liu u c truyn trn ng ny theo th t tng bit mt. Ch l
trong chun I2C, bit c trng s ln nht (MSB) c truyn trc nht, c im
ny ngc li vi chun UART.
SCL Serial Clock: l ng gi nhp ni tip. TWI (I2C) l chun truyn
thng ni tip ng b, cn c 1 ng to xung gi nhp cho qu trnh
truyn/nhn, c mi xung trn ng gi nhp SCL, mt bit d liu trn ng
SDA s c ly mu (sample). D liu ni tip trn ng SDA c ly mu khi
ng SCL mc cao trong mt chu k gi nhp, v th ng SDA khng c
i trng thi khi SCL mc cao (tr START v STOP condition). Chn SDA c
th c i trng thi khi SCL mc thp.
START Condition-iu kin bt u: t trng thi ngh, khi c SDA v SCL

mc cao nu Master mun thc hin mt cuc gi, Master s ko chn SDA
xung thp trong khi SCL vn cao. Trng thi ny gi l START Condition (chng
ta gi tt l S).
STOP Condition-iu kin kt thc: sau khi thc hin truyn/nhn d liu,
nu Master mun kt thc qu trnh n s to ra mt STOP condition. STOP
condition c Master thc hin bng cch ko chn SDA ln cao khi ng SCL
ang mc cao. STOP condition ch c to ra sau khi a ch hoc d liu
c truyn/nhn.
REPEAT START Bt u lp li: khong gia START v STOP condition
l khong bn ca ng truyn, cc Master khc khng tc ng c vo ng
truyn trong khong ny. Trng hp sau khi kt thc truyn/nhn m Master
khng gi STOP condition li gi thm 1 START condition gi l REPEAT
START. Kh nng ny thng c dng khi Master mun ly d liu lin tip t
cc Slaves. Hnh bn di m t cc Master to ra START, STOP v REPEAT
START.
Address Packet Format nh dng gi a ch: trn mng TWI (I2C), tt

c cc thit b (chip) u c th l Master hay Slave. Mi thit b c mt a ch c
nh gi l Device address. Khi mt Master mun giao tip vi mt Slave no ,
n trc ht to ra mt START condition v tip theo l gi a ch Device address
ca Slave cn giao tip trn ng truyn, v th xut hin khi nim gi a ch
(Address Packet). Gi a ch trong TWI (I2C) c nh dng 9 bits trong 7 bit
u (gi l SLA, c gi lin sau START condition) cha a ch Slave, mt bit
READ/WRITE v mt bit ACK-Ackknowledge (xc nhn). Do bit a ch c
di 7 bits nn v mt l thuyt, trn 1 mng TWI (I2C) c th tn ti ti a
2^7=128 thit b c a ch ring bit. Tuy nhin, c mt s a ch khng c s
dng nh cc a ch c nh dng 1111xxx (tc cc a ch ln hn hoc bng 120
khng c dng). Ring a ch 0 c dng cho cuc gi chung (General call).
Bit READ/WRITE (R/W) c truyn tip sau 7 bit a ch l bit bo cho Slave
bit Master mun c hay ghi vo Slave. Nu bit ny bng 0 (gi l W) th qu
trnh Ghi d liu t Master n Slave c yu cu, nu bit ny bng 1 (gi l R)
th Master mun c d liu t Slave v. Tm bits trn (SLA+R/W) c Master
pht ra sau khi pht START condition, nu mt Slave trn mng nhn ra rng a
ch m Master yu cu trng khp vi Device address ca chnh mnh, n s p
tr li Master bng cch pht ra 1 tn hiu xc nhn ACK bng cch ko chn
SDA xung thp trong xung th 9. Ngc li, nu khng c Slave p ng li,
chn SDA vn mc cao trong xung gi nhp th 9 th gi l tn hiu khng xc
nhn NOT ACK, lc ny Master cn c nhng ng x ph hp ty theo mi
trng hp c th, v d Master c th gi STOP condition v sau pht li a
ch Slave khcNh vy, trong 9 bit ca gi a ch th ch c 8 bit c gi bi
Master, bit cn li l do Slave. V d Master mun yu cu c d liu t Slave
c a ch 43, n cn pht i mt byte nh sau trn ng truyn: (43<<1)+1,
trong (43<<1) l dch s 43 v bn tri 1 v tr v 7 bit a ch nm cc v tr
cao trong gi a ch, sau cng gi tr ny vi 1 tc l qu trnh c c
yu cu.
General call Cuc gi chung: khi Master pht i gi a ch c dng 0

(thc cht l 0+W) tc n mun thc hin mt cuc gi chung n tt c cc Slave.
Tt nhin, cho php hay khng cho php cuc gi chung l do Slave quyt nh.
Nu cc Slave c ci t cho php cuc gi chung, chng s p li Master bng
ACK. Cuc gi chung thng xy ra khi Master mun gi d liu chung n cc
Slaves. Ch l cuc gi chung c dng 0+R l v ngha v khng th c chuyn
Master nhn d liu t tt c cc Slave cng thi im.
Data Packet Format nh dng gi d liu: sau khi a ch c pht
i, Slave p li Master bng ACK th qu trnh truyn/nhn d liu s din ra
gia cp Master/Slave ny. Ty vo bit R/W trong gi a ch, d liu c th c
truyn theo hng t Master n Slave hay t Slave n Master. D di chuyn theo
hng no, gi d liu lun bao gm 9 bits trong 8 bits u l d liu v 1 bit
cui l bit ACK. Tm bits d liu do thit b pht gi v bit ACK do thit b nhn
to ra. V d khi Master thc hin qu trnh gi d liu n Slave, n s pht ra 8
bits d liu, Slave nhn v pht li ACK (ko SDA xung 0 xung th 9), sau
Master s quyt nh gi tip byte d liu khc hay khng. Nu Slave pht tn hiu
NOT ACK (khng tc ng SDA xung th 9) sau khi nhn d liu th Master s
kt thc qu trnh gi bng cch pht i STOP condition. Hnh bn di m t nh
dng gi d liu trong TWI (I2C).
Phi hp gi a ch v d liu: mt qu trnh truyn/nhn TWI (I2C) thng

c bt u t Master, Master pht i mt START condition sau gi gi a
ch SLA+R/W trn ng truyn. Tip theo nu c mt Slave p ng li, d liu
c th truyn/nhn lin tip trn ng truyn (1 hoc nhiu byte lin tip). Khung
truyn thng thng c m t nh hnh bn di.
Multi-Master Bus ng truyn a chip ch: nh trnh by trn, TWI

(I2C) l chun truyn thng a chip ch, ngha l ti mt thi im c th c nhiu
hn 1 chip lm Master nu cc chip ny pht ra START condition cng lc. Nu
cc Master c cng yu cu v thao tc i vi Slave th chng c th cng tn
ti v qu trnh truyn/nhn c th thnh cng. Tuy nhin, trong a s trng hp
s c mt s Master b tht lc (lost). Mt Master b lost khi n truyn/nhn 1
mc cao trn SDA trong khi cc Master khc truyn/nhn 1 mc thp. Truyn
thng a chip ch tng i phc tp v v th ti s khng cp trng hp ny
trong lc thc hin v d giao tip trong bi hc ny.
Nm c cc khi nim v c im trn ca truyn thng TWI (I2C) l bn
sn sng iu khin module TWI trn AVR. Phn tip theo ti s hng dn
cch thao tc module TWI trn AVR thng qua mt v d c th.
III. TWI trn AVR.
1. Thanh ghi:
TWI trn AVR c vn hnh bi 5 thanh ghi bao gm thanh ghi tc gi
nhp TWBR, thanh ghi iu khin TWCR , thanh ghi trng thi TWSR, thanh ghi
a ch TWAR v thanh ghi d liu TWDR.
- TWBR (TWI Bit Rate Register): l 1 thanh ghi 8 bit quy nh tc pht
xung gi nhp trn ng SCL ca chip Master.
Tc pht xung gi nhp c tnh theo cng thc:
Trong CPU Clock frequency l tn s hot ng chnh ca AVR, TWBR l

gi tr thanh thi TWBR v TWPS l gi tr ca 2 bits TWPS1 v TWPS0 nm trong
thanh thi trng thi TWSR. Hai bits ny c gi l bit prescaler, thng thng
ngi ta hay set TWPS1:0 =00 chn Prescaler l 1 (40=1). Bng 1 tm tt tc
xung gi nhp to ra trn SCL i vi cc gi tr ca tham s:
Bng 1. Tc xung gi nhp tham kho.
- TWCR (TWI Control Register): l thanh ghi 8 bit iu khin hot ng ca

TWI.
Bit 7- TWINT (TWI Interrupt Flag): l mt c bo rt quan trng. TWINT

c t ng set ln 1 khi TWI kt thc mt qu trnh bt k no (nh
pht/nhn START, pht nhn a ch). Ch l bit ny khng t ng c xa
bi phn cng nh cc c bo trong cc module khc. V th, khi lp trnh iu
khin TWI chng ta lun phi xa TWINT trc khi mun thc hin mt qu trnh
no . Mt im quan trng cn lu l bit TWINT c xa khi chng ta vit
gi tr 1 vo n. Trong khi lp trnh cho TWI, chng ta thng xa TWINT bng
cch vit 1 vo n, sau lin tc kim tra TWINT, nu bit ny c set ln 1 th

qu trnh hon thnh.
Bit 6 TWEA (TWI Enable Acknowledge Bit): tm hiu l bit kch hot tn
hiu xc nhn. i vi chip Slave, nu bit ny c set th tn hiu xc ACK s
c gi trong cc trng hp sau: a ch do Master pht ra trng khp vi a
ch ca Slave; mt cuc gi chung ang xy ra v Slave ny cho php cuc gi
chung; d liu c Slave nhn t Master. Nh th, khi set mt chip ch
Slave, chng ta cn set bit ny n c th p ng li Master bt c khi no c
gi. i vi chip Master, tn hiu ACK ch c pht trong 1 trng hp duy nht
l khi Master nhn d liu t Slave, Master pht ACK bo cho Slave l mnh
nhn c v mun tip tc nhn t Slave.
Bit 5 TWSTA (TWI START Condition Bit): l bit to START condition.

Khi mt chip mun tr thnh Master thc hin 1 cuc gi, bit ny cn c set
v mt START condition c to ra trn ng truyn nu ng truyn ang
rnh. Nu ng truyn khng rnh, TWI s ch cho n khi n rnh (nhn ra 1
STOP condition) v tip tc gi START condition. Ch l l bit nay cn c xa
bi phn mm sau khi START condition c gi (vit 0 vo bit ny xa n).
Bit 4 TWSTO (TWI STOP Condition Bit): l bit to STOP condition cho
TWI. Khi Master mun kt thc mt cuc gi, n s pht STOP condition bng
cch vit gi tr 1 vo bit TWSTO. Slave cng c th tc ng vo bit ny, nu mt
cuc gi b li, vit 1 vo TWSTO trn Slave s reset ng truyn v trng thi
rnh ban u.
Bit 3 TWWC (TWI Write Collision Flag): khi c TWINT ang mc thp
tc TWI ang bn, nu chng ta vit d liu vo thanh ghi d liu (TWDR) th mt
li xy ra, khi bit TWWC t ng c set ln 1. V th, trong qu trnh truyn
d liu, bit TWINT cn c gi mc cao khi ghi d liu vo thanh ghi TWDR v
sau xa khi d liu sn sng.
Bit 2 TWEN (TWI Enable Bit): bit kch hot TWI trn AVR, khi TWEN
c set ln 1, TWI sn sng hot ng.
Bit 1 Reserve: khng s dng.

Bit 0 TWIE (TWI Interrupt Enable Bit): bit cho php ngt TWI, khi bit nay
c set bng 1 ng thi bit I trong thanh ghi trng thi chung c set, mt ngt
TWI xy ra khi bit TWINT c set bi phn cng. Ngt TWI c th xy ra sau
bt k hot ng no lin quan n TWI. Do cn s dng ngt hp l. Thng

thng, ngt ch c s dng cho Slave, i vi Master ngt khng cn thit v
Master ch ng khi ng mt cuc gi.
Mt iu cn ch l cc bit trong thanh ghi TWCR khng cn c set cng
lc, ty vo tng giai on trong qu trnh giao tip TWI cc bit c th c set
ring l.
- TWSR (TWI Status Register): l 1 thanh ghi 8 bit trong c 5 bit cha
code trng thi ca TWI v 2 bit chn prescaler.
C rt nhiu bc, nhiu tnh hung xy ra khi giao tip bng TWI cho c
Master v Slave. ng vi mi trng hp TWI s to ra 1 code trong thanh ghi
TWSR . Lp trnh cho TWI cn xt code trong 5 bit cao ca thanh ghi TWSR v
a ra cc ng x hp l ng vi tng code.
- TWDR (TWI Data Register): l thanh ghi d liu chnh ca TWI. Trong
qu trnh nhn, d liu nhn v s c lu trong TWDR. Trong qu trnh gi, d
liu cha trong TWDR s c chuyn ra ng SDA.
- TWAR (TWI Address Register): l thanh ghi cha device address ca chip
Slave. Cu trc thanh ghi c trnh by trong hnh di.
Nh li a ch Slave c to thnh t 7 bits, trn thanh ghi TWAR 7 bits a

ch ny nm 7 v tr cao. Trc khi s dng TWI nh Slave, chng ta phi gn
a ch cho chip, vic vit a ch thng c thc hin bng lnh TWAR =
(Device_address<<1)+TWGCE. Trong TWGCE (TWI General Call Enable) l
bit cho php cuc gi chung. Nh ti cp bn trn, Slave co quyn cho php
Master thc hin cuc gi chung vi n hay khng. Nu TWGCE=1, Slave s p
ng li cuc gi chung nu c, nu TWGCE=0 th Slave s b qua cuc gi
chung.
2. Hot ng ca TWI:
TWI trn AVR c gi l byte-oriented (tm dch l hng byte) v
interrupt-based (da trn ngt). Bt k mt s kin no trong qu trnh truyn/nhn
TWI cng c th gy ra 1 ngt TWI. TWI trn AVR v th hot ng tng i c

lp vi chip. Tuy nhin, cn khai thc ngt trn AVR mt cch hp l. V d, i
vi Master, chng ta khng cn s dng ngt v chip ny hon ton ch ng trong
vic truyn v nhn. Ring vi Slave, s dng ngt trnh b l cc cuc gi l
cn thit.
Tt c cc AVR trn mng TWI u c th l Master hay Slave, c Master v Slave
u c th truyn v nhn d liu. V th, c tt c 4 mode trong hot ng ca
TWI trn AVR. Chng ta s ln lt kho st cc mode ny nh sau: Master
Transmitter (chip ch truyn), Master Receiver (Chip ch nhn), Slave Reicever
(chip t nhn) v Slave Transmitter (Chip t truyn).
Trc khi kho st cc ch hot ng ca TWI chng ta qui c mt s k hiu
thng dng (y cng l cc k hiu dng trong datasheet ca cc chip AVR).
S:
Rs:
R:
W:
ACK:
th 9
NACK:
Data:
P:
SLA:
START condition iu kin bt u

REPEAT START bt u lp li
READ Bit, bit ny bng 1 c gi km vi gi a ch
WRITE Bit, bit ny mang gi tr 0, gi km gi a ch
Ackowledge, bit xc nhn, chn SDA c ko xung 0 xung
Not Acknowledge, khng xc nhn, SDA mc cao bit th 9
8 bits d liu
STOP condition iu kin kt thc.
Slave address, a ch ca Slave cn giao tip.
A. Master Transmitter mode Master truyn d liu:

Trong ch ny, Master truyn 1 hoc mt s byte d liu n mt hoc cc
Slave. bt u, Master to ra mt START condition trn ng SDA, nu
ng truyn ang rnh, Master s tip tc pht i a ch ca Slave cn giao tip
cng vi bit W (ghi) theo nh dng nh sau: SLA+W. Nu Slave p li bng mt
ACK trong xung gi nhp th 9, Master s tip tc gi 1 hoc lin tip cc byte d
liu trn SDA. C sau mi byte d liu, Master s kim tra ACK t Slave. Nu
Slave gi mt NACK hoc Master khng mun gi thm d liu n Slave n s
pht i mt STOP condition hoc mt REPEAT START (Rs). Nu STOP c
pht, cuc gi kt thc, nu Rs c pht, mt cuc gi mi bt u, sau Rs l a
ch ca Slave mi l v mt l thuyt, trn thc t lm sao kim tra mt
START condition c c gi cha? lm sao bit c nhn c ACK sau khi pht
a ch hoc d liu? Tt c c TWI m ha thnh cc code cha trong thanh ghi
TWSR (ch 5 bit cao). Chng ta ch thanh ghi ny v i chiu vi bng code quy
nh sn bit trng thi ng truyn v a ra quyt nh tip theo. Hnh 2 m
t mt qu trnh Master truyn d liu, cc kh nng c th xy ra v gi tr tng
ng ca thanh ghi TWSR. ngha cc code trong thanh ghi TWSR trong lc
Master truyn d liu c th tham kho thm datasheet ca chip.
Hnh 2. Master truyn d liu.

T hnh 2, chng ta nhn thy khi Master truyn d liu, dy code 0x08 ->
0x18 -> 0x28 -> -> 0x28 (-> 0x30) l dy code thnh cng nht. Code 0x08 bo
rng START codition c truyn thnh cng, code 0x18 bo a ch truyn thnh
cng v c Slave xc nhn bng ACK, code 0x28 tc d liu c Master
truyn thnh cng v Slave nhn c, bo ACK li cho Master, code 0x30 tc
d liu c truyn nhng Slave khng xc nhn li, lc ny Master c th pht
i mt STOP codition sau code 0x30. Ngoi ra cn mt s code khc tng ng
vi cc trng hp khc nh gi a ch tht bi (code 0x20), Master b lost (code
0x38)i vi mi loi ng dng, cch hnh x s khc nhau i vi cc
trng hp tht bi ny. Trong bi ny, ti s b qua tt c cc trng hp tht bi,
nu mt trong cc code tht bi xy ra chng ta s thot khi cuc gi v a
ng truyn v trng thi ngh.
B. Master Receiver mode Master nhn d liu:
Trong ch ny, Master nhn mt hoc mt s byte d liu t mt Slave.
bt u, Master to ra mt START condition trn ng SDA, nu ng truyn
ang rnh, Master s tip tc pht i a ch ca Slave cn giao tip cng vi bit R
(c) theo nh dng nh sau: SLA+R. Nu Slave p li bng mt ACK trong
xung gi nhp th 9, Master s bt u sample d liu trn SDA. C sau mi byte
d liu, nu Master mun nhn tip byte khc n phi pht ra 1 ACK xung th 9
bo cho Slave. Khi Master mun kt thc qu trnh nhn n s pht mt NOT ACK
sau khi nhn d liu, lin sau Master pht STOP kt thc cuc gi hoc pht
i mt REPEAT START nu n mun tip tc gi cc Slaves khc. Hnh 3 m t
mt qu trnh Master nhn d liu, cc kh nng c th xy ra v gi tr code tng
ng ca thanh ghi TWSR. ngha cc code trong thanh ghi TWSR trong lc
Master truyn d liu c th tham kho thm datasheet ca chip.
Hnh 3. Master nhn d liu.

T hnh 3, trong qu trnh Master nhn d liu, dy code 0x08 -> 0x40 ->
0x50 -> -> 0x58 l dy code thnh cng nht. Code 0x08 bo rng START
codition c truyn thnh cng, code 0x40 bo a ch + R c truyn thnh
cng v c Slave xc nhn bng ACK, code 0x50 bo d liu c Master nhn
thnh cng v Master cng pht mt ACK bit sau khi nhn, code 0x58 xy ra
khi Master nhn d liu thnh cng nhng n khng pht ACK m pht NOT
ACK, bo cho Slave rng Master khng mun nhn thm d liu, tip theo Master
s pht mt STOP condition hoc mt REPEAT START. Cc trng hp khc

chng ta khng kho st.
C. Slave Receiver mode Slave nhn d liu:
Hnh 4 m t mt qu trnh Slave nhn d liu, cc kh nng c th xy ra v
gi tr code tng ng ca thanh ghi TWSR. Ch Slave nhn d liu xy ra khi
Master thc hin mt cuc gi pht d liu (SLA+W). Nh quan st trong hnh 4,
Slave ch nhn ra cuc gi ny khi a ch ca n trng vi a ch ca Master
(Own address mode) hoc khi Master thc hin mt cuc gi chung. Khi , bit
TWINT ca Slave s c set ln 1. Nu Slave cho php ngt TWI (bit TWIE
trong thanh ghi TWCR c set t lc u) th mt ngt xy ra bo c mt s kin
TWI. Nu code trong thanh ghi TWSR l 0x60 th mt cuc gi a ch ring c
yu cu v Slave cng p ng li Master bng mt ACK, Slave sau bt u
nhn d liu t ng SDA. C sau mt byte d liu Slave phi xc nhn mt
ACK nu n cn mun tip tc nhn. Nu v mt l do no m Slave khng th
tip tc nhn n c th pht mt NOT ACK sau mt byte d liu. Cuc gi kt
thc khi Slave nhn c STOP condition, tng ng code 0xA0. Cuc gi chung
cng din ra hon ton tng t cuc gi a ch ring nhng code c gi tr khc.
Khi vit chng trnh cho Slave trong ch nhn d liu, chng ta cn xt c 2
trng hp cuc gi a ch ring v cuc gi chung.
Hnh 4. Slave nhn d liu.

D. Slave Transmitter mode Slave truyn d liu:
y l ch cui cng trong 4 ch ca AVR TWI. Hnh 5 m t mt qu
trnh Slave truyn d liu, cc kh nng c th xy ra v gi tr code tng ng ca
thanh ghi TWSR. Ch Slave pht d liu xy ra khi Master mun nhn d liu
t Slave, Master thc hin mt cuc gi nhn d liu (SLA+R). Nh quan st

trong hnh 5, Slave ch nhn ra cuc gi ny khi a ch ca n trng vi a ch
ca Master (Own address mode). Khi , bit TWINT ca Slave s c set ln 1.
Nu Slave p li bng mt ACK xung nhp th 9, code trong thanh ghi TWSR
s l 0xA8, Slave sau bt u pht d liu ln ng SDA. C sau mi byte d
liu, Master s xc nhn mt ACK nu n cn mun tip tc nhn, code 0xB8 s
xut hin trong trng hp ny. Nu Master khng mun tip tc nhn d liu t
Slave, mt NOT ACK s c pht v code 0xC0 xut hin, Slave kt thc qu
trnh pht d liu. Mt trng hp c bit khi bit TWEA (bit ACK) trong thanh
ghi TWCR ca Slave c reset v 0 trc khi Slave truyn d liu, trng hp
Slave mun bo rng n ht d liu truyn, byte tip theo cng l byte cui
cng. Sau khi Master nhn byte ny, n c th xc nhn 1 ACK cho Slave (v tht
ra Master khng h bit Slave ang truyn byte cui), code trn Slave trong trng
hp ny l 0xC8 v Slave s t ht thc qu trnh truyn m khng cn ch Master.
Khi lp trnh cho Slave trong ch pht, cn phi c s tha hip vi Master
trc trnh code 0xC8 v code ny khng c nhiu ngha.
Hnh 5. Slave truyn d liu.
K thut chnh dng cho Master khi truyn hay nhn cuc gi l hi vng v
ch (polling and waiting). ng vi mi code nhn v t thanh ghi TWSR (hay ng
vi mi trng thi ca cuc gi) m Master set cc bit tng ng trong thanh ghi
iu khin TWCR v sau ch bit TWINT c set (qu trnh kt thc) tip
tc c v xt code TWSR. Qu trnh ch v xt ny lp li cho n khi Master kt
thc cuc gi bng STOP condition. Tuy nhin Slave th khc, Slave khng ch
ng thc hin cuc gi m n phi ch yu cu t Master phc v. V th, nu
dng hi vng cho Slave th s tn thi gian ch v ch v i khi cn b l cc
cuc gi. i vi Slave, ngt l phng php bt cuc gi ti u nht. Trong bi
hc ny, vic truyn v nhn ca Slave s c thc hin trong cc trnh phc v
ngt TWI.
IV. iu khin AVR TWI.

Phn ny ti hng dn lp trnh iu khin module TWI AVR bng
WinAVR. Cc hnh 2, 3, 4 v 5 cn c tham kho km k v code trong phn ny
c pht trin t cc hnh ny. n gin, chng ta s vit cc hm giao tip
TWI trong 1 file ring gi l myTWI.h, y c th coi l th vin cho TWI dng
trong trang web ny. Nh trnh by, chun I2C th duy nht nhng cch sp xp
d liu ca cc chip I2C th rt a dng. V th, khi mun giao tip vi mt chip
I2C no bn nht thit phi c datasheet ca chip hiu nh dng d liu.
Cc hm trong th vin myTWI ch phc v giao tip gia cc AVR vi nhau, nu
mun s dng chng giao chip vi mt chip EEPROM 24C1004 chng hn, bn
phi vit thm cc hm m rng khc da trn cc hm ny.
Ni dung file myTWI.h c chia thnh 3 phn, phn u l cc nh ngha bin,
tham s chung, phn 2 gm cc hm truyn/nhn cho Master v phn 3 l trnh
phc v ngt TWI cho Slave. List 1 trnh by cc nh ngha chung trong file
myTWI.h.
List 1. nh ngha chung.
Phn ny ch yu nh ngha cc code trng thi trong qu trnh thao tc TWI

trn AVR m chng ta bit khi kho st cc ch hot ng ca TWI. Tht ra
bn c th tham kho cc hnh 2-5 v cc bng code trong datasheet ca AVR v s
dng cc code trng thi trc tip trong lc lp trnh, ti nh ngha nh trn ch
tin theo di trong lc lp trnh. Cc dng t 12 n 25 nh ngha cc code trng
thi cho Slave (c truyn v nhn). Chng ta cng nh ngha mt s bin ton cc
dng cho Slave, bin SLAVE_wData[100] l mt mng 100 phn t dng cha d
liu m Slave s truyn, bin Tran_Num l ch s ca phn t trong mng
SLAVE_wData s c truyn i. Bin SLAVE_buff[100] l d liu nhn v t
TWI v Rec_Num l ch s ca d liu sau cng do TWI nhn v (d liu
SLAVE_buff[Rec_Num]). Bin Device_Addr cha a ch m khi l Slave ca
chnh AVR chng ta ang lp trnh. Tng t, cc dng t 47 n 57 nh ngha
code trng thi cho Master mode. Trc , chng ta cng nh ngha cc gi tr
tc pht xung gi nhp s gn cho thanh ghi TWBR (dng 37, 38). Hai bin
TWI_R v TWI_W i din cho 2 bit R/W c truyn trong gi a ch (bo cho
Slave bit Master mun truyn hay nhn d liu). Mt s macro trong cc dng 42
n 45 bao gm START, STOP condition v xa bit TWINT bng cch gn cc gi
tr tng ng cho thanh ghi iu khin TWI.
Cui cng l chng trnh con void TWI_Init(void) khi ng TWI. Qu trnh
khi ng bao gm set tc xung gi nhp cho Master (dng 61, 62), gn a ch
device (dng 63) v xc lp TWI sn sng ch Slave. Xem li thanh ghi
TWAR, do 7 bit a ch nm v tr cao nn chng ta cn phi dch tri a ch 1 v
tr trc khi gn cho TWAR (Device_Addr <<1), ng thi set bit 0 trong TWAR
cho php nhn cuc gi chung khi c yu cu. Dng 64 khi ng TWI vi
bit ACK sn sng v cho php xy ra ngt TWI. Nh th, sau khi khi ng TWI
sn sng ch Slave.
List 2. Code cho Master.
Hm TWI_Master_Send_array(uint8_t Addr, uint8_t Data[], uint8_t len) thc

hin truyn 1 dy cc byte d liu trong mode Master. Tham s Addr l a ch ca
Slave cn giao tip, Data[] l mng d liu v len l chiu di (s byte) ca d liu
cn truyn. Vic u tin khi chng ta vo Master mode l tt ngt TWI bng
cch xa bit TWIE (dng 3). Trnh t Master truyn d liu hon ton tng t
trnh t trong hnh 2. Dng 5, TWCR=TWI_START, Master bt u pht 1 START
condition. Nu xem li nh ngha ca macro TWI_START trong list 1 bn s thy
dng TWCR=TWI_START tng ng TWCR=(1<<TWINT)|(1<<TWSTA)|
(1<<TWEN) tc chng ta thc hin xa bit TWINT (bit ny phi lun c xa
trc khi mun thc hin vic g) bng cch ghi 1 vo TWINT, set bit START (bit
TWSTA) v cho php TWI hot ng bng bit TWEN. Dng code 6 ch cho n
khi bit TWINT c phn cng set ln 1 (kt thc), sau chng ta kim tra code
trong thanh ghi trng thi TWSR. Ch l ch c 5 bit cao trong thanh ghi TWSR
cha trng thi nn chng ta cn dng gii thut mt n che cc bit thp li, TWSR
& 0xF8 chnh l cch che 3 bit thp ca TWSR. So snh code c c vi
code tng ng trong hnh 1, trong trng hp ny chng ta so snh vi
_START_Sent, chnh l so snh vi 0x80 (xem li nh ngha ca _START_Sent
trong list 1). Nu cc code khng trng nhau, mt li truyn xy ra v chng ta s
thot khi chng trnh truyn, gi tr tr v chnh l code c li (xem dng code
7). Cc dng code t 10 n 13 thc hin truyn a ch + W, ch trong lc pht,
d liu cn pht phi c ghi sn vao thanh ghi d liu TWDR trc khi xa bit
TWINT (dng 10 v 11). Sau khi truyn a ch chng ta truyn mng d liu lin
tip v cui cng l pht STOP condition, TWCR=TWI_STOP tng ng
TWCR=(1<<TWINT)|(1<<TWSTO)|(1<<TWEN). Cn khi ng li TWI a
n v ch Slave trc khi thot khi chng trnh con truyn d liu ca ch
Master (dng 24).
Hm TWI_Master_Read_array(uint8_t Addr, uint8_t Data[], uint8_t len) thc
hin nhn d liu v Master. Cch gii thch cho hm ny khng khc nhiu so vi
hm c d liu nn bn c t tm hiu. Mt im cn ch l khi nhn 1 dy
byte chng ta nn c n-1 byte u bnh thng, c tr ACK cho Slave v byte
cui cng s c nhn ring, tr NOT ACK bo cho Slave rng Master khng
mun nhn thm(on code t dng 55 n 59 dng c byte cui cng).
List 3. Code cho Slave.
Nh ti trnh by, ton b qu trnh truyn v nhn ca Slave c thc

hin trong chng trnh phc v ngt TWI. Khi ngt TWI xy ra, trnh phc v
ngt s c v kim tra code trong thanh ghi TWSR thc hin cc cng vic ph
hp. Bn c li tham kho thm hnh 4 v hnh 5 cng vi cc code trong nhng
case tng ng ca List 3 hiu on chng trnh ny. im lu ln nht
m ti mun ni l cc bin c dng cho ch Slave truyn v nhn. Ti dng
2 mng SLAVE_wData v SLAVE_buff cha bin truyn v nhn. Hai bin
Tran_Num v Rec_Num l ch s ca byte hin hnh. V th
SLAVE_wData[Tran_Num] chnh l byte tip theo s c truyn i nu Slave
c yu cu truyn, v SLAVE_buff[Rec_Num] l byte cui cng m Slave nhn
v trong ch Slave nhn d liu. Hy khi thc cc bin ny trong cc chng
trnh ng dng.
minh ha cho cc s dng cc hm trong th vin myTWI, ti thc hin
mt mch in m phng mng TWI gm 3 chip ATmega32. Chip th nht l
Master, 2 chip cn li l Slaves. Ti to 2 Project, mt cho Master v mt cho 2
Slaves dng chung. PORTD c set input c in tr ko ln. Ti dng 2 chn
PD6 v PD7 chn a ch cho 2 Slaves, Slave th nht ti ni chn PD6 xung
GND, do chip ny c a ch Device_Addr l PD7:PD6=10=2 (thp phn).
Slave cn li ti 2 chn PD6 v PD7 trng nn a ch ca n l
PD7:PD6=11=3. Trong chng trnh ca Slave c phn c 2 chn PD6:PD7 v
gn cho bin Device_Addr m chng ta khai bo trong List 1, nh vy c th
dng cc ny set a ch cho Slaves m chng ta gi l set a ch cng. Trn
chip Master, mt swich c ni vi chn PD0 chn Slave cn giao tip, nu
switch ng th SLAVE c a ch 2 c chn, nu switch m th SLAVE c a
ch 3 c chn giao tip. Mt nt nhn c ni vi ngt INT0 ca chip
Master, khi nhn nt ny chng trnh cn c d liu t Slave c gi, ty theo
switch ng hay m m Slave tng ng c gi gi d liu cho Master. D
liu nhn v s hin th trn 1 Character LCD. Hnh 6 l s mch in m
phng bng phn mm Proteus v List 4, List 5 ln lt trnh by on code cho
chng trnh chnh ca Master v Slave.
Hnh 6. Demo TWI.

List 4. Chng trnh chnh cho Master.
V d ca Master minh ha cch dng 2 hm Master truyn v nhn mng d

liu. dng 27 ti dng hm TWI_Master_Send_array gi 40 phn t ca
mng Data n Slave c a ch 2, TWI_Master_Send_array(2,Data,40). Tng t,
dng 31 gi 50 phn t ca mng Data n Slave c a ch 3. Khi button trn
mch m phng c nhn, ngt INT0 xy ra, trong trnh phc v ngt INT0
chng ta dng hm TWI_Master_Read_array c d liu t mt trong 2 Slaves,
xem dng code 43: TWI_Master_Read_array(Slave_Addr,rData,1). a ch ca
Slave cn c s do switch ni vi chn PD0 quyt nh (xem dng 42). a ch
ca Slave ang giao tip s hin th trn dng 1 ca LCD, d liu c hin th
trn dng 2.
List 5. Chng trnh chnh cho Slaves.
Chng trnh demo ca Slaves minh ha cc ch Slave truyn v nhn d

liu. Tuy nhin do cc qu trnh truyn v nhn d liu ca Slave c thc hin
trong trnh phc v ngt TWI c vit sn trong file myTWI.h. trong chng
trnh chnh ca Slave chng ta khng cn phi gi bt k hm no trong myTWI.
Cng vic cn lm trong chng trnh demo cho Slave l khi ng TWI sau
gn gi tr cho cc bin ton cc ca Slave (dng 21 gn gi tr cho mng
SLAVE_wData).
Ti c nh km v d demo cho TWI, ti thc hin 2 Projetc trong 2 th mc:
TWI1 cho AMster v TWI2 cho Slave. chy demo, chy file TWI bng Proteus,
dng switch SW1 chn Slave cn giao tip, nhn button nhn d liu t
Slave. Thay i v tr switch v kim tra kt qu.
Ma trn LED
5
( 101 Votes )
Ni dung

Cu trc AVR.
1.
Ma trn LED.
WinAVR.
2.
AVR v ma trn LED.
C cho AVR.
Download v d
I. Ma trn LED.
M phng vi Proteus.
Ma trn LED tc Dot Matrix LED l tp hp nhiu n LED c b tr thnh

dng ma trn hnh ch nht hoc vung vi s hng l a v s ct l b. Ma trn
LED c dng rt nhiu trong cc ng dng hin th nh cc bin qung co, hin
th thay th LCD hoc thm ch dng hin th video gim s lng cc ng
iu khin, trong cc ma trn LED cc LED c ni chung vi nhau theo hng v
ct. S lng LED trn ma trn LED l axb trong khi s lng ng ra bng tng s
hng v ct: a + b. Vic iu khin 1 ma trn LED kch thc ln i hi thit k
mt mch driver v iu khin rt phc tp. Vi mc ch gip bn c lm quen
khi nim ma trn LED, trong phm vi bi ny ti ch trnh by thao tc vi 1 ma
trn LED c kch thc 7x5 (7 hng, 5 ct). ma trn LED 7x5 thng c dng
hin th cc k t trong bng m ASCII thay cho Text LCD. Tuy nhin, bn c
th ghp cc ma trn LED ny li hin th cc loi hnh nh bt k c phn
gii thp. Hnh 1 m t mt cu trc ca mt ma trn LCD 7x5 vi 12 ng ra c
t tn t C0C4 v D0D6 (C i din cho Control line v D l Data line).
Hnh 1. Ma trn LED 7x5.

Bn trong cc ca ma trn LED l cc LED pht sang. Trong m hnh trn,
Cathod (cc m) ca cc LED trn mi hng c ni chung vi nhau v ng ra
chung l cc ng D (Data). Cc Anod ca cc LED trn mi ct c ni chung
to thnh cc ng C (Control). Thng thng, cc ng D v C c chn sao
s s lng ng D nhiu hn ng C hoc sao cho s lng cc ng D gn

nht vi s 8, 16, 32(ly tha ca 2). L do ca vic chn ny nhm gim kch
thc b font cha cc k t hoc hnh nh hin th ln ma trn LED, bn s hiu
r hn khi tm hiu cc iu khin ma trn LED 7x5 bn di.
a)
b)
Hnh 2 m t cch m ma trn LED 7x5 c dng hin th s 4.

Trc ht chng ta s kho cch cho sang cc LED m khng cn quan tm
n bng font. Quan st ct th nht (ct C0) trong hnh 2a, trong ct ny ch c 2
LED hng D2 v D3 l sang, cc LED cn li tt. iu ny c thc hin bng
cch kch chn C0 (Anod) ln mc cao, ko cc chn D2, D3 xung mc 0 trong
khi cc chn Data khc c gi mc cao. Cc ct khc c thc hin tng t.
Tuy nhin, cu hi y l lm sao hin th cc ct vi cc n LED sng khc
nhau trong khi cc ng Cathod ca chng u c ni chung (thnh cc chn D).
V d mt ngi ko tt c 5 chn C0C4 ln mc cao vo xut tn hiu ra cc
chn D, khi tt c cc LED trn dng mt hng s sng hoc tt nh nhau. B
quyt y chnh l k thut qut, chng ta s hin th tun t cc ct vi cc
gi tr tng ng ca chng ch khng hin th ng thi. Trong v d hin th s
4, trc ht hy kch chn C0 ln cao trong khi cc chn C1C4 mc thp,
xut tn hiu ra cc chn D hin th ln ct C0. Tip theo ko chn C1 ln cao v

cc chn Control khc mc thp, xut d liu ra cc chn D hin th ct C1
C nh th cho n khi hin th ht cc ct th quay li ct C0. Qu trnh ny gi l
qut LED. Do tc qut rt cao nn chng ta s khng c cm gic nhp
nhy, cc ct ca ma trn nh c hin th ng thi. Ch l sng ca LED
ph thuc vo s ct LED, nu bn qut qu nhiu ct LED, t l thi gian ON
ca mi ct s rt nh so vi thi gian OFF v phi ch qut cc ct khc. V th
nu ma trn LED c nhiu ct hoc khi ghp nhiu ma trn, cc mch driver cn
c s dng m bo sng ca LED.
Gi s mi LED i din cho 1 bit v cc LED sng i din cho gi tr nh
phn 1 trong khi cc LED tt l s 0. Hnh 2b th hin m hnh s nh phn cho
trng hp hin th s 4 trn ma trn LED 7x5. Nu xem mi ct ca ma trn l 1
con s 7 bit th 5 gi tr cn thit hin th s 4 l: 0x0C, 0x14, 0x24, 0x7F,
0x04. B 5 gi tr ny to thnh m font cho k t 4, chng s c nh ngha
trc v lu trong b nh ca chip iu khin (AVR), mi ln mt k t c yu
cu hin th, b font tng ng ca k t s c load ra v xut ln lt trn
cc ng Data, y chnh l l do ti sao chng ta gi cc ng D l cc ng
Data. Cch qut LED ti va trnh by l cch qut ngang, bn c th thc
hin qut dc nu ng dng yu cu. Trong phng php qut dc, cc chn
hng chung s c dng chn hng cn hin th, d liu s xut ra theo tng
hng trn 5 ct v ln lt thay i hng (hng 0 trc, n 1v cui cng l 6).
So snh 2 cch qut cho trng hp ma trn LED 7x5, r rng trong cch qut
ngang chng ta ch cn quet 5 ct cho mi ln LED nn t l thi gian ON s cao
hn (1/5 so vi 1/8 ca cch qut dc). Mt khc, nu thc hin qut dc chng ta
cn 8 s s to thnh 1 b font cho mt k t v v th tn nhiu b nh hn
cho vic lu tr bng font. Trong bi hc ny ti thc hin theo cch qut ngang v
bng font cng c xy dng cho cch qut ny.
II. AVR v Ma trn LED.
Phn ny ti minh ha cch hin th ma trn LED 7x5 bng AVR. Chng ta s
thc hin trn duy nht mt ma trn LED, cho cc ng dng cn nhiu LED bn
c hy t pht trin t tng trong phn ny. Hy v mt mch in m phng
bng phn mm Proteus nh trong hnh 3.
Hnh 3. Hin th ma trn LED bng AVR.
Cc chn C ca ma trn c ni vi cc chn trn PORTC ca chip AVR

ATmega32, v cc chn D c ni vi PORTD. Hy to 1 Project bng
Programmer Notepad tn DotMatrix v to 2 file tn font.h cng dotmatrix.c
trong Project ny. File font.h cha bng font ca cc k t v file dotmatrix.c l
file chnh cho chng trnh demo. List 1 trnh l mt phn ni dung ca file
font.h v List 2 l ni dung file dotmatrix.c.
List 1. Bng font.
List 2. Chng trnh demo.
iu cn quan tm u tin l kch thc bng font, trong v d ny bng

font c xy dng cho 223 symbol c m ASCII t 32 n 255 (do cc m
ASCII trc 32 khng c symbol tng ng nn c th b qua tit kim b
nh), mi symbol cn 5 s 8 bits, nh th chng ta cn tng cng 1115 byte cho
bng font trong khi kch thc SRAM ca chip ATmega32 ch l 2KB (2048
byte). Nu dng SRAM cha bng font s rt ph phm v y l 1 bng tnh,
gi tr trong bng hon ton khng thay i m ch c truy xut c. V th
chng ta c th tn dng b nh chng trnh (Flash) lu bng font ny.
Dng u tin trong List 1 chng ta include header pgmspace.h s dng
cc thao tc trn b nh chng trnh. Tip theo chng ta khai bo 1 mng tnh
c tn font7x5 vi kiu d liu l prog_char tc l kiu char nhng cha trong
b nh chng trnh (Program memory). Gi tr cha trong mng font7x5 chnh
l d liu ca bng font, thc cht mng font7x5 l mng 1 chiu lin tc, vic
tch ra trn nhiu dng c mc ch gip ngi c d hnh dung khi truy cp
cc gi tr ca mng xut ra sau ny. Bn hy hiu rng c mt t hp 5 s s
to thnh mt symbol hin th cho ma trn LED. D liu trong bng font c
sp xp theo trnh t ASCII v to iu kin thun li khi truy xut bng font
theo m ASCII ca k t cn hin th. Tuy nhin cn ch l bng font c bt
u cho symbol c m ASCII l 32 ch khng bt u t m ASCII 0, v th khi
truy cn bng font t m ASCII chng ta cn ly m ASCII tr i 32 c v
tr chnh xc trong bng.
Tip theo chng ta s tm hiu chng trnh chnh, dng 3 trong list 2
include file font.h s dng bng font trong chng trnh chnh. Cc dng t 5
n 9 nh ngha cc PORT kt ni vi ma trn LED, PORTD l Data bus trong
khi PORTC l control lines. Chng trnh con void DOTputChar75(uint8_t chr)
trong dng 11 l th tc c d liu t bng font v hin th trn ma trn LED.
Tham s chr ca chng trnh ny chnh l m ASCII ca k t cn hin th trn
ma trn LED. Dng 12 khai bo 2 bin ph, trong bin line cha tn hiu
iu khin cho cc ng Control. Dng 13 khai bo mt bin tm tchr dng
cha a ch d liu cn ly ra t bng font xut ra cc ng Data, v m
ASCII l mt s 8 bit trong khi s lng d liu trong bng font ln gp 5 ln s
lng k t, v th cn khai bo bin tchr c kiu d liu 16 bit. Ni dung chnh
ca on chng trnh ny nm trong vng lp for, bin i i din cho s th t
ca cc chn Control c cho chy t 0 n 4, trong dng 15
CTRL_PORT=line; xut tn hiu iu khin ra CTRL_PORT tc ra cc chn
C. Do bin line c khi to bng 1 nn ln lp u tin gi
trCTRL_PORT=0b00000001, tc chn C0 mc cao trong khi cc chn cn
li mc thp, ct u tin c chn. Sau khi 1 ct c chn, dng 16
DATA_PORT=~pgm_read_byte(&font7x5[((tchr - 32) * 5) + i]); c v
xut d liu t bng font ra cc chn Data. Trc ht l cch tnh a ch ca d
liu trong bng font. Nh trnh by trong phn gii thch cho bng font, bng
ny c chng ta bt u t k t c m 32 nn chng ta cn tr i 32 tham
chiu n v tr chnh xc trong bng font: tchr-32. V d mun hin th k t c
m chr = 48 (m ca k t 0), v tr ca t hp d liu to nn s 0 c
cha trong bng font v tr 16, gi tr ny c tnh 48-32=16. Tip theo, do
mi k t c to thnh t 5 s nn a ch thc cht ca s u tin trong t
hp s l (tchr-32)*5. di chuyn trong phm vi 5 d liu ng vi 6 ct ca
ma trn LED, bin i c cng dn vo a ch ny v chng ta c: tchr - 32) *

5) + i. c d d liu dng byte t b nh chng trnh, chng ta cn dng
hm pgm_read_byte, hm ny c nh ngha trong header pgmspace.h c
khai bo trong file font.h.
Nh vy saiu khi thc hin
pgm_read_byte(&font7x5[((tchr - 32) * 5) + i]) chng ta thu c d liu 1
byte tng ng vi ct th i ca k t chr t bng font, vic cui cng c th l
xut gi tr ny ra DATA_PORT. Tuy nhin, trc khi xut byte c c ra
DATA_PORT, chng ta cn o cc bit ca byte ny bng ton t ~, l do
c gii thch l do cc LED trong ma trn trong v v ny c cc hng ni vi
cc m Cathode, mt LED sng th gi tr cn cp cho bit D tng ng l 0
ngha l ngc li so vi cch chng ta to bng font (sng l 1). Ch bng mt
thao tc n gin l ton t ~ chng c th d dng vt qua tr ngi ny.
Trong trng hp ma trn LED c cc hng ni vi cc dng Anode th chng
ta khng cn o gi tr c v. Dng 17 thc hin dch chuyn gi tr ca bin
line sang tri 1 v tr, vic lm c tc dng chun b cho ln k tip chn C k
tip s c kch. Hm delay trong dng 18 gip cc LED trong ct hin ti
sng trong 1 khong thi gian trc khi chuyn qua ct khc.
Chng trnh chnh trong v d ny tht s rt n gin, chng ta trc ht
cn khi ng hng xut nhp cho cc PORT v sau gi hm
DOTputChar75() trong vng lp v tn while(1). v d trn, k t 4 c
xut ra v kt qu hin th nh trong hnh 3. Ch l hm DOTputChar75() ch
qut qua cc ct 1 lt, v th mun hin th mt k t trong mt khong thi
gian chng ta cn gi hm DOTputChar75() lp li trong khong thi gian .
KeyPad
5
( 29 Votes )
Ni dung

Cu trc AVR.
1.
2.
Keypad 4x4.
ckeypad 4x4 bng AVR.
Download v d
WinAVR.
C cho AVR.
M phng vi Proteus.
Text LCD
I. Keypad 4x4.
Keypad l mt "thit b nhp" cha cc nt nhn cho php ngi dng nhp
cc ch s, ch ci hoc k hiu vo b iu khin. Keypad khng cha tt c
bng m ASCII nh keyboard v v th keypad thng c tm thy trong cc
thit b chuyn dng. Cc nt nhn trn cc my tnh in t cm tay l mt v d
v keypad. S lng nt nhn ca mt keypad thay i ph thuc vo yu cu ng
dng. Trong bi ny ti gii thiu cch iu khin ca mt loi keypad n gin,
keypad 4x4.
Gi l keypad 4x4 v keypad ny c 16 nt nhn c b tr dng ma trn 4
hng v 4 ct. Cch b tr ma trn hng v ct l cch chung m cc keypad s
dng. Cng ging nh cc ma trn LED, cc nt nhn cng hng v cng ct c
ni vi nhau, v th vi keypad 4x4 s c tng cng 8 ng ra (4 hng v 4 ct). M
hnh Keypad 4x4 c th hin trong hnh 1.
a)
b)
Hnh 1. Keypad 4x4.
Hnh 1b l m hnh tht ca 1 keypad 4x4 v hnh 1a l cu hnh bn trong

ca n. Bn hng ca keypad c nh du l A, B, C v D trong khi 4 ct
c gi l 1, 2, 3 v 4.
Hot ng ca keypad: Gi s nht '2' c nhn, khi ng C v 2
c ni vi nhau. Gi s ng 2 c ni vi GND (mass, 0V) th C cng s
l GND. Tuy nhin, cu hi t ra l bng cch kim tra trng thi ng C
chng ta s c kt lun nt '2' c nhn? Gi s tt c cc ng 1, 2, 3, 4 u
ni vi GND, nu C= GND th r rng chng ta khng th kt lun nt '1',= hay
nt '2' hay nt '3' hay nt '-' c nhn. K thut khc phc vn ny chnh
l k thut "qut" keypad. K thut qut keypad bng AVR c trnh by nh
sau:
- Ni tt c 8 chn ca keypad vi 1 PORT ca AVR, v d PORTB theo th t
bn di:
- Cc chn 1, 2, 3, 4 c set nh cc chn Output v gi mc cao, cc

chn A, B, C, D l Input v c in tr ko ln. Ln lt ko chn 1, 2, 3, 4
xung thp (ln lt xut gi tr 0 ra tng chn), c trng thi cc chn A, B, C,
D kt lun nt no c nhn. V d nh trong hnh 1, nt '2' c nhn th
qu trnh qut s cho kt qu nh sau:
Bc 1: ko chn 1 xung 0 (cc chn 2,3,4 vn mc cao), kim tra 4

chn A, B, C, D thu c kt qu D=1, C=1, B=1, A=1. (gi tr c v ca
PINB l 00001111 nh phn)
Bc 2: ko chn 2 xung 0, kim tra li A, B, C, D, kt qu thu c

D=1, C=0, B=1, A=1 (gi tr c v ca PINB l 0b00001011 nh phn). Chn
C=0 tc c 1 nt hng th 3 c nhn, chng ta li ang Bc th 2tc
nt nhn thuc ct th 2. Chng ta c th dng qu trnh qut ti y v kt qu
thu v nt hng 3, ct 2 (tc nut '2' c) c nhn.
Qu trnh qut cho cc nt khc cng xy ra tng t. Ch , nu c 1 nt
no c nhn th c 4 kh nng c th c v t 4 A,B,C,D l:
D=1, C=1, B=1, A=0: nt hng A c nhn, gi tr c v l 0x0E (cc

ng A,B,C,D c ni vi 4 bit thp ca PORT trn AVR).
D=1, C=1, B=0, A=1: nt hng B c nhn, gi tr c v l 0x0D .
D=1, C=0, B=1, A=1: nt hng C c nhn, gi tr c v l 0x0B .
D=0, C=1, B=1, A=1: nt hng D c nhn, gi tr c v l 0x07 .
tin li khi so snh kt qu c v, khi lp trnh c keypad chng ta nn

lp 1 mng 4 phn t cha 4 s c th c v t keypad. V d uint8_t
scan_code[4]={0x0E,0x0D,0x0B,0x07};
Trong phn tip theo chng ta s kho st cch c keypad 4x4 bng 1 chip
AVR Atmega32.
II. c Keypad 4x4 bng AVR.
Chng ta s m phng cch c v hin th gi tr t keypad 4x4 bng phn
mm Proteus. Cc m c c t keypad s hin th ln 1 Text LCD 16x2. Th
vin myLCD.h c dng hin th ln LCD (xem li bi Text LCD). Mch in
m phng th hin trong hnh 2.
Hnh 2. c v hin th t Keypad 4x4.

Hy to 1 Project bng WinAVR vi tn gi KEYPAD, to file main.c v add
vo Project, to Makefile, ng thi copy file myLCD.h t bi hc Text LCD vo
th mc cha Project KEYPAD. M file myLCD.h v sa phn khai bo PORT
nh List0.
List 0. Khai bo PORT trong file myLCD.h
01 ....
02 #define CTRL
03 #define DDR_CTRL
04
05 #define DATA_O
06 #define DATA_I
07 #define DDR_DATA
08 ....
PORTC
DDRC
PORTC
PINC
DDRC
Vit on code trong List1 vo file main.c

List 1. Ni dung file main.c
dng 3 chng ta include file myLCD.h s dng cc hm thao tc Text

LCD. Trong cc dng 5, 6 v 7 chng ta nh ngha PORT giao tip vi Keypad,
theo PORTB c dng cho Keypad. Dng 9 khai bo mt mng 4 phn t
cha m c v t Keypad nh tho lun trong phn trn. Cc dng code t
10 n 13 khai bo mt mng 2 chiu c 16 phn t cha m ASCII ca cc k
t i din cho cc Button, ti sp xp cc k t dng ma trn d dng tng
ng vi cc nt trn keypad. Dng 14 khai bo bin key loi 8 bit khng du,
y l bin cha m ascii khi c keypad. Dng 15 khai bo hm qut Keypad
c tn checkpad(). Tt c gii thut qut v c keypad u nm trong hm ny,
gi tr tr v ca hm l m ascii ca nt c nhn.
Trc khi kho st on code trong chng trnh main, chng ta s tm hiu
chng trnh con checkpad(). dng 31 trong chng trnh con checkpad,
chng ta khai bo 3 bin ph 8 bit khng du, i l bin i din cho ct ca
keypad v j l hng, keyin l gi tr c v t cc chn A, B, C, D. Vng
lp for 4 ln trong dng 32 ca bin i chnh l 4 bc qut m ti trnh by
trong v d trn. bc 1, bin i=0, nu chng ta dch tri s 1 nh (1<<(4+i))
th gi tr thu c l (1<<(4+i))=0b00010000, kt hp vi dng code
33: KEYPAD_PORT=0xFF-(1<<(4+i)); chng
ta
thu
c
KEYPAD_PORT=0xEF. S 4 trong php dch xut hin v cc ct ca Keypad
c ni vi 4 bit cao ca PORT trn AVR. Tm li, sau bc u tin ct th
nht ca Keypad c ko xung mc 0, sn sng cho qu trnh kim tra cc
hng A,B,C,D trong cc dng tip theo. Dng 35 c gi tr t Keypad v bin
keyin, v chng ta kt ni cc chn A,B,C,D ca Keypad vi 4 bit thp ca
PORT nn chng ta ch quan tm n gi tr ca 4 bit thp ny, vic AND (&)
gi tr c v vi 0x0F cho php chng ta b qua 4 bit cao. Trong dng 36,
chng ta kim tra xem nu gi tr c v khc 0x0F th thc hin cc dng tip
theo. Nu keyin =0x0F ngha l khng c bt k nt no trn ct 1 c nhn,
cc dng tip theo khng thc hin, vng lp for cho bin i c tip tc gi tr
tip theo. Nu bin keyin khc 0x0F th chng ta bit rng c 1 nt no trn
ct i c nhn, cc dng tip theo s xc nh chnh xc nt no c nhn.
Dng 37 cho bin hng j chy t 0 n 4, dng 38 kim tra gi tr keyin, nu
keyin bng phn t th j trong mng scan_code m chng ta nh ngha trc
th nt trn hng j c nhn, tm li nt c nhn l nt hng j v ct i,
chng ta tr v gi tr m ascii ca nt ny bng cch ly gi tr tng ng ca
mng ascii_code c nh ngha trc : return ascii_code[j][i]. Nu qu
trnh qut tht bi chng ta tr v gi tr 0.
Ni dung ca chng trnh chnh l khi ng chip v thc hin demo qu

trnh c Keypad, Dng 19 chng ta khai bo s dng 4 bit thp ca
KEYPAD_PORT lm input (cc chn A,B,C,D l input) v 4 bit cao lm output.
Dng 18 khi ng cc in tr ko ln cho 4 bit thp. Hai dng 21 v 22 khi
ng v xa Text LCD. Trong vng lp v tn while(1), chng ta qut keypad
dng 24 v hin th ln LCD dng 25 (ch hin th nu qu trnh qut thnh
cng).
Trong v d ny ti ch trnh by gii thut qut Keypad c bn, vn cn mt
s vn khc nh kim tra s kin nhn (key down), th (key up)...bn c
hy t gii tuyt theo cch ca ring mnh.
C cho AVR
5
( 109 Votes )
Ni dung
1.
Mt s khi nim C cho AVR.
Lm quen AVR.
2.
Cu trc iu khin v hm.
Cu trc AVR.
3.
V d minh ha.
WinAVR.
Nh ti trnh by cc bi hc trc, khi bn hiu AVR, thc hin

cc ng dng, bn c th khng nht thit phi lun lp trnh bng
Assembly(ASM). Ngn ng cp cao nh C s gip cho bn xy dng cc ng
dng nhanh chng v d dng hn, tuy nhin khng v th m bn qun ASM,
lp trnh bng C kt hp ASM l gii php hay nht. Mt ch l chng ta ch
s dng C n gin ha lp trnh tnh ton, cu trc iu khinlp trnh C
cho AVR khng c ngha l bn khng cn bit cu trc v cch thc hot ng
ca chip. Ti khng c nh ni v ngn ng C y nhng ch gii thiu
mt cch c bn nht v cch vit chng trnh cho AVR bng C, c th l C
trong avr-gcc. c th hiu v vit nhng chng trnh phc tp hn, bn cn
t trang b kin thc v C, ti liu ny s khng gip bn phn . Tuy nhin,
nu bn cha tng lp trnh bng C th bn cng yn tm c ti liu ny, v t ra
ti s gii thch nhng g ti vit.
I. Mt s khi nim C cho AVR.
Mt chng trnh C cho AVR thng bao gm cc thnh phn nh: ch

thch (comments), biu thc (expressions), cu lnh (statements), khi (blocks),
ton t, cu trc iu khin (Flow controls), hm (functions)
Ch thch (comments): c 2 cch to phn ch thch trong C l ch thch
tng dng bng 2 du // nh trong dng u ca on v d //day la chu thich,
khong duoc bien dich hoc ch thch block bng cch kp block cn ch thch vo
gia /* .*/ v d:
/*
Ban co the type bat ky chu thich nao trong block nay
Ngay ca khi ban xuong dong
Phan chu thich thuong co mau chu la green
*/
Tin x l (preprocessor): l mt tin ch ca ngn ng C, cc preprocessor
c trnh bin dch x l trc tt c cc phn khc, cc preprocessor c chc
nng tng t cc Directive trong ASM cho AVR.Cc preprocessor c bt u
bng du #, trong s cc preprocessors trong ngn ng C c hai preprocessors
c s dng ph bin nht l#include v #define. Preprocessor #include ch nh
1 file c nh km trong qu trnh bin dch (tng ng .INCLUDE trong
ASM) v #define nh ngha 1 chui thay th hoc 1 macro. Xem cc v d sau:
#include "avr/io.h" *nh km ni dung file io.h trong lc bin dch (file io.h
nm trong th mc con avr ca th mc include trong th mc ci t ca
WinAVR).*/
#define max (a,b) ((a)>(b)? (a): (b)) /*nh ngha mt macro tm s ln nht
trong 2 s a v b, trong chng trnh nu bn gi x=max(2,3) th kt qu thu
c x=3.*/
Biu thc (Expressions): l 1 phn ca cc cu lnh, biu thc c th bao

gm bin, ton t, gi hm, biu thc tr v 1 gi tr n. Biu thc khng phi
l 1 cu lnh hon chnh. V d: PORTB=val.
Cu lnh (Statement): thng l 1 dng lnh hon chnh, c th bao gm cc
keywords, biu thc v cc cu lnh khc v c kt thc bng du ;. V d:
unsigned char val=1; val*=2; l cc cu lnh.
Khi (Blocks): l s kt hp ca nhiu cu lnh thc hin chung 1 nhim
v no , khi c bao bi 2 du m khi { v ng khi }: v d 1 khi:
while(1){
PORTB=val;
val*=2;
if (!val) val=1;
}
Ton t (Operators): l nhng k hiu bo cho trnh bin dch cc nhim v
cn thc hin, cc bng bn di tm tt cc ton t C dng cho lp trnh AVR:
Bng 1 cc ton t i s: dng thc hin cc php ton i s quen thuc,

trong ng ch l cc ton t ++ (tng thm 1) v -- (bt i 1), ch phn
bit y=x++ v y=++x, v d ta c x=3 trong khi y=x++ ngha l gn x cho y ri
sau tng x thm 1, iu ny khng nh hng n y (cui cng y=3, x=4) trong
khi y=++x ngha l tng x trc ri mi gn cho y (cui cng y=x=4), tng t cho
cc trng hp ca ton t -- .
Bng 2 Ton t truy cp v kch thc: ton t [] thng c s dng khi

bn dng mng trong lc lp trnh, phn t th ca mng s c truy xut thng
qua [i], ch mng trong C bt u t 0.
Bng 3 Ton t Logic v quan h: thc hin cc php so snh v logic,

thng c dng lm iu kin trong cc cu trc iu khin, ch ton t so
snh bng ==, ton t ny khc vi ton t gn =, trong khi y = x ngha l ly
gi tr ca x gn cho y th (y== x) ngha l nu y bng x.
Bng 4 Ton t thao tc Bit (Bitwise operator): l cc ton t thc hin

trn tng bit nh phn ca cc con s, cc ton t dch tri << v dch phi
">>" rt thng c s dng khi x l s.
Bng 5 cc ton t khc: l 1 s ton t c bit rt hay s dng nhng

chng ta thng khng v vai tr ca chng rt d nhn thy. c bit ch
ton t ?: l 1 ton t rt c bit ca C so vi cc ngn ng lp trnh khc, ?:
l ton t 3 ngi duy nht c th dng thay th cho cu trc if n gin.
II. Cu trc iu khin v hm.

2.1 Cu trc iu khin (Flow Controls).
Cc cu trc iu khin bin tng ca bn thnh hin thc. Mt s cu trc
iu khin c bn trong C nh sau:
If (iu kin) statement;: nu iu kin l ng th thc hin statement
theo sau, statement c th c trnh by cng dng hoc dng sau iu khin If.
iu kin c th l mt biu thc bt k, c th l s kt hp ca nhiu iu kin
bng cc ton t quan h AND (&&), OR (||)iu kin c cho l ng khi n
khc 0, v d if (1) th iu kin hin nhin l ng. Xt mt vi v d dng cu
trc if nh sau:
If (!val) val=1; ngha l nu val bng 0 th chng trnh s gn cho val gi tr
l 1, ! l ton t NOT, NOT ca mt s khc 0 th bng 0, ngc li, NOT ca 0
th thu c kt qu l 1. Trong v d ny, nu val bng 0 th !val s bng 1, nh
th iu kin s tr thnh ng v cu lnh val=1 c thc thi.
If (x==1 && y==2) result=A; ngha l nu x bng 1 v y bng 2 th gn k
t A cho bin result. Trong v d ny, ton t logic && c s dng ni
2 iu kin li, bn hon ton c th s dng nhiu ton t logic khc nu cn thit.
Trong trng hp bn mun thc thi nhiu cu lnh cng lc nu mt iu kin
no tha th bn cn t tt c cc cu lnh trong 1 khi nh bn di:
If (iu kin) {
Statement1;
Statement2;
}
If (iu kin ) statement1; else statement2; : nu iu kin ng th thc
hin statement1, ngc li thc thi statement2. Vic t cc statement v else..trn
cng 1 dng hay trn nhng dng khc nhau u khng nh hng n kt qu.
Tng t trng hp trn, nu c nhiu statements th cn t chng trong 1 khi.
If (iu kin) {
Statement1;
Statement2;
}else {
Statement1;
Statement2;
}
Ngoi ra, bn cng c th t nhiu cu trc ifelse lng vo nhau.
Cu trc switch: trong trng hp c nhiu kh nng c th xy ra cho 1 biu
thc (hay 1 bin), ng vi mi kh nng bn cn chng trnh thc hin mt vic
no , khi ny bn nn s dng cu trc switch. Cu trc ny c trnh by nh
bn di.
switch (biu thc) {
case hng_s_1:
cc statement1;
break;
case hng_s_2:
cc statement2;
break;
default:
cc statement khc;
}
Hy xt 1 v d bn kt ni 2 chip AVR vi nhau, 1 chip lm Master s ra cc
lnh iu khin chip Slave, chip Slave nhn m lnh t Master v thc hin cc
cng vic c tho hip trc. Gi s m lnh c lu trong bin Command,
di y l chng trnh v d cch x l ca chip Slave ng vi tng m lnh.
switch (Command) {
case 1:
PWM=255;
ON_Motor();
break;
case 2:
PWM=0;
OFF_Motor();;
break;
default:
Get_Cmd();
break;
}Ngoi ra, bn cng c th t nhiu cu trc ifelse lng vo nhau.
Nu Command=1, gn gi tr 255 cho bin PWM v gi chng trnh con
ON_Motor(). Trong trng hp ny, break c s dng, break ngha l thot khi
cu trc iu khin hin ti ngay lp tc, nh vy sau khi thc hin 2 lnh, switch
kt thc m khng cn xt n cc trng hp khc. By gi, nu Command=2,
gn gi tr 0 cho bin PWM v gi chng trnh con OFF_Motor(), trong tt c cc
trng hp cn li (default), thc hin chng trnh con Get_Cmd().
while (iu kin ) statement1;: l mt cu trc lp (Loop), ngha ca cu
trc while l khi iu kin cn ng th s thc hin statement1 (hoc cc
statements nu chng c t trong 1 khi {} nh trong trng hp ca if c
gii thiu trn). Cn thn, bn rt d ri vo mt vng lp khng li thot vi
while nu iu kin lun lun ng.
for (biu_thc_1; biu_thc_2; biu_thc_3) statement;: l mt cu trc
lp khc, trong cu trc for, biu_thc_1 thng c hiu l khi to,
biu_thc_2 l iu kin v biu_thc_3 l biu thc c thc hin sau. Cu trc
for ny tng ng vi cu trc while sau:
biu_thc_1;
while (biu_thc_2){
statement;
biu_thc_3;
}
Cc biu thc trong cu trc for c th vng mt trong cu trc nhung cc
du ; th khng c b. Nu bn vit for( ; ; ) tng ng vi vng lp v tn
while (1).
Cu trc for thng c dng thc hin 1 hay nhng cng vic no
trong s ln no , v d bn di thc hin xut cc gi tr t 0 n 200 ra
PORTB, sau mi ln xut s gi lnh delay trong 65000 chu k my.
for (uint8_t i=0; i<=200; i++){
PORTB=i;
}
Ch , bn c th thc hin vic khai bo 1 bin (xem phn khai bo bin bn
di) ngay trong cu trc for nu bin ln u c s dng. V d trn c hiu
nh sau: khai bo 1 bin i kiu byte khng m, gn gi tr khi u cho i=0 (ch
thc hin 1 ln duy nht), kim tra iu kin i<=200 (nh hn hoc bng 200), nu
iu kin cn ng, thc hin 2 statements trong block {}, sau quay v thc
hin i++ (tng i thm 1) ri li kim tra iu kin i<=200 v qu trnh lp li. Nh
th on code trong {} c thc thi khong 201 ln trc khi bin i bng 201 v
iu kin i<=200 sai.
2.2 Hm (Functions).
Ngn ng C bao gm tp hp ca rt nhiu hm, mi hm thc hin mt chc
nng c th, cc hm trong C thng c thit kt rt nh gn, c cc hm
phc tp ngi dng cn t to ra. Hm C cho AVR c nh ngha trong th vin
avr-libc, ngoi cc hm C thng thng, avr-libc cn cha rt nhiu cc hm ring
dng ring cho chip AVR, cc hm ny c khai bo trong cc file header ring,
s dng hm no, bn cn #include file header tng ng (tham kho ti liu
avr-libc user manual bit thm chi tit, trong ti liu ny, khi cn s dng mt
hm no ti s ni r file header cn thit).
V d: _delay_loop_2(65000) l mt hm c nh ngha trong file delay.h
(trong th mc C:\WinAVR\avr\include\util), hm ny thc hin vic delay khong
65000 chu k my. C 4 hm delay bn c th s dng sau khi include file l:
_delay_loop_1(uint8_t __count) : delay theo mt s ln chu k my nht

nh (bin __count), s lng chu k delay l s 8 bit (t 0 n 255).

(Ch : thc cht 2 hm delay trn c nh ngha trong file header
delay_basic.h).
_delay_us(double __us): delay 1 microsecond.
_delay_ms(double __ms): delay 1 milisecond.

Ch : dng 2 hm _delay_us v _delay_ms cn nh ngha tn s xung
clock trong Makefile (bin F_CPU), s dng 2 hm ny trc tip thng cho kt
qu khng nh mong mun, ti s trnh by cch s dng 2 hm ny trong v d
bn di.
Main: mt chng trnh C cho AVR phi bao gm 1 chng trnh chnh main,
tt c cc ni dung chnh s c t bn trong chng trnh chnh. Cu trc
chng trnh chnh c th nh sau:
int main(void){
//noi dung chinh
return 0; //gia tri tra ve cho chuong trinh chinh
}
Trong , int l kiu gi tr tr v ca main, t kha void ni rng chng
trnh chnh ca chng ta khng cn bt k tham s no km theo.
Cn rt nhiu cc vn lin quan n C cho AVR, chng ta s tm hiu trong
lc vit cc v d c th.
III. V d minh ha.
minh ha cc khi nim v phng php lp trnh C cho AVR, ti s gii
thch v d qut LED vit bng C m chng ta thc hin trong bi hng dn
WinAVR. on code c trnh by trong List 1.
List 1. v d qut LED bng C.
1 //file: main.c
2 //Description: Cung hoc avr, www.hocavr.com
5 unsigned char val=1;
6 int main(void){
7
DDRB=0xFF; //x dng PORTD lm ng xut d liu
8
while(1){
9
PORTB=val;
10
11
val*=2;
12
if (!val) val=1;
13
14
15
}
return 0;
}
Trc ht l preprocessor nh km cc file khi bin dch, #include l nh

km file header io.h, file ny thc ra khng phi l file cha cc thng tin v chip
nhng n s lm mt nhim v trung gian l nh km 1 file khc tng ng vi
bin MCU trong Makefile, v d trong Makefile, MCU=atmega8 th dng
#include c thc thi, file iom8.hc t ng nh km km vo v file
iom8.h mi thc cht cha cc nh ngha cho chip ATmega8 (cc nh ngha v
a ch thanh ghi, kch thc b nh,). iu ny gip bn khng cn nh ht tt
c cc file header ca tng chip AVR. Nu khng an tm, bn c th thm
dng #include iom8.h sau khi include io.h (iu ny khng tht s cn thit).
Ngoi ra, mi ln include file io.h s c 4 file header khc c t ng nh
km l avr/sfr_defs.h, avr/portpins.h, avr/common.h, v
avr/version.h. Tm li bn cn (hoc phi) include file io.h v khai bo loi
chip AVR trong file Makefile (dng MFile, nh hng dn trn) l c th an
tm vit chng trnh C cho AVR.
- Dng th 4 include file header delay.h s dng lnh delay nh cp
trn.
- Dng 5 : khai bo 1 bin tn val trong b nh SRAM, kiu ca val l
unsigned char l kiu d liu 8 bit khng du c khong gi tr t 0 n 255. Bin
val c dng lm bin tm cha gi trc khi xut ra PORTB. Bin trong C
c khai bo bng cch t kiu bin trc sau tn bin. Mt s kiu d liu
c bn trong C c tm tt trong bng 6.
Bng 6 cc kiu d liu trong C.
Tn kiu d liu (Data S byte
type)
Khong d liu (Range)
char
127 to 127 or 0 to 255
unsigned char
0 to 255
signed char
127 to 127

type)
Khong d liu (Range)
int
32,767 to 32,767
unsigned int
0 to 65,535
signed int
Nh kiu int
short int
Nh kiu int
unsigned short int
0 to 65,535
signed short int
Nh kiu short int
long int
2,147,483,647 to 2,147,483,647
signed long int
Nh kiu long int
unsigned long int
0 to 4,294,967,295
long long int
(2631) to 2631 (C99 only)
signed long long int
same as long long int (C99 only)
unsigned long long int 8
0 to 2641 (C99 only)
float
6 digits of precision
double
long double
12
Mt s kiu d liu thng dng nht l char (1 byte), int (2 byte) v float. T
kha unsigned c thm trc 1 kiu d liu nguyn ch nh cc s nguyn
dng, khi khong gi tr nguyn s c tng ln gn 2 ln. V d char ch cc
s nguyn t -127 n 127 thng c dng ch m ASCII ca cc k t trong
bng m ASCII, nhng unsigned char s bao gm cc s nguyn dng t 0 n
255 v thng c dng khi lm vic vi cc thanh ghi 8 bit.
Ngoi ra, avr-libc cn nh ngha mt s kiu d liu thay th, chng ta c th
dng cc kiu d liu ny thay cho cc kiu thng thng, xem tm tt nh bn
di.
Mt khai bo uint8_t val tng ng usigned char val, s dng kiu khai
bo no l do thi quen ca ngi s dng. Ch l theo mc nh, mt bin mi
c khai bo theo cch thng thng nh trn s c t trong SRAM, nh cc
bn bit SRAM trong AVR tng i nh v th nn khai bo v s dng hp l
bin, ng khai bo qu nhiu bin nu bn khng s dng ht, ng khai bo kiu
bin qu ln so vi gi tr tht s dng, tuy nhin cng khng c khai bo kiu
d liu c kch thc qu nh so vi gi tr m bin c th vn ti. S dng b
nh chng trnh (flash program memory) lu tr d liu khng i l mt k
thut khc tit kim b SRAM, ti s cp vn ny trong 1 bi khc.
Cui cng v vic khai bo bin, mt bin c th c gn gi tr khi to
ngay lc khai bo nh trong trng hp ca chng ta, bin val=1 lc c khai
bo.
- Dng 6 int main(void){ bt u chng trnh chnh.
- Dng 7: DDRB=0xFF gn gi tr hexadecimal 0xFF (11111111) cho thanh
thi iu khin ca Port B, DDRB, Port B khi s tr thnh Port xut
- Dng 8 while (1){: bt u 1 vng lp v tn.
- Dng 9 v dng 10: xut val ra PORTB v gi lnh delay.

- Bn cn ch 11 v 12, 2 dng ny c chc nng xoay gi tr ca bin val
xut ra PORTB to hiu ng xoay vng. val*=2 c hiu l val=val*2, y l
1 kiu vit thu gn ca C, nu ton hng th nht v kt qu tr v l cng 1 bin,
chng ta c th b bt 1 tn bin v di chuyn ton t v bn phi ton t gn =.
V d: i = i + 6 c rt gn thnh i + = 6.
Nh th sau cu lnh val*=2 gi tr ca val c tng ln 2 ln. ngha tht

s ca vic gp i bin val l g? Hy nhn vo gi tr nh phn ca val, lc khai
bo val, chng ta gn cho val = 1 hay val = 00000001 (nh phn), sau khi gp i
ln th nht, val = 2=00000010, tip tc gp i ln th hai, val = 4=00000100
c th bn thy chuyn g xy ra? y l cu tr li: trong thao tc vi s nh
phn, gp i mt s ngha l di chuyn s sang tri 1 v trQu trnh gp i
s tip din n lc val = 128=10000000, nu tip tc gp i, bn ngh val = 256 ?
Tuy nhin bn nh rng chng ta khai bo bin val c kiu unsigned char (8
bits), trong khi 256=100000000 (9 bits), nu gn val = 256, ch c 8 bits thp
(00000000) ca 256 s c gn cho val, kt qu l val = 0. Ni mt cch khc,
sau khi val=128, val = 0, cu lnh: if (!val) val=1; s gip cho qu trnh qut
lp quay li t u nu val = 0. Mi th r.
Cui cng v chng trnh chnh ca chng ta c kiu int (int main) chng ta
cn tr v mt gi tr no , return 0; thc hin tr v 0 (bn c th tr v gi
tr no ty ).
Text LCD
( 100 Votes )
Ni dung
Cc bi cn tham kho tr
1.
Bn s i n u.
Cu trc AVR
2.
Text LCD.
WinAVR
3.
AVR v Text LCD.
C cho AVR.
4.
V d iu khin Text LCD bng th vin myLCD.
M phng vi Proteu
Download v d
I. Bn s i n u.
Bi ny nm trong phn ng dng AVR thuc lot bi cng hc AVR. Trong
bi ng dng ny chng ta khng kho st nhiu cu trc AVR m ch yu l tm
hiu Text LCD cch iu khin bng AVR. Cng c chnh cng l 2 b phn mm
quen thuc WinAVR v Proteus.
- Cu trc Text LCD.
- Nguyn l hot ng Text LCD
- Pht trin 1 th vin iu khin Text LCD bng AVR c 2 ch 8 bit v 4
bit.
- V d iu khin Text LCD bng AVR.
II. Text LCD.
Text LCD l cc loi mn hnh tinh th lng nh dng hin th cc dng ch
hoc s trong bng m ASCII. Khng ging cc loi LCD ln, Text LCD c chia
sn thnh tng v ng vi mi ch c th hin th mt k t ASCII. Cng v l
do ch hin th c k t ASCII nn loi LCD ny c gi l Text LCD ( phn
bit vi Graphic LCD c th hin th hnh nh). Mi ca Text LCD bao gm cc
chm tinh th lng, vic kt hp n v hin cc chm ny s to thnh mt
k t cn hin th. Trong cc Text LCD, cc mu k t c nh ngha sn. Kch
thc ca Text LCD c nh ngha bng s k t c th hin th trn 1 dng v
tng s dng m LCD c. V d LCD 16x2 l loi c 2 dng v mi dng c th
hin th ti a 16 k t. Mt s kch thc Text LCD thng thng gm 16x1,
16x2, 16x4, 20x2, 20x4Hnh 1 l mt v d Text LCD 16x2.
Hnh 1. Text LCD 16x2.

Text LCD c 2 cch giao tip c bn l ni tip (nh I2C) v song song. Trong
phm vi bi hc ny ti ch gii thiu loi giao tip song song, c th l LCD 16x2
iu khin bi chip HD44780U ca hng Hitachi. i vi cc LCD khc bn cn
tham kho datasheet ring ca tng loi. Tuy nhin, HD44780U cng c coi l
chun chung cho cc loi Text LCD, v th bn c th dng chng trnh v d
trong bi ny test trn cc LCD khc vi rt t hoc khng cn chnh sa.
HD44780U l b iu khin cho cc Text LCD dng ma trn im (dotmatrix), chip ny c th c dng cho cc LCD c 1 hoc 2 dng hin th.
HD44780U c 2 mode giao tip l 4 bit v 8 bit. N cha sn 208 k t mu kch
thc font 5x8 v 32 k t mu font 5x10 (tng cng l 240 k t mu khc nhau).
1. S chn.
Cc Text LCD theo chun HD44780U thng c 16 chn trong 14 chn kt
ni vi b iu khin v 2 chn ngun cho n LED nn. Th t cc chn
thng c sp xp nh sau:
Bng 1. S chn.
Trong mt s LCD 2 chn LED nn c nh s 15 v 16 nhng trong mt

s trng hp 2 chn ny c ghi l A (Anode) v K (Cathode). Hnh 2 m t
cch kt ni LCD vi ngun v mch iu khin.
Hnh 2. Kt ni Text LCD.

Chn 1 v chn 2 l cc chn ngun, c ni vi GND v ngun 5V. Chn 3
l chn chnh tng phn (contrast), chn ny cn c ni vi 1 bin tr chia
p nh trong hnh 2.Trong khi hot ng, chnh thay i gi tr bin tr t
c tng phn cn thit, sau gi mc bin tr ny. Cc chn iu khin
RS, R/W, EN v cc ng d liu c ni trc tip vi vi iu khin. Ty theo
ch hot ng 4 bit hay 8 bit m cc chn t D0 n D3 c th b qua hoc ni
vi vi iu khin, chng ta s kho st k cng hn trong cc phn sau.
2. Thanh ghi v t chc b nh.
HD44780U c 2 thanh ghi 8 bits l INSTRUCTION REGISTER (IR) v
DATA REGISTER (DR). Thanh ghi IR cha m lnh iu khin LCD v l thanh
ghi ch ghi (ch c th ghi vo thanh ghi ny m khng c c n). Thanh ghi
DR cha cc cc loi d liu nh k t cn hin th hoc d liu c ra t b nh
LCDC 2 thanh ghi u c ni vi cc ng d liu D0:7 ca Text LCD v
c la chn ty theo cc chn iu khin RS, RW. Thc t iu khin Text
LCD chng ta khng cn quan tm n cch thc hot ng ca 2 thanh ghi ny, v
th cng khng cn kho st chi tit chng.

HD44780U c 3 loi b nh, l b nh RAM d liu cn hin th DDRAM
(Didplay Data RAM), b nh cha ROM cha b font to ra k t CGROM
(Character Generator ROM) v b nh RAM cha b font to ra cc symbol ty
chn CGRAM (Character Generator RAM). iu khin hin th Text LCD
chng ta cn hiu t chc v cch thc hot ng ca cc b nh ny:
2.1 DDRAM.
DDRAM l b nh tm cha cc k t cn hin th ln LCD, b nh ny gm
c 80 c chia thnh 2 hng, mi c rng 8 bit v c nh s t 0 n
39 cho dng 1; t 64 n 103 cho dng 2. Mi nh tng ng vi 1 trn mn
hnh LCD. Nh chng ta bit LCD loi 16x2 c th hin th ti a 32 k t (c 32
hin th), v th c mt s nh ca DDRAM khng c s dng lm cc
hin th. hiu r hn chng ta tham kho hnh 3 bn di
Hnh 3. T chc ca DDRAM.

Ch c 16 nh c a ch t 0 n 15 v 16 a ch t 64 n 79 l c
hin th trn LCD. V th mun hin th mt k t no trn LCD chng ta cn
vit k t vo DDRAM 1 trong 32 a ch trn. Cc k t nm ngoi 32 nh
trn s khng c hin th, tuy nhin vn khng b mt i, chng c th c
dng cho cc mc ch khc nu cn thit.
2.2 CGROM.
CGROM l vng nh c nh cha nh ngha font cho cc k t. Chng ta
khng trc tip truy xut vng nh ny m chip HD44780U s t thc hin khi c
yu cu c font hin th. Mt iu ng lu l a ch font ca mi k t
vng nh CGROM chnh l m ASCII ca k t . V d k t a c m ASCII l
97, tham kho t chc ca vng nh CGROM trong hnh 4 bn s nhn thy a
ch font ca a c 4 bit thp l 0001 v 4 bit cao l 0110, a ch tng hp l
01100001 = 97.
CGROM v DDRAM c t ng phi hp trong qu trnh hin th ca
LCD. Gi s chng ta mun hin th k t a ti v tr u tin, dng th 2 ca
LCD th cc bc thc hin s nh sau: trc ht chng ta bit rng v tr u tin
ca dng 2 c a ch l 64 trong b nh DDRAM (xem hnh 3), v th chng ta s
ghi vo nh c a ch 64 mt gi tr l 97 (m ASCII ca k t a). Tip theo,
chip HD44780U c gi tr 97 ny v coi nh l a ch ca vng nh CGROM, n

s tm n vng nh CGROM c a ch 97 v c bng font c nh ngha
sn y, sau xut bn font ny ra cc chm trn mn hnh LCD ti v tr u
tin ca dng 2 trn LCD. y chnh l cch m 2 b nh DDRAM v CGROM
phi hp vi nhau hin th cc k t. Nh m t, cng vic ca ngi lp trnh
iu khin LCD tng i n gin, l vit m ASCII vo b nh DDRAM ti
ng v tr c yu cu, bc tip theo s do HD44780U m nhim.
Hnh 4. Vng nh CGROM.

2.3 CGRAM.
CGRAM l vng nh cha cc symbol do ngi dng t nh ngha, mi
symbol c c kch thc 5x8 v c dnh cho 8 nh 8 bit. Cc symbol
thng c nh ngha trc v c gi hin th khi cn thit. Vng ny c tt
c 64 nh nn c ti a 8 symbol c th c nh ngha. Ti liu ny khng
cp n s dng b nh CGRAM nn ti s khng i chi tit phn ny, bn c th
tham kho datasheet ca HD44780U bit thm.
3. iu khin hin th Text LCD.
3.1 Cc chn iu khin LCD.
Cc chn iu khin vic c v ghi LCD bao gm RS, R/W v EN.
RS (chn s 3): Chn la chn thanh ghi (Select Register), chn ny cho php
la chn 1 trong 2 thanh ghi IR hoc DR lm vic. V c 2 thanh ghi ny u
c kt ni vi cc chn Data ca LCD nn cn 1 bit la chn gia chng.
Nu RS=0, thanh ghi IR c chn v nu RS=1 thanh ghi DR c chn. Chng
ta u bit thanh ghi IR l thanh ghi cha m lnh cho LCD, v th nu mun gi 1
m lnh n LCD th chn RS phi c reset v 0. Ngc li, khi mun ghi m
ASCII ca k t cn hin th ln LCD th chng ta s set RS=1 chn thanh ghi
DR. Hot ng ca chn RS c m t trong hnh 5.
Hnh 5. Hot ng ca chn RS.

R/W (chn s 4): Chn la chn gia vic c v ghi. Nu R/W=0 th d liu
s c ghi t b iu khin ngoi (vi iu khin AVR chng hn) vo LCD. Nu
R/W=1 th d liu s c c t LCD ra ngoi. Tuy nhin, ch c duy nht 1
trng hp m d liu c th c t LCD ra, l c trng thi LCD bit LCD
c ang bn hay khng (c Busy Flag - BF). Do LCD l mt thit b hot ng
tng i chm (so vi vi iu khin), v th mt c BF c dng bo LCD
ang bn, nu BF=1 th chng ta phi ch cho LCD x l xong nhim v hin ti,
n khi no BF=0 mt thao tc mi s c gn cho LCD. V th, khi lm vic vi
Text LCD chng ta nht thit phi c mt chng trnh con tm gi l wait_LCD
ch cho n khi LCD rnh. C 2 cch vit chng trnh wait_LCD. Cch 1
l c bit BF v kim tra v ch BF=0, cch ny i hi lnh c t LCD v b
iu khin ngoi, do chn R/W cn c ni vi b iu khin ngoi. Cch 2 l
vit mt hm delay mt khong thi gian c nh no (tt nht l trn 1ms). u
im ca cch 2 l s n gin v khng cn c LCD, do chn R/W khng cn
s dng v lun c ni vi GND. Tuy nhin, nhc im ca cch 2 l khong
thi gian delay c nh nu qu ln s lm chm qu trnh thao tc LCD, nu qu
nh s gy ra li hin th. Trong bi ny ti hng dn bn cch tng qut l cch
1, s dng cch 2 bn ch cn mt thay i nh trong chng trnh wait_LCD
(s trnh by chi tit sau) v kt ni chn R/W ca LCD xung GND.
EN (chn s 5): Chn cho php LCD hot ng (Enable), chn ny cn c
kt ni vi b iu khin cho php thao tc LCD. c v ghi data t LCD
chng ta cn to mt xung cnh xung trn chn EN, ni theo cch khc, mun
ghi d liu vo LCD trc ht cn m bo rng chn EN=0, tip n xut d liu
n cc chn D0:7, sau set chn EN ln 1 v cui cng l xa EN v 0 to 1
xung cnh xung.
3.2 Tp lnh ca LCD.
Bng 2 tm tt cc lnh c th ghi vo LCD
Danh sch lnh trn c ti t 2 mu khc nhau, cc lnh mu s c

dng thng xuyn trong lc hin th LCD v cc lnh mu xanh thng ch c
dng 1 ln trong lc khi ng LCD, ring lnh Read BF c th c dng hoc
khng ty theo cch vit chng trnh wait_LCD. Phn tip theo ti gii thch
ngh ca cc lnh v tham s km theo chng.
Trc ht l nhm lnh :
- Clear display xa LCD: lnh ny xa ton b ni dung DDRAM v v th
xa ton b hin th trn LCD. V y l 1 lnh ghi Instruction nn chn RS phi

c reset v 0 trc khi ghi lnh ny ln LCD. M lnh xa LCD l 0x01(ghi vo
D0:D7).
- Cursor home a con tr v v tr u, dng 1 ca LCD: lnh ny thc hin
vic a con tr v v tr u tin ca b nh DDRAM, v th nu sau lnh ny mt
bin c ghi vo DDRAM th bin ny s nm v tr u tin (1;1). RS cng
phi bng 0 trc khi ghi lnh. M lnh l 0x02 hoc 0x03(chn 1 trong 2 m lnh,
ty ).
- Set DDRAM address nh v tr con tr cho DDRAM: di chuyn con tr
n mt v tr ty trong DDRAM v v th c th c dng chn v tr cn
hin th trn LCD. thc hin lnh ny cn reset RS=0. Bit MSB ca m lnh
(D7) phi bng 1, 7 bit cn li ca m lnh chnh l a ch DDRAM mun di
chuyn n. V d chng ta mun di chuyn con tr n v tr th 3 trn dng 2 ca
LCD (a ch 42) chng ta cn ghi m lnh 0xAA v 0xAA=10101010 (binary)
trong bit MSB bng 1, by bit cn li l 0101010=42, a ch ca nh mun
n.
- Write to CGRAM or DDRAM ghi d liu vo CGRAM hoc DDRAM: v
y khng phi l lnh ghi instruction m l 1 lnh ghi d liu nn chn RS cn
c set ln 1 trc khi ghi lnh vo LCD. Lnh ny cho php ghi m ASCII ca
mt k t cn hin th vo thanh ghi DDRAM. Trng hp ghi vo CGRAM
khng c kho st.
K n l nhm lnh mu xanh: nhm lnh ny thng ch thc hin 1 ln (t
nht l trong bi hc ny) v thng c vit chung trong 1 chng trnh con
khi ng LCD ( chng ta gi l init_LCD trong bi hc ny).
- Entry mode set xc lp cc hin th lin tip cho LCD: ni mt cch d
hiu, lnh ny ch ra cch m bn mun hin th mt k t tip theo 1 k t trc
. V d nu bn mun hin th 2 k t lin tip AB, trc ht bn vit A ti v tr
5, dng 1. Sau bn ghi B vo LCD, lc ny c 4 cch m LCD c th hin th B
nh sau: hin th B bn phi A ti v tr s 6 (cch 1); B cng c th c hin th
bn tri A, ti v tr s 4(cch 2); hoc LCD c th t dch chuyn A v bn tri n
v tr 4 sau hin th B bn phi A, ti v tr 5(cch 3); v kh nng cui cng l
LCD dch chuyn A v bn phi n v tr 6 sau hin th B bn tri A, ti v tr
5(cch 4). Chng ta c th chn 1 trong 4 cch hin th trn thng qua lnh Entry
mode set. y l lnh ghi Instruction nn RS=0, 5 bit cao D7:3=00000, bit D2=1,
hai bit cn li D1:0 cha m lnh la chn 1 trong 4 cch hin th. Xem li bng
2, bit D1 cha gi tr I/D v D0 cha S. Trong I/D ngha l tng hoc gim
(Increment or Decrement). I/D= 1 l hin th tng tc k t sau s hin th bn phi
k t trc, nu I/D=0 th hin th gim, tc k t sau hin th bn tri k t trc.
S l gi tr Shift, nu S=1 th cc k t trc s c y i, k t sau chim
ch k t trc, ngc li nu S=0 th v tr hin th ca cc k t trc khng

thay i. C th tm tt 4 mode hin th ng vi 4 m lnh nh sau:
+ D7:0 = 0x04 (00000100) : hin th gim v khng shift (nh cch 2 trong v
d).
+ D7:0 = 0x05 (00000101) : hin th gim v shift (nh cch 4 trong v d).
+ D7:0 = 0x06 (00000110) : hin th tng v khng shift (nh cch 1, khuyn
khch).
+ D7:0 = 0x07 (00000111) : hin th tng v shift (nh cch 3 trong v d).
- Display on/off control xc lp cch hin th cho LCD: lnh ny bao gm
cc thng s cho php LCD hin th, cho php hin th cursor v m/tt blinking.
y cng l mt lnh ghi Instrcution nn RS phi bng 0. M lnh cho lnh ny c
dng 00001DCB trong D (Display) cho php hin th LCD nu mang gi tr 1,
C (Cursor) bng 1 th cursor s c hin th v B l blinking cho cursor ti v tr
hin th (blinking l dng 1 en nhp nhy ti v tr k t ang hin th). M lnh
c dng ph bin cho lnh ny l 0x0E (00001110 - hin th cursor nhng khng
hin th blinking).
- Function set xc lp chc nng cho LCD: y l lnh thit lp phng thc
giao tip vi LCD, kch thc font ch v s lng line ca LCD. RS cng phi
bng 0 khi s dng lnh ny. M lnh function set c dng 001DLNFxx. Trong
nu DL=1 (DL: Data Length) th mode giao tip 8 bit s c dng, lc ny tt
c cc chn t D0 n D7 phi c kt ni vi b iu khin ngoi. Nu DL=0 th
mode 4 bit c dng, trong trng hp ny ch c 4 chn D4:7 c dng
truyn nhn d liu v kt ni vi b iu khin ngoi, cc chn D0:3 c
trng. N quy nh s dng ca LCD, v chng ta ang kho st LCD loi hin th 2
dng nn N=1 (N=0 cho trng hp LCD 1 dng). F l kch thc font ch hin
th, do LCD c 2 b font ch c sn trong CGROM nn chng ta cn la chn
thng qua bit F, nu F=1 b font 5x10 c s dng v nu F=0 th font 5x8 c
hin th. 2 bit thp trong m lnh ny c th c gn gi tr ty . M lnh c
dng ph bin cho lnh function set l 0x38 (00111000 giao tip 8 bit, 2 dng vi
font 5x8 ) hoc 0x28 (00101000 giao tip 4 bit, 2 dng vi font 5x8 ). V d
trong bi ny s dng c 2 m lnh trn.
3.3 Giao tip 8 bit v 4 bit.
Nh trnh by trong lnh function set, c 2 mode ghi v c d liu vo
LCD l mode 8 bit v mode 4 bit:
- Mode 8 bit: Nu bit DL trong lnh function set bng 1 th mode 8 bit c
dng. s dng mode 8 bit, tt c cc lines d liu ca LCD t D0 n D7 (t
chn 7 n chn 14) phi c ni vi 1 PORT ca chip iu khin bn ngoi (v
d PORTC ca ATmega32 trong v d ca bi ny) nh trong hnh 3. u im ca
phng php giao tip ny l d liu c ghi v c rt nhanh v n gin v chip
iu khin ch cn xut hoc nhn d liu trn 1 PORT. Tuy nhin, phng php
ny c nhc im l tng s chn dnh cho giao tip LCD qu nhiu, nu tnh
lun c 3 chn iu khin th cn n 11 ng cho giao tip LCD.
- Mode 4 bit: LCD cho php giao tip vi b iu khin ngoi theo ch 4
bit. Trong ch ny, cc chn D0, D1, D2 v D3 ca LCD khng c s dng
( trng), ch c 4 chn t D4 n D7 c kt ni vi chip b iu khin ngoi.
Cc instruction v data 8 bit s c ghi v c bng cch chia thnh 2 phn, gi l
cc Nibbles, mi nibble gm 4 bit v c giao tip thng qua 4 chn D7:4, nibble
cao c x l trc v nibble thp sau. u im ln nht ca phng php ny ti
thiu s lines dng cho giao tip LCD. Tuy nhin, vic c v ghi tng nibble
tng i kh khn hn c v ghi d liu 8 bit. Trong bi hc ny, ti s trnh by
2 chng trnh con c vit ring ghi v c cc nibbles gi l Read2Nib v
Write2Nib.
III. AVR v Text LCD.
1. Trnh t giao tip Text LCD.
Trnh t giao tip vi LCD c trnh by trong flowchart hnh 6.
Hnh 6. Trnh t giao tip vi Text LCD.

s dng LCD chng ta cn khi ng LCD, sau khi c khi ng LCD
sn sng hin th. Qu trnh khi ng ch cn thc hin 1 ln u chng
trnh. Trong bi ny, qu trnh khi ng c vit trong 1 chng trnh con tn
int_LCD, khi ng LCD thng bao gm xc lp cch giao tip, kch thc font,
s dng LCD (funcstion set), cho php hin th LCD, sursor(Display control),
ch hin th tng/gim, shift (Entry mode set). Cc th tc khc nh xa LCD,
vit k t ln LCD, di chuyn con trc s dng lin tc trong qu trnh hin
th LCD v s c trnh by trong cc on chng trnh con ring.
2. AVR giao tip vi Text LCD trong WinAVR.
Phn ny ti trnh by cch iu khin hin th Text LCD bng vi iu khin
AVR trong mi trng C ca WinAVR. Hnh thc l mt th vin hm giao tip
Text LCD trong 1 file header c tn l myLCD.h. Cc hm trong th vin bao gm
(ch l phn code trong List 0 khng nm trong file myLCD.h).
List 0. Cc hm c trong th vin myLCD.
1 char Read2Nib(); //c 2 nibbles t LCD
2 void Write2Nib(uint8_t chr); //ghi 2 nibbles vo LCD
3 void Write8Bit(uint8_t chr); //ghi tr tip 8 bit v LCD
4 void wait_LCD();
//ch LCD rnh
5 void init_LCD(); //khi ng LCD
6 void clr_LCD(); //xa LCD
7 void home_LCD(); //a cursor v home
8 void move_LCD(uint8_t y, uint8_t x); //di chuyn cursor v tr mong mun (dng, ct)
9 void putChar_LCD(uint8_t chr);
//ghi 1 k t ln LCD
10 void print_LCD(char* str, unsigned char len); //hin th chui k t
Tuy nhin, trc khi vit cc hm giao tip LCD chng ta cn nh ngha mt
s macro v bin. Hy to 1 file Header c tn myLCD.h v vit cc on code bn
di vo file ny (bt u t List 1).
List 1. nh ngha cc bin thay th.
02 #define sbi(sfr,bit) sfr|=_BV(bit)
03 #define cbi(sfr,bit) sfr&=~(_BV(bit))
04 #define EN
2
05 #define RW
1
06 #define RS
0
07 #define CTRL
08 #define DDR_CTRL
09
10 #define DATA_O
11 #define DATA_I
12 #define DDR_DATA
13 /*
14 #define LCD8BIT
15 #define DATA_O
16 #define DATA_I
17 #define DDR_DATA
18 */
PORTB
DDRB
PORTB
PINB
DDRB
PORTD
PIND
DDRD
cbi v sbi l 2 macro c dng xa v set 1 bit trong 1 thanh ghi. V d

cbi(PORTA, 5) l xa bit 5 trong thanh ghi PORT v 0. Do WinAVR khng h tr
tuy xut trc tip cc bit nn cn nh ngha 2 macro ny h tr.
Cc bin EN, RW v RS nh ngha s th t ca chn trn 1 PORT ca AVR
c dng kt ni vi cc chn EN, R/W v RS ca LCD. CTRL l bin cho
bit PORT no ca AVR c dng kt ni vi cc chn iu khin ca
LCD. DDR_CTRL l thanh ghi iu khin hng ca PORT kt ni vi cc chn
iu khin, DDR_CTRL lun ph thuc vo bin CTRL. Trong trng hp ca bi
ny, bn thy ti nh ngha CTRL l PORTB ngha l PORTB c dng kt
ni vi cc chn iu khin LCD, v CTRL l PORTB nn DDR_CTRL phi l
DDRB (thanh ghi iu khin hng ca PORTB). EN nh ngha bng 2 ngha l
chn EN ca LCD c ni vi chn 2 ca PORTB (PB2), tng t chn R/W ni
vi chn 1 PORTB (PB1) v chn RS ni vi chn 0 PORTB (PB0). Vic chn cc
PORT giao tip v th t chn ph thuc vo kt ni tht trong mch in giao
tip, bn phi thay i cc nh ngha ny cho ph hp vi thit k mch in ca
bn. L do cho vic nh ngha cc bin thay th kiu ny l nhm to ra tnh tng
qut cho th vin hm. V d, mt ngi khng mun dng PORTB iu khin
LCD m dng PORTA th ngi ny ch cn thay i nh ngha 2 dng 7 v 8,
khng cn thay i ni dung cc hm v trong cc hm ny chng ta ch dng tn
thay th l CTRL v DDR_CTRL. Tng t, ti nh ngha 3 bin thay th l
DATA_O ngha l PORT xut d liu, DATA_I l PORT nhp d liu v
DDR_DATA l thanh ghi iu khin hng. DATA_O v DATA_I l PORT ni vi
cc chn D0:7 (mode 8 bit) hoc D4:7 (mode 4 bit) ca LCD, y l cc ng
truyn v nhn d liu. Trong v d trn, ti dng chnh PORTB lm ng data v
y l trng hp giao tip 4 bit, do 3 chn u ca PORTB kt ni vi cc chn
iu khin nn PORTB ch cn tha li 5 chn, chng ta s ni 4 chn PB4, PB5,

PB6 v PB7 tng ng vi D4, D5, D6 v D7 ca LCD. Hnh 7 m t cch kt ni
AVR v LCD theo v d ny. Tt nhin bn c th s dng PORT khc lm ng
data nht l khi bn mun s dng mode 8 bit, v trong mode ny cn ti 11 ng
giao tip (3 iu khin + 8 data). Phn c che trong 2 du comment /* */ l
trng hp bn mun dng mode 8 bit. s dng mode 8 bit, bn cn nh ngha
1 bin c tn LCD8BIT, bit ny s bo cho cc on chng trnh con thc hin
ghi v c d liu theo cch 8 bit. ng thi, bn phi nh ngha li ng giao
tip data (DATA_O, DATA_I, DDR_DATA).
Hnh 7. V d Kt ni LCD vi AVR trong mode 4 bit (chip mega8).

Phn bn di l phn nh ngha cc hm trong th vin myLCD. Bn hm
u tin (xem li List 0) l cc hm h tr, chng ch c dng bi cc hm khc
trong th vin v khng c gi trong cc chng trnh ng dng bn ngoi.
List 2. c 2 nibbles t LCD.
01 char Read2Nib(){
02
char HNib, LNib;
03
DATA_O |=0xF0;
04
sbi(CTRL,EN); //enable
05
06
07
08
09
10
11
12
13
14
15 }
DDR_DATA &=0x0F; //set 4 bits cao cua PORT DATA lam input
HNib=DATA_I & 0xF0;
cbi(CTRL,EN); //disable
LNib = DATA_I & 0xF0;
LNib>>=4;
return (HNib|LNib);
Hm ny thc hin vic c d liu t LCD ra ngoi, c theo tng nibble 4

bit, kt qu tr v l 1 s 8 bit. Hm ny ch c dng duy nht khi c c Busy
(BF) trong chng trnh ch LCD rnh (wait_LCD) mode 4 bit. Trc ht cn
nh ngha 1 bin tm HNib (high nibble) v LNib (Low nibble) cha 2 nibbles
c v (dng 2, List 2). Dng 5 set chn EN ln mc 1 chun b cho LCD lm
vic. Chng ta cn i hng ca PORT d liu trn AVR sn sng nhn d liu
v, do ch c 4 bit cao ca PORT data kt ni vi cc ng data ca LCD (v y
l mode 4 bit) nn ch cn set hng cho 4 bit ny trn AVR, dng 6 thc hin vic
set hng. Trong ch 4 bit, LCD s truyn v nhn nibble cao trc v th dng
7 c d liu t LCD thng qua cc chn DATA_I vo bin HNib, ch l chng
ta ch cn ly 4 bit cao ca DATA_I nn cn phi dng gii thut mt n (mask)
che cc bit thp li (and vi 0xF0). Dng 8 xa chn EN chun b cho bc tip
theo. Tng t, cc dng 10, 11 v 12 c nibble thp vo bin LNib. Hai dng 13
v 14 kt hp 2 nibbles to thnh s 8 bit v tr kt qu v cho on chng
trnh.
List 3. Ghi 2 nibbles vo LCD.
01 void Write2Nib(uint8_t chr){
02
uint8_t HNib, LNib, temp_data;
03
temp_data=DATA_O & 0x0F; //doc 4 bit thap cua DATA_O de mask,
04
HNib=chr & 0xF0;
05
LNib=(chr<<4) & 0xF0;
06
07
DATA_O =(HNib |temp_data);
08
09
10
11
12
13
14
15 }
DATA_O =(LNib|temp_data);
Hm Write2Nib thc hin ghi mt bin 8 bit c tn chr vo LCD theo tng
nibble, hm ny c s dng rt nhiu ln trong mode 4 bit. Dng 2 nh ngha 3
bin tm l HNib, LNib v temp_data, khng ging nh khi c t LCD, vic ghi
vo LCD c th lm nh hng n cc chn ca PORT dng lm ng d liu
nht l khi cc ng iu khin v d liu dng chung 1 PORT (PORTB). Bin
temp_data dng trong gii thut mt n khng lm nh hng n cc bit khc
khi ghi LCD. Dng 3 c d liu t PORT DATA_O v che i cc bit cao, ch lu
li cc bit thp vo bin temp_data v cc bit thp ny khng c dng xut nhp
d liu (xem hnh 7, cc chn thp ca PORTB dng lm cc chn iu khin).
ghi 1 gi tr 8 bit c tn l chr theo cch ghi tng nibbles chng ta cn tch bin chr
thnh 2 nibbles. Dng 5 tch 4 bit cao ca chr v cha vo bin HNib. Dng 6 thc
hin thm vic di chuyn 4 bit thp ca chr qua tri ri gn cho bin LNib. Nh
vy sau 2 dng ny cc bin HNib v LNib c m t nh sau:
Do d liu c sp xp sn sng cc v tr cao (ng vi cc chn D4:7)

nn cng vic tip theo ch n gin l xut 2 bin HNib v LNib ra ng
DATA_O, cn phi to 1 xung cnh xung chn EN mi ln xut d liu (dng
9, 10). Ch l phi xut nibble cao trc v nibble thp theo sau.
List 4. Ghi 8 bit trc tip vo LCD.
01 void Write8Bit(uint8_t chr){
02
DATA_O=chr; //out 8 bits to DATA Line
03
04
05 }
on ny rt n gin l xut d liu 8 bit ra DATA_O, dng trong mode 8
bit. Trong mode ny, 8 chn data ca LCD c ni vi 8 ng DATA_O ca
AVR.
List 5. Ch LCD rnh.

01 void wait_LCD(){
02
#ifdef LCD8BIT
03
while(1){
04
cbi(CTRL,EN); //xa EN
05
cbi(CTRL,RS); //y l Instruction
06
sbi(CTRL,RW); //chiu t LCD ra ngoi
07
08
DDR_DATA=0xFF; //hng data out
09
DATA_O=0xFF; // gi lnh c BF
10
11
12
DDR_DATA=0x00; // i hng data in
13
if(bit_is_clear(DATA_I,7)) break;
14
}
15
cbi(CTRL,EN); //disable for next step
16
cbi(CTRL,RW); //ready for next step
17
DDR_DATA=0xFF; //Ready to Out
18
#else
19
char temp_val;
20
while(1){
21
cbi(CTRL,RS); //RS=0, the following data is COMMAND
22
sbi(CTRL,RW); //LCD -> AVR
23
temp_val=Read2Nib();
24
if (bit_is_clear(temp_val,7)) break;
25
}
26
cbi(CTRL, RW); //ready for next step
27
DDR_DATA=0xFF;//Ready to Out
28
#endif
29
//_delay_ms(1);
30 }
Hm wait_LCD ch lm mt vic n gin l ch cho n khi LCD rnh
gn cc cng vic khc. on code trong list 5 trnh by cch 1: c c Busy Flag
v ch n khi n bng 0 (LCD rnh). Vic c c BF ph thuc v mode ang s
dng l 8 bit hay 4 bit, v th lnh #ifdef trong dng s 2 kim tra mode ph hp
trc khi tin hnh c. #ifdef LCD8BIT ngha l nu bin LCD8BIT c
nh ngha pha trn (mode 8 bit c dng) th s tin hnh c BF theo mode
ny. Bng cch kim tra s c mt ca bin LCD8BIT chng trnh s bit cch
ghi v c LCD ph hp, phng php dng #ifdef LCD8BIT c p dng cho
tt c cc hm sau ny. Cc on code t dng 4 n 17 thc hin trong mode 8
bit. Trc khi c BF, chng ta cn gi 1 lnh c BF dng 9, sau dng 12
thc hin i hng cc chn data nhn gi tr v. Trong dng 10, kim tra bit
th 7 ca DATA_I, DATA_I chnh l gi tr c v v bit th 7 trong gi tr nhn v
chnh l c Busy Flag. Nu BF=0 (bit_is_clear(DATA_I,7)) th kt thc qu trnh
lp ch vi lnh break;. Trong trng hp mode 4 bit c s dng (#else), qu
trnh kim tra c BF cng tng t, im khc nhau duy nht l cch c d liu
v c khc, chng ta dng hm Read2Nib c vit trc nhn gi tr v
(xem dng 23). Nh trnh by, chng ta c th vit hm wait_LCD bng cch
dng hm delay mt khong thi gian c nh, trong dng 29 bn thy mt hm
_delay_ms(1) khng c s dng, nu mun bn c th xa ht cc dng lnh
trc trong hm wait_LCD v dng hm delay ny thay th, LCD vn s
hot ng tt.
List 6. Khi ng LCD.
01 void init_LCD(){
02
DDR_CTRL=0xFF;
03
DDR_DATA=0xFF;
04 //Function set-----------------------------------------------------------------------------05
cbi(CTRL,RS); // the following data is COMMAND
06
cbi(CTRL, RW); // AVR->LCD
07
cbi(CTRL, EN);
08
#ifdef LCD8BIT
09
Write8Bit(0x38);
10
wait_LCD();
11
#else
12
13
sbi(DATA_O, 5);
14
15
wait_LCD();
16
Write2Nib(0x28);//4 bit mode, 2 line, 5x8 font
17
wait_LCD();
18
#endif
19 //Display control------------------------------------------------------------------------20
21
#ifdef LCD8BIT
22
Write8Bit(0x0E);
23
wait_LCD();
24
#else
25
Write2Nib(0x0E);
26
wait_LCD();
27
#endif
28 //Entry mode set-----------------------------------------------------------------------29
30
#ifdef LCD8BIT
31
Write8Bit(0x06);
32
wait_LCD();
33
#else
34
Write2Nib(0x06);
35
wait_LCD();
36
#endif
37 }
Qu trnh khi ng gm 3 bc: function set, display control v entry mode
set.
Vi function set, ba dng 5,6 v 7 xc lp cc chn iu khin chun b gi
cc lnh. Hai dng 9 v 10 vit lnh function set vo LCD theo mode 8 bit. Gi tr
0x38, tc 00111000 l mt lnh xc lp mode 8 bit, LCD 2 dng v font 5x8. Nu
mode 4 bit c dng, chng ta cn vit hm function set khc i mt cht. Theo
mc nh, khi va khi ng LCD th mode 8 bit s c chn, v th nu mt hm
no c ghi vo LCD u tin, LCD s c gng c ht cc chn D0:7 ly
d liu, do trong mode 4 bit cc chn D0:3 khng c kt ni vi AVR nn vic
c ln u c th dn n sai s. V vy, vic u tin cn lm nu mun s dng
mode 4 bit l gi mt lnh function set vi tham s DL=0 (0010xxxx) n LCD
bo mode chng ta mun dng. Dng 13 lm vic ny, dng lnh ch n gin set
bit D5 nhng chnh l gi lnh dng 0010xxxx n LCD, v th LCD s vo
mode 4 bit sau lnh ny. Tip theo qu trnh thao tc vi LCD din ra bnh thng,
dng 16 ghi vo LCD m ca function set, trong trng hp ny l m 0x28,
tc00101000: mode 4 bit, LCD 2 dng v font 5x8.
Vi Display control, m lnh c dng l 0x0E, tc 00001110 trong
00001 l m ca lnh display control, 3 bit theo sau xc lp hin th LCD, hin
th cursor v khng blinking.
Vi Entry mode set, m lnh c dng l 0x06 tc hin th tng v khng
shift. Xem li phn gii thch tp lnh LCD hiu thm ngha ca m lnh
0x06.
List 7. Di chuyn cursor.
01 void home_LCD(){
02
03
#ifdef LCD8BIT
04
Write8Bit(0x02);
05
wait_LCD();
06
#else
07
Write2Nib(0x02);
08
wait_LCD();
09
#endif
10 }
11 void move_LCD(uint8_t y,uint8_t x){
12
uint8_t Ad;
13
Ad=64*(y-1)+(x-1)+0x80; // tnh m lnh
14
15
#ifdef LCD8BIT
16
Write8Bit(Ad);
17
wait_LCD();
18
#else
19
Write2Nib(Ad);
20
wait_LCD();
21
#endif
22 }
List 7 trnh by 2 hm di chuyn cursor v home (home_LCD) v di chuyn
n 1 v tr do ngi dng t. Hmhome_LCD tng i n gin v ch cn ghi
m lnh 0x02 vo LCD th cursor s t ng di chuyn v home (v tr u tin
trn LCD).
Hm move_LCD(uint8_t y,uint8_t x) cho php di chuyn cursor n v tr
dng y, ct x. im cn ch trong hm ny l cch tnh m lnh cn ghi vo
LCD. Thc cht y l lnh set DDRAM address. Xem li bng 2 ta thy m lnh
cho lnh ny c dng 1xxxxxxx trong xxxxxxx l mt s 7 bit cha a ch ca
DDRAM chng ta cn di chuyn n. V th trc khi thc hin ghi m lnh ny,
chng ta cn tnh tham s xxxxxxx theo dng y, ct x. Xem li t chc ca
DDRAM trong hnh 3, gi s mt nh dng y v ct x trn, do dng 2 bt u
vi a ch 64, 2 nh cng 1 ct trn 2 dng s cch nhau 64 v tr (64*(y-1)).
Mt khc do v tr nh c tnh t 0 trong khi chng ta mun gn ta x bt
u t 1, v th chng ta cn thm (x-1) vo cng thc tnh. Cui cng chng ta
cn phi thm m lnh set a ch DDRAM, m 0x80. Gi tr cui cng ca m
lnh l : Ad=64*(y-1)+(x-1)+0x80 (dng 13). Cc dng lnh tip theo trong hm
move_LCD thc hin ghi gi tr m lnh vo LCD.
Cui cng l phn code hin th LCD c trnh by trong list 8. Phn hin th
bao gm 1 chng trnh con: xa LCd, hin th 1 k t v hin th 1 chui cc k
t.
List 8. Hin th trn LCD.
01 void clr_LCD(){ //xa ton b LCD
02
cbi(CTRL,RS); //RS=0 mean the following data is COMMAND (not normal DATA)
03
#ifdef LCD8BIT
04
Write8Bit(0x01);
05
wait_LCD();
06
#else
07
Write2Nib(0x01);
08
wait_LCD();
09
#endif
10 }
11 void putChar_LCD(uint8_t chr){ //hin th 1 k t chr ln LCD
12
sbi(CTRL,RS); //this is a normal DATA
13
#ifdef LCD8BIT
14
Write8Bit(chr);
15
wait_LCD();
16
#else
17
Write2Nib(chr);
18
wait_LCD();
19
#endif
20 }
21 void print_LCD(char* str, unsigned char len){ //Hin th 1 chui k t
22
unsigned char i;
23
for (i=0; i<len; i++)
24
if(str[i] > 0) putChar_LCD(str[i]);
25
else putChar_LCD(' ');
26
}
27 }
xa ton b LCD chng ta cn gi 1 instruction c m 0x01 n LCD,
hm clr_LCD() thc hin vic ny. Lu m lnh xa LCD l 1 instruction, v
th cn xa chn RS xung 0 trc khi gi m ny xung LCD (dng 2 xa chn
RS). Hm putChar_LCD(uint8_t chr) hin th 1 k t ln LCD, gi tr tham s
ca hm ny l m ASCII ca k t cn hin th, chr. Ni dung ca hm hon ton
ging hm xa LCD, ch khc y khng phi l 1 instruction nn cn set chn RS
ln 1 trc khi gi m lnh n LCD (dng 12). M lnh cho hm ny chnh l m

ASCII cn hin th. Cui cng hm print_LCD(char* str, unsigned char len) cho
php hin th 1 chui k t lin tip ln LCD, thc cht y l qu trnh lp ca
hm hin th 1 k t. Ch tham s len l chiu di cn hin th ca chui.
IV. V d iu khin Text LCD bng th vin myLCD.
Phn ny ti s minh ha cch s dng th vin myLCD.h hin th cc k
t ln 1 Text LCD. S dng phn mm Proteus v mt mch in gm 1 LCD
2x16 (keyword: LM016L), 1 chip Atmega32 v 1 bin tr (POT-LIN) nh trong
hnh 8. To 1 Project bng WinAVR c tn l TextLCD_Demo v to file source l
main.c, to makefile vi khai bo s dng chip ATmega32 v clock 8MHz. Copy
file myLCD.h vo th mc ca Project mi to. Vit code cho file main.c nh
trong list 9. Ch cc nh ngha chn kt ni vi LCD trong phn u file
myLCD.h phi ging vi kt ni tht trong hnh 8.
Hnh 8. Mch in m phng LCD vi AVR.

List 8. Chng trnh demo iu khin TextLCD, main.c.
#include <avr/io.h>
#include <util/delay.h>
#include "myLCD.h" //include th vin myLCD
int main(){
init_LCD(); //khi LCD
clr_LCD(); // xa to b LCD
putChar_LCD(' '); //ghi 1 khong trng
putChar_LCD(' '); //ghi 1 khong trng
putChar_LCD('D'); //Hin th kt 'D'
print_LCD("emo of the",10); //hin th 1 chui k t
move_LCD(2,1); //di chuyn cursor n dng 2, ct u tin
print_LCD("2x16 LCD Display",16); //hin th chui th 2
while(1){
};
}
s dng th vin myLCD, chng ta cn include file myLCD.h vo Project
nh trong dng 3, #include"myLCD.h". Hai dng 6 v 7 thc hin khi ng v
xa LCD. Sau , cc dng 9, 10 v 11 t 3 k t l cc khong trng v ch ci
D bng hm putChat_LCD. Dng 12 in chui emo of the ngay tip theo ch ci
D trc bng hm print_LCD. Dng 13 thc hin di chuyn cursor n v tr
dng th 2, ct u tin ca LCD trc khi tin hnh in chui th 2 2x16 LCD
Display dng code 14. Nu bn thc hin ng trnh t nh trn, kt qu thu
c s nh trong hnh 8.
Graphic LCD
5
( 23 Votes )
Ni dung
Cc bi cn tham kho t
1.
Bn s i n u.
Cu trc AVR
2.
Graphic LCD.
WinAVR
3.
AVR v Graphic LCD.
C cho AVR.
4.
V d iu khin Graphic LCD bng th vin myGLCD.
M phng vi Prote
Download v d
Download phn mm G.Edit
Gii thiu phn mm
I. Bn s i n u.
Trong bi ng dng ny ti trnh by v cu trc v cch iu khin Graphic
LCD loi dot khng mu. Cng c chnh cng l 2 b phn mm quen thuc
WinAVR, Proteus v phn mm bin tp Graphic LCD, G.Edit.
- Cu trc Graphic LCD 128x64 v chip iu khin KS0108.
- Nguyn l hot ng Graphic LCD.
- Pht trin 1 th vin iu khin Graphic LCD 128x64 cho AVR.
- V d iu khin Graphic LCD 128x64 bng AVR.
II. Graphic LCD.
Graphic LCD (gi tt l GLCD) loi chm khng mu l cc loi mn hnh tinh
th lng nh dng hin th ch, s hoc hnh nh. Khc vi Text LCD, GLCD
khng c chia thnh cc hin th cc m ASCII v GLCD khng c b nh
CGRAM (Character Generation RAM). GLCD 128x64 c 128 ct v 64 hng
tng ng c 128x64=8192 chm (dot). Mi chm tng ng vi 1 bit d liu, v
nh th cn 8192 bits hay 1024 bytes RAM cha d liu hin th y mi
128x64 GLCD. Ty theo loi chip iu khin, nguyn l hot ng ca GLCD c
th khc nhau, trong bi ny ti gii thiu loi GLCD c iu khin bi chip
KS0108 ca Samsung, c th ni GLCD vi KS0108 l ph bin nht trong cc
loi GLCD loi ny (chm, khng mu). Hnh 1 l hnh nh tht ca 1 GLCD
128x64 iu khin bi KS0108.
Hnh 1. Graphic LCD 128x64.

Chip KS0108 ch c 512 bytes RAM (4096 bits = 64x64) v v th ch iu
khin hin th c 64 dng x 64 ct. iu khin GLCD 168x64 cn 2 chip
KS0108, v thc th trong cc loi GLCD c 2 chip KS0108, GLCD 128x64 do
tng t 2 GLCD 64x64 ghp li. Chng ta s ln lt kho st s chn, cu
trc b nh v nguyn l hot ng ca GLCD, chip KS0108 trong phn tip theo.
1. S chn GLCD 128x64.
Cc GLCD 128x64 dng KS0108 thng c 20 chn trong ch c 18 chn
l thc s iu khin trc tip GLCD, 2 chn (thng l 2 chn cui 19 v 20) l 2
chn Anode v Cathode ca LED nn. Trong 18 chn cn li, c 4 chn cung cp
ngun v 14 chn iu khin+d liu. Khc vi cc Text LCD HD44780U, GLCD
KS0108 khng h tr ch giao tip 4 bit, do bn cn dnh ra 14 chn iu
khin 1 GLCD 128x64. S chn ph bin ca GLCD 128x64 c m t trong
bng 1.
Bng 1. S chn GLCD GDM-12864-04.
Ch l trn mt s GLCD, th t cc chn c th khc (nh GLCD

WG12864A2) nhng s lng v chc nng chn th khng i. Hnh 2 m t
cch kt ni GLCD vi ngun v mch iu khin.
Hnh 2. Kt ni GLCD.
Chn VSS c ni trc tip vi GND, chn VDD ni vi ngun +5V, mt
bin tr khong 20K c dng chia in p gia Vdd v Vee cho chn Vo,
bng cch thay i gi tr bin tr chng ta c th iu chnh tng phn ca
GLCD. Cc chn iu khin RS, R/W, EN v cc ng d liu c ni trc tip
vi vi iu khin. Ring chn Reset (RST) c th ni trc tip vi ngun 5V.
EN (Enable): cho php mt qu trnh bt u, bnh thng chn EN c gi
mc thp, khi mt thc hin mt qu trnh no (c hoc ghi GLCD), cc
chn iu khin khc s c ci t sn sng, sau kch chn EN ln mc cao.
Khi EN c ko ln cao, GLCD bt u lm thc hin qu trnh c yu cu,
chng ta cn ch mt khong thi gian ngn cho GLCD c hoc gi d liu. Cui
cng l ko EN xung mc thp kt thc qu trnh v cng chun b chn EN
cho qu trnh sau ny.
RS (Register Select): l chn la chn gia d liu (Data) v lnh
(Instruction), v th m trong mt s ti liu bn c th thy chn RS c gi l
chn DI (Data/Instruction Select). Chn RS=1 bo rng tn hiu trn cc ng
DATA (D0:7) l d liu ghi hoc c t RAM ca GLCD. Khi RS=0, tn hiu trn
ng DATA l mt m lnh (Instruction).
RW (Read/Write Select): chn la gia vic c v ghi. Khi RW=1, chiu

truy cp t GLCD ra ngoi (GLCD->AVR). RW=0 cho php ghi vo GLCD. Giao
tip vi GLCD ch yu l qu trnh ghi (AVR ->GLCD), ch duy nht trng hp
c d liu t GLCD l c bit BUSY v c d liu t RAM. c bit BUSY th
chng ta kho st cho Text LCD, bit ny bo GLCD c ang bn hay khng,
vic c ny s c dng vit hm wait_GLCD. c d liu t RAM ca
GLCD l mt kh nng mi m Text LCD khng c, bng vic c ngc t
GLCD vo AVR, chng ta c th thc hin nhiu php logic hnh (hay mt n,
mask) lm cho vic hin th GLCD thm th v.
CS2 v CS1 (Chip Select): nh ti trnh by trong phn trn, mi chip
KS0108 ch c kh nng iu khin mt GLCD c kch thc 64x64, trn cc
GLCD 128x64 c 2 chip KS0108 lm vic cng nhau, mi chip m nhim mt
na LCD, 2 chn CS2 v CS1 cho php chn mt chip KS0108 lm vic. Thng
thng nu CS2=0, CS1=1 th na tri c kch hot, ngc li khi CS2=1,
CS1=0 th na phi c chn. Chng ta s hiu r hn cch phi hp lm vic
ca 2 na GLCD trong phn kho st b nh ca LCD.
2. T chc b nh.
Chip KS0108 c mt loi b nh duy nht l RAM, khng c b nh cha
b font hay cha m font t to nh chip HD44780U ca Text LCD. V vy, d
liu ghi vo RAM s c hin th trc tip trn GLCD. Mi chip KS0108 c 512
bytes RAM tng ng vi 4096 chm trn mt na (64x64) LCD. RAM ca
KS0108 khng cho php truy cp tng bit m theo tng byte, iu ny c ngha l
mi ln chng ta vit mt gi tr vo mt byte no trn RAM ca GLCD, s c
8 chm b tc ng, 8 chm ny nm trn cng 1 ct. V l do ny, 64 dng GLCD
thng c chia thnh 8 pages, mi page c cao 8 bit v rng 128 ct (c 2
chip gp li). Hnh 3 m t b mt mt GLCD v cng l cch sp xp RAM ca
cc chip KS0108.
Hnh 3. T chc ca RAM.

T chc RAM ca 2 chip KS0108 tri v phi hon ton tng t, vic c hay
ghi vo RAM ca 2 chip cng c thc hin nh nhau. Chng ta s chn na tri
GLCD kho st. Nh bn thy trn hnh 3, 64 dng t trn xung di c
chia thnh 8 dy m ta gi l 8 pages. Page trn cng l page 0 v page di
cng la page 7. Trong cc GLCD, page cn c gi l a ch X (X address), hay
ni cch khc X=0 l a ch ca page trn cng, tng t nh th, X=7 l a ch
ca page di cng. Mi page cha 64 ct (ch xt 1 chip KS0108), mi ct l mt
byte RAM 8 bit, mi bit tng ng vi 1 chm trn LCD, bit c trng s thp
(LBS - tc bit D0 nh trong hnh 3) tng ng vi chm trn cao nht. Bit c trng
s cao nht (MBS - tc bit D7 nh trong hnh 3) tng ng vi chm thp nht
trong 1 page. Th t cc ct trong 1 page gi l a ch Y (Y address), nh th ct
u tin c a ch Y = 0 trong khi ct cui cng c a ch Y l 63. Bng cch phi
hp a ch X v a ch Y chng ta xc nh c v tr ca byte cn c hoc ghi.
Chip KS0108, tt nhin, s h tr cc lnh di chuyn n a ch X v Y ghi hay
c RAM. Hy quan st hnh 4 xem cch m mt ch ci a c hin th trn
GLCD.
Hnh 4. Hin th ch ci a trn GLCD.

Trong cch hin th hnh 4, ch a ch nm trong page 0, tc X=0. Mun hin
th ch ci a chng ta cn ghi vo cc ct (a ch Y) ca page 0 ln lt cc gi
tr nh sau: 0, 228, 146, 74, 252 v 128., xem bng bn di.
3. Tp lnh cho chip KS0108.

Bng 2 tm tt cc lnh ca chip KS0108.
So vi HD44780U ca Text LCD, lnh cho KS0108 ca GLCD n gin v t

hn v v th vit chng trnh iu khin GLCD cng tng i d hn Text
LCD. C tt c 7 lnh (Instruction) c th giao tip vi KS0108. Ti s ln lt
gii thch ngha v cch s dng ca tng lnh.
- Display ON/OFF Hin th GLCD: lnh ny cho php GLCD hin th ni
dung trn RAM ra b mt GLCD. vit lnh ny cho GLCD, 2 chn RS v
RW cn c ko xung mc thp (RS=0: y l Instrucion, RW=0: AVR>GLCD). M lnh (code) c cha trong 7 bit cao (D7:1) v bit D0 cha thng
s. Quan st bng 2, d thy m lnh nh phn cho Display ON/OFF l 0011111x
(0x3E+x) trong x=1: cho php GLCD hin th, x=0: tt hin th.
- Set Address chn a ch: ng hn y l lnh chn ct hay chn a ch
Y. Hai bit D7 v D6 cha m lnh (01000000=0x40=64) v 6 bit cn li cha ch
s ca ct mun di chuyn n. Ch l mi na GLCD c 64 ct nn cn 6 bit
cha ch s ny (26=64). Vy lnh ny c dng 0x40+Y. V d nu chng ta mun
di chuyn n ct 36 chng ta ghi vo GLCD m lnh: 0x40+36. Hai chn RS v
RW c gi mc thp khi thc hin lnh ny.
- Set Page chn trang: lnh cho php chn page (hay a ch X) cn di
chuyn n, do GLCD ch c 8 pages nn ch cn 3 bit cha a ch page. M
lnh cho lnh ny c dng 0xB8+X. Trong bin X l ch s page cn di chuyn
n. Hai chn RS v RW c gi mc thp khi thc hin lnh ny.
- Display Start Line chn line u tin: hay cn gi l lnh cun, lnh ny
cho php di chuyn ton b hnh nh trn GLCD (hay RAM) ln pha trn mt s
dng no , chng ta gi l LOffset. S lng LOffset c th t 0 n 63 nn cn
6 bit cha gi tr ny. M lnh Display Start Line c dng 0xC0+LOffset. Hai chn
RS v RW c gi mc thp khi thc hin lnh ny. Khi di chuyn GLCD ln
pha trn, phn d liu pha trn b che khut s cun xung pha di. Hnh 5 l
mt v d cun GLCD ln 20 dng.
- Status Read c trng thi GLCD: y l mt trong 2 lnh c t GLCD.

Cng ging nh vi Text LCD, lnh c trng thi GLCD ch yu xt bit
BUSY (bit th 7) xem GLCD c ang bn hay khng, lnh ny s c dng
vit mt hm wait_GLCD ch cho n khi GLCD rnh. V y l lnh c t
GLCD nn chn RW phi c set ln mc 1 trc khi thc hin, chn RS vn
mc thp (c Instruction).
- Write Display Data ghi d liu cn hin th vo GLCD hay RAM: v y
l 1 lnh ghi d liu hin th nn chn RS cn c set ln 1 trc khi thc hin,
chn RW gi mc 0. Lnh ny cho php ghi mt byte d liu vo RAM ca
KS0108 v cng l d liu s hin th ln GLCD ti v tr hin hnh ca 2 con tr
a ch X v Y. 8 bit d liu ny s tng ng vi 8 chm trn ct Y page X. Ch
l sau lnh Write Display Data, a ch ct Y t ng c tng ln 1 v v th
nu c mt d liu mi c ghi, d liu mi s khng ln d liu c. Vic
tng t ng a ch Y rt c li cho vic ghi d liu lin tip, n gip gim thi
gian set li a ch ct Y. Sau khi thc hin ghi ct Y=63 (ct cui cng trong 1
page, i vi 1 chip KS0108), Ys v 0.
- Read Display Data c d liu hin th t GLCD (cng l d liu t RAM
ca KS0108): lnh c ny mi so vi Text LCD, n cho php chng ta c ngc
1 byte d liu t RAM ca KS0108 ti v tr hin hnh v AVR. Sau khi c
c gi tr ti v tr hin hnh, chng ta c th thc hin cc php Logic nh o
bit, or hay andlm tng kh nng thao tc hnh nh. Trc khi thc hin c
chng ta cn di chuyn n v tr mun c bng 2 lnh set a ch X v Y, sau khi
c gi tr a ch page X v ct Y khng thay i, do nu c tip m khng di
chuyn a ch th vn thu c gi tr c.
III. AVR v Graphic LCD.
1. Trnh t giao tip GLCD.
So vi Text LCD th vic giao tip vi GLCD d hn nhiu v GLCD c t
Instruction hn, GLCD ch c mt loi b nh l RAM tng ng trc tip vi
mn hnh hin th, GLCD khng c cursor nn khng cn set cursor, GLCD ch h
tr giao tip 8 bit nn khng cn bn tm chn mode, qu trnh khi ng cho
GLCD v th rt n gin bng cch gi lnh DISPLAY ON/OFF. Trong hnh 5 ti
trnh by qu trnh khi ng v s dng GLCD.
Hnh 5. Trnh t giao tip vi GLCD.

Sau khi khi ng GLCD bng hm DISPLAY ON chng ta c th set a ch
X v Y ghi d liu, thm ch c th ghi d liu m khng cn set X, Y. Tuy
nhin, cn nhc li l c n 2 chip KS0108 trn GLCD 128x64, v vy tt c cc
qu trnh u phi thc hin cho 2 chip.
2. AVR giao tip vi GLCD trong WinAVR.

Phn ny ti trnh by cch iu khin hin th GLCD 128x64 bng vi iu
khin AVR trong mi trng C ca WinAVR. Hnh thc l mt th vin hm giao
tip GLCD trong 1 file header c tn l myGLCD.h. Cc hm trong th vin bao
gm (ch l phn code trong List 0 khng nm trong file myGLCD.h):
List 0. Cc hm c trong th vin myGLCD.
Trc khi vit cc hm giao tip LCD chng ta cn nh ngha mt s macro

v bin. Hy to 1 file Header c tn myGLCD.h v vit cc on code bn di
vo file ny (bt u t List 1).
List 1. nh ngha cc bin thay th
Do GLCD khng h tr b font, nu mun hin th cc k t chng ta cn

nh ngha chng trong mt bng font (tng t trng hp ma trn LED), file
font.h c to trc v include vo th vin myGLCD (dng 2). ng thi, b
font s c cha trong b nh chng trnh (FLASH) nn cn cc hm h tr c
FLASH, chng ta include file pgmspace.h phc v cho vic ny (dng 3).
cbi v sbi l 2 macro c dng xa v set 1 bit trong 1 thanh ghi. V d

cbi(PORTA, 5) l xa bit 5 trong thanh ghi PORTA v 0. Do WinAVR khng h tr
tuy xut trc tip cc bit nn cn nh ngha 2 macro ny h tr (dng 5, 6).
Tm ng DATA s c dnh cho 1 PORT, cc dng 8, 9 v 10 nh ngha
PORT trn AVR dnh cho DATA, trong v d ny l PORTB. Tng t cc ng
iu khin cng nm trn cng 1 PORT, cc dng 14, 15, 16 nh ngha PORT
dnh cho cc ng iu khin (PORTD chng hn), sau chng ta nh ngha
th t chn trn PORT iu khin kt ni vi cc chn EN, RW, RS, CS1 v CS2
ca GLCD (xem cc dng t 18 n 22). Chng ta nh ngha tip 2 macro kch
hot v stop GLCD cc dng 25 v 26 v cc hot ng ny c dng rt nhiu
khi giao tip vi GLCD.
Tip theo chng ta nh ngha 4 m lnh (Instruction code) ca 4 hm Display
on/off, Set Address, Set page v Display Start Line m ti trnh by trn (cc
dng t 29 n 32). Cui cng l nh ngha v tr bit BUSY khi c trng thi
GLCD.
Sau phn nh ngha chng ta s bt u vit code truy cp GLCD, on code
trnh by trong List 2 cha cc hm h tr.
List 2. Cc hm h tr.
Hm GLCD_Delay() thc hin delay khong 16 chu k my, hm ny c

dng ch LGCD c hay ghi d liu sau khi chn EN c kch. Mt nt mi
y l ti s dng ngn ng ASM chn vo C, d ch l chn hm nop nhng n
ni cho bn bit rng avr-gcc cho php chng ta chn ASM, ti s trnh by chi tit
cc v d chn ASM phc tp hn trong mt bi khc.
Hm GLCD_OUT_Set() dng 5 set cc PORT giao tip trn AVR (DATA
v Control) c hng Ouput. Hm GLCD_IN_Set() dng 12 set cc PORT giao
tip c hng Input (dng khi c t GLCD -> AVR). Hm GLCD_SetSide(char
Side) dng 19 chn chip KS0108 tri hoc phi thao tc, trong Side=1 th
mt na GLCD bn phi c chn bng cch reset bit CS1=0 v CS2=1 (cc
dng 22, 23), ngc li na bn tri c kch hot, CS1=1, CS2=0 (dng 26 v
27).
List 3 trnh by phn code cho 4 hm truy cp Instruction GLCD c bn vit
li cho cc hm Status Read, Display On/Off, Set Address, Set page v Display
Start Line trch t bng 2.
List 3. Cc hm truy cp Instruction.
Tt c cc hm trong List 3 u truy cp Instruction nn chn RS lun c

ko xung mc thp, trong 5 hm trn, hm wait_GLCD s dng Instruction c
trng thi t GLCD nn chn RW s c ko ln cao, trong 4 hm cn li chn
RW mc thp.
Hm wait_GLCD(void), cng tng t nh hm wait_LCD() trong trng
hp Text LCD, hm ny ch GLCD rnh bng cch c trng thi GLCD v kim
tra bit BUSY, nu BUSY bng 1 th GLCD ang bn, BUSY=0 tc GLCD rnh.
Cc dng 4, 5, 6 chun b cc ng DATA, RS, RW cho qu trnh c Instruction
t GLCD (RS=0, RW=0), dng 8 chn EN c ko ln cao bng
macro GLCD_ENABLE (nh ngha trong list 1). Nhc li chc nng ca chn
EN, khi EN=1 GLCD bt u qu trnh giao tip do cc chn RS, RW xc lp
(trong trng hp ny l c Instruction t GLCD), chng ta cn ch mt khong
thi gian ngn cho GLCD y thanh ghi trng thi ra cc ng DATA bng hm
GLCD_Delay() trong dng 9. Tip theo gi GLCD_DISABLE ko chn EN
xung mc 0 kt thc qu trnh c (mt xung c to trn chn EN), v
bt u kim tra bit BUSY. Dng 12 l mt vng lp while kim tra xem nu bit
BUSY trong gi tr c v (gi tr c v cha trong thanh ghi PIN ca PORT
DATA trn AVR), nu BUSY=1 (bit_is_set) vng lp tip tc vi vic to mt
xung khc trn chn EN (cc dng ) ri quay li kim tra bit BUSY. Nu BUSY
bng 0, GLCD rnh, vng lp while c gii thot, qu trnh ch kt thc.
Hm GLCD_SetDISPLAY(uint8_t ON) cho php GLCD hin th khi tham s
ON=1, hoc tt khi tham s ON=0. Trc khi set GLCD chng ta cn ch cho
GLCD rnh bng cch gi hm wait_GLCD() dng 20, sau xc lp cc chn
RS, RW sn sng cho qu trnh gi m lnh vo GLCD (dng 21, 22 v 23). Trc
khi kch hot qu trnh, cn chun b m lnh sn sng trn ng d liu, dng
25: GLCD_DATA_O=GLCD_DISPLAY+ON, trong GLCD_DISPLAY l m
lnh ca hm Display On/Off c nh ngha trong List 1, bin ON bo GLCD tt
hay m. Sau khi mi th sn sng, mt xung c to ra trn chn EN (cc
dng t 26 n 28). Qu trnh set Display thc hin v kt thc.
Hm void GLCD_SetYADDRESS(uint8_t Col) l hm vit li cho Insrtuction
chn a ch Y (ct) cn thao tc, tham s Col trong hm ny chnh l ch s ct,
Col c gi tr t 0 n 63. Ni dung hm ny hon ton ging
hmGLCD_SetDISPLAY, ch c mt im khc duy nht l m hm khc, m
GLCD_YADDRESS c dng (xem dng 36: GLCD_DATA_O =
GLCD_YADDRESS+Col).
Hm void GLCD_SetXADDRESS(uint8_t Line) l hm vit li cho
Insrtuction chn a ch X (page) cn thao tc, tham s Line trong hm ny chnh
l ch s page, Line c gi tr t 0 n 8. Ni dung hm ny hon ton ging
hmGLCD_SetXADDRESS, nhng m GLCD_XADDRESS c dng thay cho

GLCD_YADDRESS,(xem dng 36:GLCD_DATA_O =
GLCD_XADDRESS+Line).
Hm void GLCD_StartLine(uint8_t Offset) l hm vit li cho Insrtuction
cun GLCD, ch s Offset l gi tr cun ln. Xem li v d hnh cun GLCD
trong phn gii thch ca lnh Display Start Line, vi trng hp ny hm
GLCD_StartLine(20) c gi.
List 4 trnh by 2 hm vit v c d liu hin th ln GLCD.
List 4. Cc hm thao tc d liu.
Hai hm trong list 4 thao tc d liu hin th trn GLCD nn chn RS phi
c set bng 1.
Hm GLCD_WriteDATA(uint8_t DATA) ghi mt byte vo RAM ca
KS0108, byte ny cng s c hin th ln GLCD, v tr ghi vo l v tr hin hnh
ca con tr X v Y (nh hng bi cc qu trnh ghi trc hoc do cc hm set
a ch), tham s DATA l byte cn ghi. Ni dung bn trong hm ny cng ging
nh cc hm trong list 3. im khc l chn RS c ko ln bo y l qu

trnh thao tc d liu (dng 6: sbi(GLCD_CTRL_O, GLCD_RS)). Gi tr gi n
GLCD chnh l tham s DATA nh trong dng 8: GLCD_DATA_O=DATA.
Hm uint8_t GLCD_ReadDATA(void) c gi tr hin th trn t GLCD vo
AVR, chn RW cn c set ln 1 bo qu trnh ny l c (dng
22: sbi(GLCD_CTRL_O, GLCD_RW)). Chn EN c kch ln 1 trc (dng
24:GLCD_ENABLE;) v ch mt khong thi gian ngn trc khi c gi tr t
cc ng DATA vo mt bin tm DATA nh trong dng
26: DATA=GLCD_DATA_I;. Sau khi tr gi tr v bng dng lnh 30: return
DATA, th qu trnh c kt thc.
Vi cc hm to chng ta c th iu khin hin th GLCD, cc
chng trnh con trong List 5 v List 6 s dng cc hm trn thc hin mt s
nhim v hin th c bn. Chng ta gi l cc chng trnh con m rng.
List 5. Cc chng trnh con m rng.
Hm void GLCD_Init(void) khi ng GLCD. Trc ht, chng ta phi chn

chip KS0108 khi ng, dng 4: GLCD_SetSide(0) ngha l chn chip KS0108
bn tri tc na tri GLCD. Chng ta khi ng na tri GLCD bng vic cho
php hin th (dng 5: GLCD_SetDISPLAY(1)), di chuyn con tr v v tr u
tin trn GLCD vi 2 hm chn a ch cc dng 6 v 7, chn gi tr cun l 0
dng 8: GLCD_StartLine(0). Sau lp li qu trnh khi ng cho na phi ca

GLCD (xem cc dng t 10 n 14).
Hm void GLCD_GotoXY(uint8_t Line, uint8_t Col) di chuyn con tr hin
th n a ch X v Y. Tham s Line l a ch X (tc l page, gi tr t 0 n 7),
tham s Col l a ch Y hay chnh l ct. Hm ny cho php di chuyn trn ton
b GLCD, ngha l bin Col c khong gi tr t 0 n 127, v th trc ht chng
ta phi xc nh v tr cn duy chuyn n thuc na no ca GLCD, nu Col<64
th v tr thuc na tri, ngc li n thuc v na phi. Dng 19 chng ta chia
Col cho 64 v gn phn nguyn kt qu cho 1 bin tm tn l Side (Side=Col/64 ),
r rng nu Col<64 th Side=0, ngc li Side=1. Bin Side c dng lm tham
s cho hm GLCD_SetSide(Side) dng 20, vi cch thc hin ny chng ta t
ng chn na GLCD m im cn di chuyn n thuc vo. Do hm chn a ch
Y (hm GLCD_SetYADDRESS xt trn) ch chn a ch trong phm vi 1 na
LCD, nn chng ta cn cp nht li gi tr ca ct Col, dng 21 thc hin vic ny:
Col -= 64*Side. Sau dng 21, gi tr Col c cp nht li t 0 n 63 v c
chn lm ct khi hm GLCD_SetYADDRESS(Col) dng 22 c gi. Cui
cng l chn a ch X dng 23:GLCD_SetXADDRESS(Line).
Hm void GLCD_Clr(void) xa ton b mn hnh GLCD (c 2 na GLCD).
Mu cht ca vic xa GLCD l vit gi tr 0 vo tt c cc v tr trong RAM, cu
lnh: GLCD_WriteDATA(0) 2 dng 29 v 33 thc hin iu ny. Qu trnh xa
c thc hin trn tng chip KS0108, c 2 vng vp for c dng l v th, ch
dng lnh 28:GLCD_GotoXY(Line,0) a con tr v ct u ca page th
Line, na tri GLCD. Trong khi , dng lnh
32:GLCD_GotoXY(Line,64) a con tr v ct u ca page th Line, na
phi GLCD (ct 64 ca GLCD l ct u tin ca na bn phi).
List 6. Cc chng trnh con m rng (tt)..
y l 3 chng trnh con cui cng trong th vin myGLCD. Trong c 2

hm in cc k c kch thc 7x8 (7 ct, 8 dng) c nh ngha trong bng font
v 1 hm in ton b mn hnh GLCD vi mt hnh kch thc 128x64.
Hm void GLCD_PutChar78(uint8_t Line, uint8_t Col, uint8_t chr) cho
php in k t c m ascii l bin chr, bin Line l a ch X (0 n 7) v bin
Col l a ch ct Y (0 n 127). Phn phc tp nht trong chng trnh con ny l
vic xt trng hp c s chuyn bn (tri qua phi) khi in. V mi k t c nh
ngha bng 7 bytes trong bng font, tng ng vi 7 ct trn GLCD, nu chng ta
mun in k t ti v tr 60 trn GLCD, cc byte th 0 1, 2, 3 nm v tr ct 60, 61,
62 v 63 ca na tri trong khi cc byte th 4, 5 v 6 li nm cc ct 0, 1 v 2
ca na bn phi. Chng ta phi nhn ra s chuyn bn ny chuyn chip
KS0108 cn thao tc. Chng ta chia qu trnh in ra 2 trng hp, trng hp c s
chuyn bn v trng hp cn li khng chuyn bn (k t nm trn bn tri hoc
phi). Cu trc If dng trong dng 4 kim tra xem c s chuyn bn xy ra hay
khng: if ((Col>57) && (Col<64)), nu ct Col ln hn 57 v nh hn 63 th s
c mt s chuyn bn xy ra (v 1 k t chim 7 ct trn GLCD). Chia qu trnh in
thnh 2 vng lp for, vng for th nht (dng 6) in t v tr Col n v tr ct ca
na tri v vng lp for th 2 dng 9 in t ct u tin ca na GLCD bn phi
n byte cui cng ca k t cn in. Trng hp ngc li, khng c s chuyn
bn xy ra, chng ta in bnh thng (xem cc dng t 12 n 15). Ch l d liu
ghi vo GLCD ly t bng font7x8 c nh ngha trong file font.h, bng font
c vit sn trong b nh FLASH ca AVR, vic c ni dung FLASH thc hin
bng hm pgm_read_byte, bn xem li bi iu khin ma trn LED hiu thm.
Hm void GLCD_Print78(uint8_t Line, uint8_t Col, char* str) cho php in
mt chui k t hay 1 cu ln GLCD, hm ny cng ging hm in chui m chng
ta thc hin trong trng hp ca Text LCD (modified code), mt im khc ti
thm vo l cho phep xung dng nu cu cn in vt qu 1 dng. Cc cu lnh
bn trong iu kin if (dng 23 n 27) thc hin xung dng nu cn thit. Qu
trnh in sau din ra bnh thng bng cch gi hmGLCD_PutChar78.
Cui cng l hm void GLCD_PutBMP(char *bmp) thc hin in mt hnh
c kch thc 128x64 c nh ngha trc ln ton b mn hnh GLCD (in ).
Qu trnh in cng kh n gin vi vic c ni dung hnh trong FLASH v gi
n GLCD. Cn chia thnh 2 qu trnh in cho 2 na tri v phi (2 vng lp for
trong 2 dng 38 v 43). D liu hnh c ghi trong FLASH c nh kch thc
128x8 pages= 1024 bytes, nh dng l 1 mng c 1024 phn t, mi phn t l 1
con s dng byte, mi s tng ng 8 chm ca 1 ct trong 1 page. Cc con s
c sp xp thnh 8 dng tng ng 8 pages, mi dng c 128 phn t tng ng
128 ct GLCD.
GLCD c kh nng ty bin hin th cao, l c hi cho bn th hin s sng

to ~, trong th vin myGLCD ti ch trnh by mt s chng trnh con c bn,
phn cn li thuc v bn. Hy s dng cc hm truy xut trong myGLCD vit
cc chng trnh con hin th khc nh v ng thng, ng trn, hm sine,
cosine hay bt k hm s noHope to hear from you soon.
IV. V d iu khin Graphic LCD bng th vin myGLCD.
Phn ny ti s minh ha cch s dng th vin myGLCD.h in trc tip d
liu ln GLCD, hin th cc k t trong bng font7x8 v hnh nh ln GLCD. S
dng phn mm Proteus v mt mch in gm 1 GLCD 128x64 (keyword:
LGM12641BS1R), 1 chip Atmega32 v 1 bin tr (keyword: POT-LIN) nh trong
hnh 6. To 1 Project bng WinAVR c tn l myGLCD v to file source l
main.c, to Makefile vi khai bo s dng chip ATmega32 v clock 8MHz. Copy
file myGLCD.h v font.h vo th mc ca Project mi to. Vit code cho file
main.c nh trong list 7. Ch cc nh ngha chn kt ni vi LCD trong phn u
file myGLCD.h phi ging vi kt ni tht trong hnh 6.
Hnh 6. Mch in m phng Graphic LCD vi AVR.

List 7. Chng trnh demo giao tip GLCD.
s dng th vin myGLCD, chng ta cn include file myGLCD.h vo

Project nh trong dng 4, #include "myGLCD.h". Hai dng 9 v 10 thc hin khi
ng v xa LCD. Ti thc hin 4 demo in ln GLCD. Trong cc dng t 12 n
17 thc hin ghi trc tip gi tr ln GLCD bng hm GLCD_WriteDATA, kt
qu l 1 dy cc chm c rng 8 bit nm page 4 ca GLCD (xem hnh bn
di). Ch l in ht c chiu ngang ca GLCD cn thc hin 2 ln in trn 2
na GLCD.
Cc dng lnh t 21 n 27 thc hin in 97 k t trong bng font7x8 bt u

bng m ascii 33 (k t !), bin Line l a ch page c khi to bng 0 khi
khai bo trong dng 7. Bin Col l a ch ct, Col cng c khi to bng 0.
Dng 32 in k t c m i ln GLCD ti v tr page=Line, ct=Col. Sau khi mt
k t c in, Col s c tng ln 8 v tr (dng 24), chng ta dnh 8 ct trn
GLCD cho mt k t 7x8 trnh cc k t dnh vi nhau. Nu Col ln hn 127
th mt qu trnh xung dng cn thc hin, khi reset Col v 0 v tng bin Line
thm 1 (dng 25). Cc k t s c in ln lt trn GLCD vi 1 khong delay.
Cc dng t 31 n 35 m t cch dng hm GLCD_Print78 in cc chui k
t hay cc cu. Dng 23 in t code ln GLCD ti v tr page=4, ct=20. Ch
hm sprintf trong dng 33, y l mt hm ca ngn ng C, hm ny cho php
chuyn mt s thnh mt chui cc k t, trong v d ny ti thc hin chuyn s
8205 thnh chui 8205, kt qu cha trong bin dis, bin ny l 1 mng cc k
t hay con tr n mng cc k t. Sau , dng 34 in chui dis ln GLCD.
Demo cui cng l in 1 hnh 128x64 ln GLCD bng
hm GLCD_PutBMP(hiGLCD) v sau thc hin animation (mt kiu hot
hnh) bng hm GLCD_StartLine. Dng 38 in mt hnh c tn hiGLCD c nh
ngha trc trong file font.h ra GLCD. Cc dng 40 n 44 cun mn hnh GLCD
ln trn thc hin animation. Bin i l bin offset c cho chy t 1 n 63,
sau mi ln cun chng ta delay mt khong thi gian ngn thy GLCD cun.
Hy tham kho thm bi gii thiu phn mm G.Edit bit cch to code hnh
nh cho Graphic LCD.
iu khin ng c DC servo (PID)
5
( 159 Votes )
Ni dung
1.
Gii thiu
2.
Incremental Optical Encoder
Cu trc AVR.
3.
Chip driver L298D
WinAVR.
4.
Mch logic cho L298D
C cho AVR.
5.
Gii thut iu khin PID
M phng vi Proteus.
6.
iu khin DC Motor bng AVR
Download v d
I. Gii thiu
iu khin ng c DC (DC Motor) l mt ng dng thuc dng c bn nht
ca iu khin t ng v DC Motor l c cu chp hnh (actuator) c dng
nhiu nht trong cc h thng t ng (v d robot). iu khin c DC Motor l
bn c th t xy dng c cho mnh rt nhiu h thng t ng. Khi nim
Servo m ti dng trong bi hc ny ch mt h thng hi tip. DC servo motor
l ng c DC c b iu khin hi tip.
Bi ny l mt bi tng hp nhiu vn ng dng AVR bao gm nhn d liu
t ngi dng, iu khin motor, c encoder, hin th LCD, c gii thut iu

khin PID v mch cng sut cho MotorDo , t nht bn phi nm c cc
vn c bn nh Timer-Counter, TexLCD, mch cu H. Phn cn li ti s gii
thch trong lc hc bi ny. C 2 phng php iu khin ng c DC l analog v
digital. Mc ch chnh ca chng ta l dng AVR iu khin ng c DC nn
phng php s m c th l phng php iu rng xung (PWM) s c gii
thiu. Ngoi ra, khi ni n iu khin ng c DC c 2 i lng iu khin
chnh l v tr (s vng quay) v vn tc. Trong phn gii thch v b iu khin
PID ti s iu khin v tr lm v d, tuy nhin trong phn v d lp trnh cho AVR
chng ta s thc hin iu khin vn tc cho DC Motor. Bng cch ny, bn c th
t tin m rng v d iu khin cho c 2 i lng. V l iu khin mt cch
t ng nn chng ta cn c v i lng iu khin (c th l v tr hoc vn tc
motor) v hi tip (feedback) v hiu chnh PWM cp cho ng c. Chng ta
s dng incremental optical encoder c s vng quay v hi tip v cho AVR.
B iu khin PID s c dng v vn hnh bi AVR. Tng qut, bi hc ny bao
gm:
- AVR pht PWM iu chnh vn tc ng c: phn ny bn xem li bi 4 v
Timer-Counter. iu c bn cn nm l bng cch thay i rng ca xung
PWM chng ta s thay i c vn tc Motor.
- Xung PWM khng trc tip lm quay ng c m thng qua mt mch cng
sut gi l dirver. Driver cho DC Motor chnh l mch cu H m chng ta tm
hiu trong bi Mch cu H. Trong bi hc ny, ti gii thiu mt chip c tch hp
sn mch cu H, chip L298D.
- vic iu khin chip driver L298D d dng, chng ta s to mt mch
logic dng cc cng NOT v AND.
- ng c DC m chng ta s dng c tch hp sn mt encoder 3 ng ra,
chng ta s dng AVR c s xung (hay s vng quay) v tnh ra vn tc ca
Motor. Vic c encoder s c thc hin bng ngt ngoi.
- Mt gii thut PID c xy dng trong AVR hiu chnh vn tc ng c.
- Ngi dng s nhp vn tc cn iu khin vo AVR thng qua cc switches.
Vn tc mong mun v vn tc thc ca ng c c hin th trn Text LCD.
Mch in v d c trnh by trong hnh 1.
Hnh 1. H thng iu khin ng c DC servo.

Trong mch in hnh 1, ti chia h thng thnh 3 nhm: nhm CONTROL bao
gm AVR vn hnh gii thut iu khin PID v vic nhp, xut. Nhm LOGIC
thc hin vic bin i cc tn hiu iu khin to ra cc tn hiu ph hp cho
chip driver. Nhm POWER bao gm chip driver L298D v DC Motor. Ngoi ra
cn c mt Encoder c tch hp sn trn DC Motor.
Phn tip theo chng ta s tm hiu ring tng nhm, cui cng l vit chng
trnh cho AVR iu khin h thng DC Servo Motor
II. Incremental Optical Encoder
iu khin s vng quay hay vn tc ng c th chng ta nht thit phi
c c gc quay ca motor. Mt s phng php c th c dng xc nh
gc quay ca motor bao gm tachometer (tht ra tachometer o vn tc quay),
dng bin tr xoay, hoc dng encoder. Trong 2 phng php u tin l
phng php analog v dng optiacal encoder (encoder quang) thuc nhm
phng php digital. H thng optical encoder bao gm mt ngun pht quang
(thng l hng ngoi infrared), mt cm bin quang v mt a c chia rnh.
Optical encoder li c chia thnh 2 loi: encoder tuyt i (absolute optical
encoder) v encoder tng i (incremental optical encoder). Trong a s cc DC
Motor, incremental optical encoder c dng v m hnh ng c servo trong bi
ny cng khng ngoi l. T by gi khi ti ni encoder tc l incremental
encoder. Hnh 2 l m hnh ca encoder loi ny.
Hnh 2. Optical Encoder (trch t [1]).
Encoder thng c 3 knh (3 ng ra) bao gm knh A, knh B v knh I

(Index). Trong hnh 2 bn thy hy ch mt l nh bn pha trong ca a quay
v mt cp phat-thu dnh ring cho l nh ny. l knh I ca encoder. C mi
ln motor quay c mt vng, l nh xut hin ti v tr ca cp pht-thu, hng
ngoi t ngun pht s xuyn qua l nh n cm bin quang, mt tn hiu xut
hin trn cm bin. Nh th knh I xut hin mt xung mi vng quay ca
motor. Bn ngoi a quay c chia thnh cc rnh nh v mt cp thu-pht khc
dnh cho cc rnh ny. y l knh A ca encoder, hot ng ca knh A cng
tng t knh I, im khc nhau l trong 1 vng quay ca motor, c N xung xut
hin trn knh A. N l s rnh trn a v c gi l phn gii (resolution) ca
encoder. Mi loi encoder c phn gii khc nhau, c khi trn mi a ch c vi
rnh nhng cng c trng hp n hng nghn rnh c chia. iu khin
ng c, bn phi bit phn gii ca encoder ang dng. phn gii nh
hng n chnh xc iu khin v c phng php iu khin. Khng c v
trong hnh 2, tuy nhin trn cc encoder cn c mt cp thu pht khc c t
trn cng ng trn vi knh A nhng lch mt cht (lch M+0,5 rnh), y l
knh B ca encoder. Tn hiu xung t knh B c cng tn s vi knh A nhng
lch pha 90o. Bng cch phi hp knh A v B ngi c s bit chiu quay ca
ng c. Hy quan st hnh 3.
Hnh 3. Hai knh A v B lch pha trong encoder (trch t [1])
Hnh trn cng trong hnh 3 th hin s b tr ca 2 cm bin knh A v B lch

pha nhau. Khi cm bin A bt u b che th cm bin B hon ton nhn c hng
ngoi xuyn qua, v ngc li. Hnh thp l dng xung ng ra trn 2 knh. Xt
trng hp motor quay cng chiu kim ng h, tn hiu i t tri sang phi.
Bn hy quan st lc tn hiu A chuyn t mc cao xung thp (cnh xung) th
knh B ang mc thp. Ngc li, nu ng c quay ngc chiu kim ng h,
tn hiu i t phi qua tri. Lc ny, ti cnh xung ca knh A th knh B ang
mc cao. Nh vy, bng cch phi hp 2 knh A v B chng ta khng nhng xc
nh c gc quay (thng qua s xung) m cn bit c chiu quay ca ng c
(thng qua mc ca knh B cnh xung ca knh A).
Cu hi by gi l lm th no c encoder bng AVR?
Ty theo i lng iu khin (v tr hay vn tc) v c im encoder (
phn gii) chng ta c cc gii php sau c encoder bng AVR
- Dng input capture: mt s b timer-counter trn AVR c chc nng Input
capture, hiu nm na nh sau. C mi ln c mt tn hiu (cnh ln hoc cnh
xung) trn chn ICP (Input Capture Pin), gi tr thi gian ca timer c t ng
gn cho thanh ghi ICR (Input capture Register). So snh gi tr thanh ghi ICR trong
2 ln lin tip s c c chu k ca tn hiu kch chn ICP. T suy ra tn s
tn hiu. Nu mt knh ca encoder c ni vi chn ICP th chng ta c th o
c tn s tn hiu ca knh ny. Ni cch khc, chng ta s tnh c vn tc
ca ng c. Chng ta c th dng ngt Input capture v khi ngt xy ra, c th
m s thm s xung bit c gc quay motor, cng c th xc nh c
hng quay thng qua xc nh mc knh B trong trnh phc v ngt input
capture. y l mt phng php hay, nhng c nhc im l kh phc tp khi s
dng chc nng input capture ca AVR. Mc khc trn cc chip AVR t mega32
tr xung, Input capture ch c timer 1, trong khi Timer ny thng dng to
PWM iu khin ng c.
- Dng chc nng counter: t cc knh ca encoder vo cc chn m (T0,
T1) ca cc b timer chng ta s m c s lng xung ca cc knh. y l
phng php s dng t ti nguyn nht (t tn thi gian cho encoder). Nhc im
ln nht ca phng php ny l khng xc nh c chiu quay, mc khc
phng php ny khng n nh khi vn tc ng c c s thay i ln.
- Cui cng l s dng ngt ngoi: y l phng php d nhng chnh xc
c encoder v cng l phng php c dng trong bi hc ny. tng ca
phng php rt n gin, chng ta ni knh A ca encoder vi 1 ngt ngoi (INT2
chng hn) v knh B vi mt chn no bt k (khng phi chn ngt). C mi
ln ngt ngoi xy ra, tc c 1 xung xut hin trn knh A th trnh phc v ngt
ngoi t ng c gi. Trong trnh phc v ngt ny chng ta kim tra mc ca
knh B, ty theo mc ca knh B chng ta s tng bin m xung ln 1 hoc gim
i 1. Tuy nhin, bn cn phi tnh ton rt cn thn khi s dng phng php ny.
V d trng hp encoder c phn gii 2000 xung/vng, motor bn quay vi

vn tc 100 vng/s th tn s xung trn knh A ca encode l 2000x100=200KHz,
ngha l c mi 5 us ngt ngoi xy ra mt ln. Tn s ngt nh th l qu cao cho
AVR, iu ny c ngha l AVR ch tp trung cho mi vic m xung, khng c
thi gian thc thi cc vic khc. Trong bi ny, chng ta chn phn gii
ca encoder l 112 (112 xung trn mi vng quay). Vn tc ti a ca ng c
c chn vo khong 30 vng/s nn tn s xung ln nht t encoder l
112x30=3.36KHz. Gi tr ny hp l v tn s cho AVR trong bi ny c chn
8MHz. Knh A ca encoder c ni vi ngt INT2 ca chip atmega32, knh B
c ni vi chn PB0, chng ta khng s dng knh I (xem hnh 1).
Ch : cc ng ra trn a s (gn nh tt c) cc encoder c dng cc gp h
(Open collector), mun s dng chng cn mc in tr ko ln VCC (5V).
III. Chip driver L298D
L298D l mt chip tch hp 2 mch cu H trong gi 15 chn. Tt c cc mch
kch, mch cu u c tch hp sn. L298D c in p danh ngha cao (ln nht
50V) v dng in danh ngha ln hn 2A nn rt thch hp cho cc cc ng dng
cng sut nh nh cc ng c DC loi nh v va. V l loi all in one nn l
la chn hon ho cho nhng ngi cha c nhiu kinh nghim lm mch in t.
Trong bi hc ny ti dng chip L298D lm driver cho motor. Hnh 4 th hin
m hnh tht ca chip v cu trc bn trong chip.
Hnh 4. Chip L298D

Hnh pha trn l hnh dng bn ngoi v tn gi cc chn ca L298D. Hnh
pha di l cu trc bn trong chip. C 2 mch cu H trn mi chip L298D nn c
th iu khin 2 i tng ch vi 1 chip ny. Mi mch cu bao gm 1 ng
ngun Vs (tht ra l ng chung cho 2 mch cu), mt ng current sensing
(cm bin dng), phn cui ca mch cu H khng c ni vi GND m b trng
cho ngi dng ni mt in tr nh gi l sensing resistor. Bng cch o in p
ri trn in tr ny chng ta c th tnh c dng qua in tr, cng l dng qua
ng c (xem hnh 4). Mc ch chnh ca vic o dng in qua ng c l xc
nh cc trng hp nguy him xy ra trong mch, v d qu ti. Nu vic o dng
ng c khng tht s cn thit bn c th ni ng current sensing ny vi GND
(trong mch in ca bi ny, ti ni chn current sensing vi GND). ng c s
c ni vi 2 ng OUT1, OUT2 (hoc OUT3, OUT4 nu dng mch cu bn
phi). Mt chn En (EnA v EnB cho 2 mch cu) cho php mch cu hot ng,
khi chn En c ko ln mc cao, mch cu sn sang hot ng. Cc ng kch
mi bn ca mch cu c kt hp vi nhau v nhng mc in p ngc nhau
do mt cng Logic NOT. Bng cch ny chng ta c th trnh c trng hp 2
transistor cng mt bn c kch cng lc (ngn mch). Nh vy, s c 2 ng
kch cho mi cu H gi l In1 v In2 (hoc In3, In4). motor hot ng chng ta
phi ko 1 trong 2 ng kch ny ln cao trong khi ng kia gi mc thp, v
d In1=1, In2=0. Khi o mc kch ca 2 ng In, ng c s o chiu quay.
Tuy nhin, do L298D khng ch c dng o chiu ng c m cn iu
khin vn tc ng c bng PWM, cc ng In cn c t hp li bng cc
cng Logic (xem phn tip theo). Ngoi ra, trn chip L298D cn c cc ng Vss
cp in p cho phn logic (5V) v GND chung cho c logic v motor.
Trong thc t, cng sut thc m L298D c th ti nh hn so vi gi tr danh
ngha ca n (V=50V, I=2A). tng dng in ti ca chip ln gp i, chng ta
c th ni 2 mch cu H song song vi nhau (cc chn c chc nng nh nhau ca
2 mch cu c ni chung).
II. Mch logic cho L298D
Thng thng, khi thit k mt mch driver cho motor ngi ta thng dnh 3
ng iu khin l PWM dng iu khin vn tc, DIR iu khin hng v
En cho php mch hot ng. Chip L298D c sn ng En nhng 2 ng
iu khin In1 v In2 khng tht s chc nng nh chng ta mong mun. V th,
chng ta s thit k mt mch logic ph vi 2 ng vo l PWM v DIR trong khi 2
ng ra l 2 ng iu khin In1 v In2. Bng chn tr ca mch logic cn thit k
c trnh by trong bng 1.
Bng 1. bng chn tr ca mch logic cho driver L298D.
PW
M
DIR
In1
In2
T bng chn tr ny, chng ta c th vit hm bool cho 2 ng In1 v In2:

In1=PWM.NOT(DIR)
In2=PWM.DIR
Mch logic v th s c dng nh trong hnh 5.
Hnh 5. Mch logic cho L239

Ti s khng gii thch chi tit phn ny, tuy nhin iu bn cn nm l vi
mch logic ny, ng DIR c chc nng o chiu ng c trong khi ng
PWM iu khin vn tc ng c bng tn hiu PWM.
V. Gii thut iu khin PID

PID l cch vit tc ca cc t Propotional (t l), Integral (tch phn) v
Derivative (o hm). Tuy xut hin rt lu nhng n nay PID vn l gii thut
iu khin c dng nhiu nht trong cc ng dng iu khin t ng. gip
bn c ci hiu r hn bn cht ca gii thut PID ti s dng mt v d iu khin
v tr ca mt car (xe) trn ng thng. Gi s bn c mt xe ( chi...) c gn
mt ng c DC. ng c sinh ra mt lc y xe chy ti hoc lui trn mt
ng thng nh trong hnh 6.
Hnh 6. V d iu khin v tr xe trn ng thng

Gi F l lc do ng c to ra iu khin xe. Ban u xe v tr A, nhim v
t ra l iu khin lc F (mt cch t ng) y xe n ng v tr O vi cc
yu cu: chnh xc (accurate), nhanh (fast response), n nh (small overshot).
Mt iu rt t nhin, nu v tr hin ti ca xe rt xa v tr mong mun (im
O), hay ni cch khc sai s(error) ln, chng ta cn tc ng lc F ln nhanh
chng a xe v O. Mt cch n gin cng thc ha tng ny l dng quan
h tuyn tnh:
F=Kp*e
(1)
Trong Kp l mt hng s dng no m chng ta gi l h s P
(Propotional gain), e l sai s cn iu khin tc khong cch t im O n v tr
hin ti ca xe. Mc tiu iu khin l a e tin v 0 cng nhanh cng tt. R rng
nu Kp ln th F cng s ln v xe rt nhanh chng tin v v tr O. Tuy nhin, lc
F qu ln s gia tc cho xe rt nhanh (nh lut II ca Newton: F=ma). Khi xe
n v tr O (tc e=0), th tuy lc F=0 (v F=Kp*e=F=Kp*0) nhng do qun tnh xe
vn tip tc tin v bn phi v lch im O v bn phi, sai s e li tr nn khc 0,
gi tr sai s lc ny c gi l overshot (vt qu). Lc ny, sai s e l s m, lc
F li xut hin nhng vi chiu ngc li ko xe v li im O. Nhng mt ln

na, do Kp ln nn gi tr lc F cng ln v c th ko xe lch v bn tri im O.
Qu trnh c tip din, xe c mi dao ng quanh im O. C trng hp xe dao
ng cng ngy xng xa im O. B iu khin lc ny c ni l khng n nh.
Mt xut nhm gim overshot ca xe l s dng mt thnh phn thng trong
b iu khin. S rt l tng nu khi xe ang xa im O, b iu khin sinh ra
lc F ln nhng khi xe tin gn n im O th thnh phn thng s gim tc
xe li. Chng ta u bit khi mt vt dao ng quanh 1 im th vt c vn
tc cao nht tm dao ng (im O). Ni mt cch khc, gn im O sai s e
ca xe thay i nhanh nht (cn phn bit: e thay i nhanh nht khng phi e ln
nht). Mt khc, tc thay i ca e c th tnh bng o hm ca bin ny theo
thi gian. Nh vy, khi xe t A tin v gn O, o hm ca sai s e tng gi tr
nhng ngc chiu ca lc F (v e ang gim nhanh dn). Nu s dng o
hm lm thnh phn thng th c th gim c overshot ca xe. Thnh
phn thng ny chnh l thnh phn D (Derivative) trong b iu khin PID m
chng ta ang kho st. Thm thnh phn D ny vo b iu khin P hin ti,
chng ta thu c b iu khin PD nhu sau:
F=Kp*e +
Kd*(de/dt)
(2)
Trong (de/dt) l vn tc thay i ca sai s e v Kd l mt hng s khng m
gi l h s D (Derivative gain).
S hin din ca thnh phn D lm gim overshot ca xe, khi xe tin gn v O,
lc F gm 2 thnh phn Kp*e > =0 (P) v Kd*(de/dt) <=0 (D). Trong mt s
trng hp thnh phn D c gi tr ln hn thnh phn P v lc F i chiu,
thng xe li, vn tc ca xe v th gim mnh gn im O. Mt vn ny sinh
l nu thnh phn D qu ln so vi thnh phn P hoc bn thn thnh phn P nh
th khi xe tin gn im O (cha tht s n O), xe c th dng hn, thnh phn D
bng 0 (v sai s e khng thay i na), lc F = Kp*e. Trong khi Kp v e lc ny
u nh nn lc F cng nh v c th khng thng c lc ma st tnh. Bn hy
tng tng tnh hung bn dng sc ca mnh y mt xe ti nng vi chc
tn, tuy lc y tn ti nhng xe khng th di chuyn. Nh th, xe s ng yn mi
d sai s e vn cha bng 0. Sai s e trong tnh hung ny gi l steady state error
(tm dch l sai s trng thi tnh). trnh steady state error, ngi ta thm vo
b iu khin mt thnh phn c chc nng cng dn sai s. Khi steady state
error xy ra, 2 thnh phn P v D mt tc dng, thnh phn iu khin mi s
cng dn sai s theo thi gian v lm tng lc F theo thi gian. n mt lc no
, lc F ln thng ma st tnh v y xe tin tip v im O. Thnh phn
cng dn ny chnh l thnh phn I (Integral - tch phn) trong b iu khin
PID. V chng ta iu bit, tch phn mt i lng theo thi gian chnh l tng
ca i lng theo thi gian. B iu khin n thi im ny y l PID:
F=Kp*e + Kd*(de/dt)
+Ki*edt
(ch : edt l tch phn ca bin e theo t)
(3)
Nh vy, chc nng ca tng thnh phn trong b iu khin PID gi r.

Ty vo mc ch v i tng iu khin m b iu khin PID c th c lt
bt tr thnh b iu khin P, PI hoc PD. Cng vic chnh ca ngi thit k
b iu khin PID l chn cc h s Kp, Kd v Ki sao cho b iu khin hot ng
tt v n nh (qu trnh ny gi l PID gain tuning). y khng phi l vic d
dng v n ph thuc vo nhiu yu t. Ti tm tt mt kinh nghim c bn khi
chn cc h s cho PID nh sau:
- Chn Kp trc: th b iu khin P vi i tng tht (hoc m phng), iu
chnh Kp sao cho thi gian p ng nhanh, chp nhn overshot nh.
- Thm thnh phn D loi overshot, tng Kd t t, th nghim v chn gi tr
thch hp. Steady state error c th s xut hin.
- Thm thnh phn I gim steady state error. Nn tng Ki t b n ln
gim steady state error ng thi khng cho overshot xut hin tr li.
C mt phng php rt ph bin dng chn cc h s cho b iu khin
PID gi l ZieglerNichols, bn quan tm c th t tm hiu thm.
iu khin PID s
Cng thc ca b iu khin PID trnh by trong (3) l dng hm lin tc ca
bin e, trong c c thnh phn tuyn tnh, o hm v tch phn. Tuy nhin, h
thng my tnh v vi iu khin li l h thng s. Mun xy dng b iu khin
PID trn my tnh hay trn vi iu khin chng ta phi bit cch xp x phng
trnh lin tc thnh dng ri rc. thc hin s ha b iu khin PID trc ht
ti ni s qua th no l h thng s (digital) so vi h thng lin tc hay h thng
tng t (analog). Hy quan st h thng iu chnh nhit n gin nh trong
hnh 7.
Hnh 7. T ng iu chnh nhit

Gi s chng ta cn iu chnh nhit trong phng mt mc no (ty
theo gi tr tham chiu) bng qut. Cm bin o nhit v hi tip v b khuych
i vi sai (so snh v khuych i). Nu c sai s gia gi tr tham chiu v gi tr
o t cm bim, b khuych i vi sai s t ng khuych i sai s ny v lm
tng hay gim vn tc ca qut iu chnh nhit . Qu trnh ny xy ra mt
cch lin tc. B khuych i vi sai trong trng hp ny chnh l b iu khin
tng t (analog controller). B khuych i ny l mt mch in t thng
thng nh Opamp chng hn. Nu chng ta thay b khuych i ny bng mt vi
iu khin AVR th qu trnh hiu chnh khng cn xy ra lin tc na m theo mt
chu k no . V d c mi 10 ms chng ta c gi tr t cm bin mt ln tnh
ton sai s v xut gi tr iu khin qut. B iu khin do AVR thc hin gi l
b iu khin s (digital controller) v khong thi gian 10ms ny gi l thi gian
ly mu (sampling time), l khong cch gia 2 ln iu khin lin tip. R rng
thi gian ly mu cng nh (tn s cao) th vic hiu chnh cng tin gn n s
lin tc v cht lng iu khin s tt hn. Trong cc b iu khin s, thi
gian ly mu l mt yu t rt quan trng. Cn tnh ton thi gian ny khng
qu ln nhng cng ng qu nh, v nh th s hao ph thi gian thc thi.
V b iu khin PID xy dng trong AVR s l b iu khin s, chng ta cn
xp x cng thc ca b iu khin ny theo cc khong thi gian ri rc. Trc
ht, thnh phn P tng i n gin v l quan h tuyn tnh Kp*e, chng ta
ch cn p dng trc tip cng thc ny m khng cn bt k xp x no. Tip n
l xp x cho o hm ca bin e. V thi gian ly mu cho cc b iu khin
thng rt b nn c th xp x o hm bng s thay i ca e trong 2 ln ly mu
lin tip:
de/dt =(e(k) e(k-1))/h.
Trong e(k) l gi tr hin ti ca e, e(k-1) l gi tr ca e trong ln ly mu
trc v h l khong thi gian ly mu (h l hng s).
Hnh 8. Xp x o hm ca bin sai s e

Thnh phn tch phn c xp x bng din tch vng gii hn bi hm ng
biu din ca e v trc thi gian. Do vic tnh ton tch phn khng cn qu chnh
xc, chng ta c th dng phng php xp x n gin nht l xp x hnh ch
nht (sai s ca phng php ny cng ln nht). tng c trnh by trong
hnh 9.
Hnh 9. Xp x tch phn ca bin sai s e

Tch phn ca bin e c tnh bng tng din tch cc hnh ch nht ti mi
thi im ang xt. Mi hnh ch nht c chiu rng bng thi gian ly mu h v
chiu cao l gi tr sai s e ti thi im ang xt. Tng qut:
(4)
Tng hp cc xp x, cng thc ca b iu khin PID s c trnh by trong
(5)
(5)
Trong u l i lng output t b iu khin. n gin ha vic tnh
thnh phn tch phn, chng ta nn dng phng php cng dn (hay quy):
(6)
Vi I(k) l thnh phn tch phn hin ti v I(k-1) l thnh phn tch phn trc
.
Cc cng thc (5) v (6) rt d dng thc hin bng AVR. Do , n lc ny

chng ta sn sng a tng vo lp trnh cho chip.
VI. iu khin DC Motor bng AVR
Phn ny chng ta s vn dng tt c phn l thuyt gii thiu trn vit
chng trnh cho AVR. Mc ch l iu khin vn tc ca DC Motor bng gii
thut PID. Mch in m phng c trnh by trong hnh 1. M hnh Motor dng
trong v d l loi 12V c vn tc khng ti ti a l 720rpm (revolute per minute)
tc 20 vng/s. Encoder dng cho motor c chn c phn gii 112 pulse/vng.
Knh A ca encoder c ni vi ngt ngoi INT2 m xung, knh B ni vi
chn PB0 (chn 1) ca chip Atmega32 xt hng quay. Bn switches c ni
vi 4 bit cao ca PORTB ci t vn tc mong mun cn iu khin. Mt Text
LCD dng hin th vn tc thc ca motor c t Encoder (Actual speed) v vn
tc ci t (Desired speed). Do Text LCD c ni vi PORTC nn nu bn mun
dng chng trnh ny cho ng dng tht th phi np li fuses v hiu ha
JTAG. Gii thut PID s c vn hnh bi AVR trong thi gian ly mu l 25ms.
Timer 2 c dng to khong thi gian 25ms. Timer 1 (16 bit) l b to PWM
iu khin vn tc ng c. Ton b ni dung chng trnh c trnh by trong
list 1.
List 1. iu khin vn tc ng c DC
Cc dng t 14 n 17 chng ta nh ngha cc chn iu khin DC Motor, chn

DIR iu khin hng v EN kch hot hoc dng Motor (thc ra l dng L298D).
Do mc ch ca chng ta l iu khin vn tc ng c, 2 chn ny ch c
kch mt ln duy nht trong chng trnh chnh (khng cn i hng quay ca
Motor). Dng 18 nh ngha thi gian ly mu, Sampling_time l 25 ms (.025s).
Bin inv_Sampling_time dng 19 l nghch o ca Sampling_time, 1/0.025 =
40, v y cng l hng s, chng ta nh ngha trc sau ny khng cn thc
hin php nghch o trong chng trnh chnh (tit kim thi gian thc thi). PWM
dng iu khin ng c c chn c tn s 1KHz nn chu k la 1ms. Do chng
ta dng ngun xung gi nhp 8MHz, to thi gian 1ms cn 8000 xung, gi tr
ny c nh ngha trong dng 20 v s c gn cho thanh ghi ICR1 (TOP ca
PWM, xem li bi Timer-Counter, Timer1, Fast PWM) trong chng trnh chnh
(dng 81). Cc dng code t 22 n 27 khai bo mt s bin ton cc dng trong
chng trnh chnh. Do cc bin ny s c dng c trong trnh phc v ngt v
chng trnh chnh nn cn khai bo c tnh volatile, kiu bin l long int tc s
nguyn 32 bit ( trnh b trn khi tnh ton sau ny). Bin Pulse v pre_Pulse l s
xung hin ti v ln ly mu trc c t encoder. Cc bin trong dng 23 v 24
dng cho b iu khin PID, bin Ctrl_Speed l vn tc mong mun (set point)
ton cc v bin Output cha gi tr tnh c t b iu khin PID.
Trc khi i tm hiu chng trnh con cha gii thut PID, chng ta s kho
st ni dung chng trnh main v cc trnh phc v ngt trc hiu tng quan
cch thc thc hin. Chng trnh chnh bt u t dng 45 v kt thc dng
103. Phn u ca chng trnh chnh (ngoi vng lp while) khai bo v khi to
cc module c s dng. 2 dng 49 v 50 ci t hng cho PORTB, do PORT
ny dng c encoder v cc switches chng ta cn set n l input v c in tr
ko ln. Hai dng 52 v 53 set hng cho ng c v s gi hng ny khng i
trong sut qu trnh iu khin sau ny. Hai dng 55 v 56 khai bo ngt ngoi
INT2 dng m xung knh A ca encoder. Ch l INT2 ch c 2 mode l cnh
xung v cnh ln nn ch c 1 bit sense ISC2 chn mode. Bit ISC2 khng nm
trong thanh ghi iu khin MCUCR nh cc ngt khc m nm trong thanh ghi
iu khin-trng thi MCUCSR. Khi ISC2=0 th ch ngt cnh xung ca INT2
c chn (xem dng 55). Sau INT2 c cho php hot ng dng 56. Hy
tm thi di chuyn n dng 109 xem trnh phc v ngt INT2. Chc nng ca
INT2 trong bi ny l m xung encoder v th trnh phc v s lm vic ny.
Khi c mt ngt INT2 xy ra tc c 1 xung t encoder vo th trnh phc v ngt
ISR(INT2 vect) t ng c gi ra, dng 110 trong trnh phc v ngt kim tra
trng thi chn PB0, tc kenh B ca encoder. Nu PB0=1 th tng bin xung m
c Pulse ln 1, ngc li nu PB0=0 th gim Pulse i 1 trong dng 111. Quay
v gii thch chng trnh chnh dng 59, y l cc khai bo cho timer 2. Chng
ta s dng timer 2 to ra mt khong thi gian ly mu 25 ms, c sau 25 ms th s
c ngt trn timer2 mt ln v trong trnh phc v ngt trn ca timer2 chng ta
thc hin tnh ton PID. Dng 59 chng ta set cc bit CS chn b chia tn s, b
chia Prescaler=1024 c chn v 25 ms kh ln so vi thi gian 1 chu k xung
gi nhp (1/8 micro giy). Prescaler = 1024 ngha l sau 1024 nhp ca xung gi
nhp, tc sau 128 micro giy (1024 *1/8=128 us) th thanh ghi gi tr TCNT2 mi
tng 1 n v. Do chng ta mun to khong thi gian 25 ms tng ng
25000/128=195 n v m ca thanh ghi TCNT2, chng ta s gn gi tr khi to
cho TCNT2 l 255-195=60 (timer 2 s trn mt ln khi TCNT2 m n 255, xem
li bi Timer-Counter). iu ny thc hin dng 60 TCNT2=60. Dng 61 cho
php ngt trn timer2. Hai dng 64 v 65 khi ng Timer 1 dng nh mt b to
xung Fast PWM, mode 14, trong thanh ghi ICR1 cha chu k PWM v 2 thanh
ghi OCR1A, OCR1B cha duty cycle (khong ON) ca PWM. Cc dng t 68 n
70 ghi texts ln LCD. Cc dng t 80 n 83 khi ng PWM cho DC Motor v
cho php ngt ton cc sei();. Trong vng lp while ch yu l cng vic kim tra
v hin th, bin sample_count m s ln ngt trn timer2 xy ra, n c tng 1
n v khi c mt ngt trn (xem dng 106) tc sau 25ms. Dng 86, chng ta kim
tra bin sample_count, vic hin th ch cthc hin mi 250 ms mt ln
(sample_count=10) v vic ny tn kh nhiu thi gian. Trong dng 87 chng ta
kim tra cc swiches xem ngi dng cho mun thay i vn tc tham chiu
cho iu khin. Cc dng tip theo in bin rSpeed l s lng xung m c t
encoder trong vng 25 ms (cho ti hin ti) dong 1 ca LCD v in bin
Ctrl_Speed l s xung/25ms m ngi dng mong mun motor t c. Ni dung
quan trng nht ca list 1, tuy nhin, khng nm trong chng trnh chnh m nm
cc trnh phc v ngt v chng trnh con Motor_Speed_PID(long int
des_Speed).
Trc ht, trnh phc v ngt ISR(TIMER2_OVF_vect) c t ng gi sau
mi 25ms, trong trnh ny chng ta cn set li gi tr khi ng cho thanh ghi gi
tr TCNT2 (xem li bi Timer-counter) dng 105. Sau tng bin m
sample_count ln 1 (cng cho vic m thi gian hin th, ni trn). Cui
cng l gi chng trnh con tnh ton gii thut PID Motor_Speed_PID(long int
des_Speed). y l on chng trnh tnh ton gii thut PID v xut gi tr iu
khin Motor. Hy quay li dng 30 tm hiu chng trnh con ny. Do bin
Pulse cha tng s xung c t encode (trong ISR(INT2_vect) ), chng ta ly gi
tr ny tr i gi tr pre_Pulse, tc s lng xung thi im 25 ms trc ,
thu c tng s xung thu c trong 25 ms qua. y chnh l vn tc motor tnh
trn 25 ms:rSpeed=Pulse-pre_Pulse. Sau khi tnh c vn tc rSpeed chng ta
gn li gi tr Pulse cho pre_Pulse ln ly mu sau dng n (dng 32). Sai s
vn tc c t tn l Err, bin ny c tnh bng bng cch ly vn tc mong
mun tr vn tc hin ti: Err=des_Speed-abs(rSpeed) dng 33. Dng 34 tnh
thnh phn P ca b iu khinpPart=Kp*Err. Dng 35 tnh thnh phn D ca b
iu khin, nh chng ta tho lun trong cng thc (2) th thnh phn D c
tnh l: dPart=Kd*(Err-pre_Err)/Sampling_time, trong pre_Err l gi tr sai s
ln ly mu trc c lu li. Do 1/Sampling_time = inv_Sampling_time nn
chng ta c th thay dng tnh dPart bng cng thc trong dng
35: dPart=Kd*(Err-pre_Err)*inv_Sampling_time. Dng 36 tnh thnh phn I
(iPart), s dng phng php cng dn ( quy) chng ta thu c iPart bng
iPart trc cng vi din tch hnh ch nht sai s hin
ti:iPart+=Ki*Sampling_time*Err/1000. Chng ta phi chia iPart cho 1000 v
Sampling_time c tnh theo ms trong khi n v tnh ton chun trong l s. Cng
cc thnh phn ny li chng ta c gi tr Output tng hp trong dng 37. Tuy
nhin, theo l thng th cng thc dng 37 phi l Output=pPart+dPart+iPart
nhng y li l :Output+=pPart+dPart+iPart ( du + trc du =), ngha
l Output c cng dn thay v l tng tc thi nh chng ta tho lun trong
phn gii thut PID. Tht ra vic ny cng d hiu. Trong bi ton iu khin v tr,
khi sai s bng 0 chng ta c th dng b iu khin (u=0) nhng trong bi ton
iu khin vn tc, khi sai s bng 0 th gi tr u vn phi c gi l gi tr trc
.V vy, trong bi ton iu khin vn tc gi tr Output c cng dn thay v
gn trc tip, bn phi ghi nh iu ny trong cc ng dng iu khin ca mnh.
Hai dng 40 v 41 xt trng hp bo ha (saturation) khi Output vt qu gii
hn cho php ca PWM (xn 2 u). Cui cng l gn gi tr tnh ton c t PID
cho thanh ghi OCR1A tng hoc gim duty cycle ca PWM trn chn OC1A
(ni vi PWM ca Motor) v gn gi tr sai s Err cho bin pre_Err cho ln ly
mu sau dng n.
Chy m phng: ton b chng trnh v c mch in m phng c ti
to sn. Ngi c ch cn c hiu v chy m phng mch in. Ch khi chy
m phng hy thay i cc switches thay i vn tc cn iu khin. Gi tr vn
tc thc cht l s xung encoder trong 25 ms, ngi c hy t tnh ra s vng /s.
Do m hnh motor trong phn mm m phng khng hon ho lm nn p ng b
iu khin hi chm, bn c th phi ch mt khong thi gian thy vn tc
Motor t n vn tc yu cu. Hay thay gi tr Kd trong dng 23 thnh 1 hoc 0,
bin dch li chng trnh v m phng quan st v so snh ovetshot (s vt
qu) ca h thng.
ng h thi gian thc DS1307
5
( 103 Votes )
Ni dung

Cu trc AVR.
1.
Chip DS1307.
2.
AVR v DS1307.
Download v d
WinAVR.
C cho AVR.
Text LCD
Giao tip TWI-I2C
I. Chip DS1307.
DS1307 l chip ng h thi gian thc (RTC : Real-time clock), khi nim thi
gian thc y c dng vi ngha thi gian tuyt i m con ngi ang s
dng, tnh bng giy, pht, giDS1307 l mt sn phm ca Dallas
Semiconductor (mt cng ty thuc Maxim Integrated Products). Chip ny c 7
thanh ghi 8-bit cha thi gian l: giy, pht, gi, th (trong tun), ngy, thng,
nm. Ngoi ra DS1307 cn c 1 thanh ghi iu khin ng ra ph v 56 thanh ghi
trng c th dng nh RAM. DS1307 c c v ghi thng qua giao din ni tip
I2C (TWI ca AVR) nn cu to bn ngoi rt n gin. DS1307 xut hin 2 gi
SOIC v DIP c 8 chn nh trong hnh 1.
Hnh 1. Hai gi cu to chip DS1307.

Cc chn ca DS1307 c m t nh sau:
- X1 v X2: l 2 ng kt ni vi 1 thch anh 32.768KHz lm ngun to dao
ng cho chip.
- VBAT: cc dng ca mt ngun pin 3V nui chip.
- GND: chn mass chung cho c pin 3V v Vcc.
- Vcc: ngun cho giao din I2C, thng l 5V v dng chung vi vi iu
khin. Ch l nu Vcc khng c cp ngun nhng VBAT c cp th DS1307
vn ang hot ng (nhng khng ghi v c c).
- SQW/OUT: mt ng ph to xung vung (Square Wave / Output Driver),
tn s ca xung c to c th c lp trnh. Nh vy chn ny hu nh khng
lin quan n chc nng ca DS1307 l ng h thi gian thc, chng ta s b
trng chn ny khi ni mch.
- SCL v SDA l 2 ng giao xung nhp v d liu ca giao din I2C m
chng ta tm hiu trong bi TWI ca AVR.
C th kt ni DS1307 bng mt mch in n gin nh trong hnh 2.
Hnh 2. Mch ng dng n gin ca DS1307.

Cu to bn trong DS1307 bao gm mt s thnh phn nh mch ngun, mch
dao ng, mch iu khin logic, mch giao in I2C, con tr a ch v cc thanh
ghi (hay RAM). Do a s cc thnh phn bn trong DS1307 l thnh phn cng
nn chng ta khng c qu nhiu vic khi s dng DS1307. S dng DS1307 ch
yu l ghi v c cc thanh ghi ca chip ny. V th cn hiu r 2 vn c bn
l cu trc cc thanh ghi v cch truy xut cc thanh ghi ny thng qua giao din
I2C. Phn ny chng ta tm hiu cu trc cc thanh ghi trc v cch truy xut
chng s tm hiu trong phn 2, iu khin DS1307 bng AVR.
Nh ti trnh by, b nh DS1307 c tt c 64 thanh ghi 8-bit c nh
a ch t 0 n 63 (t 0x00 n 0x3F theo h hexadecimal). Tuy nhin, thc cht
ch c 8 thanh ghi u l dng cho chc nng ng h (ti s gi l RTC) cn li
56 thanh ghi b trng c th c dng cha bin tm nh RAM nu mun. By
thanh ghi u tin cha thng tin v thi gian ca ng h bao gm: giy
(SECONDS), pht (MINUETS), gi (HOURS), th (DAY), ngy (DATE), thng

(MONTH) v nm (YEAR). Vic ghi gi tr vo 7 thanh ghi ny tng ng vi
vic ci t thi gian khi ng cho RTC. Vic c gi t 7 thanh ghi l c thi
gian thc m chip to ra. V d, lc khi ng chng trnh, chng ta ghi vo
thanh ghi giy gi tr 42, sau 12s chng ta c thanh ghi ny, chng ta thu
c gi tr 54. Thanh ghi th 8 (CONTROL) l thanh ghi iu khin xung ng ra
SQW/OUT (chn 6). Tuy nhin, do chng ta khng dng chn SQW/OUT nn c
th b qua thanh ghi th 8. T chc b nh ca DS1307 c trnh by trong hnh
3.
Hnh 3. T chc b nh ca DS1307.

V 7 thanh ghi u tin l quan trng nht trong hot ng ca DS1307, chng
ta s kho st cc thanh ghi ny mt cch chi tit. Trc ht hy quan st t chc
theo tng bit ca cc thanh ghi ny nh trong hnh 4.
Hnh 4. T chc cc thanh ghi thi gian.

iu u tin cn ch l gi tr thi gian lu trong cc thanh ghi theo dng
BCD. BCD l vit tt ca cm t Binary-Coded Decimal, tm dch l cc s thp
phn theo m nh phn. V d bn mun ci t cho thanh ghi MINUTES gi tr
42. Nu quy i 42 sang m thp lc phn th chng ta thu c 42=0x2A. Theo
cch hiu thng thng chng ta ch cn gn MINUTES=42 hoc
MINUTES=0x2A, tuy nhin v cc thanh ghi ny cha gi tr BCD nn mi
chuyn s khc, ti s din gii bng hnh 5.
Hnh 5. S BCD.
Vi s 42, trc ht n c tch thnh 2 ch s (digit) 4 v 2. Mi ch s sau
c i sang m nh phn 4-bit. Ch s 4 c i sang m nh phn 4-bit l
0100 trong khi 2 c i thnh 0010. Ghp m nh phn ca 2 ch s li chng ta
thu c mt s 8 bit, l s BCD. Vi trng hp ny, s BCD thu c l
01000010 (nh phn) = 66. Nh vy, t s pht 42 cho DS1307 chng ta cn
ghi vo thanh ghi MINUTES gi tr 66 (m BCD ca 42). Tt c cc phn mm lp
trnh hay thanh ghi ca chip iu khin u s dng m nh phn thng thng,
khng phi m BCD, do chng ta cn vit cc chng trnh con quy i t s
thp nh phn (hoc thp phn thng) sang BCD, phn ny s c trnh by
trong lc lp trnh giao tip vi DS1307. Thot nhn, mi ngi u cho rng s
BCD ch lm vn n thm rc ri, tuy nhin s BCD rt c u im trong vic
hin th nht l khi hin th tng ch s nh hin th bng LED 7 on chng hn.
Quay li v d 42 pht, gi s chng ta dng 2 LED 7-on hin th 2 ch s
ca s pht. Khi c thanh ghi MINUTES chng ta thu c gi tr 66 (m BCD
ca 42), do 66=01000010 (nh phn), hin th chng ta ch cn dng phng
php tch bit thng thng tch s 01000010 thnh 2 nhm 0100 v 0010 (tch
bng ton t shift >> ca C hoc instruction LSL, LSR trong asm) v xut trc
tip 2 nhm ny ra LED v 0100 = 4 v 0010 =2, rt nhanh chng. Thm ch, nu
chng ta ni 2 LED 7-on trong cng 1 PORT, vic tch ra tng digit l khng
cn thit, hin th c s, ch cn xut trc tip ra PORT. Nh vy, vi s BCD,
vic tch v hin th digit c thc hin rt d dng, khng cn thc hin php
chia (rt tn thi gian thc thi) cho c s 10, 100, 1000nh trong trng hp s
thp phn.
Thanh ghi giy (SECONDS): thanh ghi ny l thanh ghi u tin trong b nh
ca DS1307, a ch ca n l 0x00. Bn bit thp ca thanh ghi ny cha m BCD
4-bit ca ch s hng n v ca gi tr giy. Do gi tr cao nht ca ch s hng
chc l 5 (khng c giy 60 !) nn ch cn 3 bit (cc bit SECONDS6:4) l c th
m ha c (s 5 =101, 3 bit). Bit cao nht, bit 7, trong thanh ghi ny l 1 iu
khin c tn CH (Clock halt treo ng h), nu bit ny c set bng 1 b dao
ng trong chip b v hiu ha, ng h khng hot ng. V vy, nht thit phi
reset bit ny xung 0 ngay t u.
Thanh ghi pht (MINUTES): c a ch 0x01, cha gi tr pht ca ng h.
Tng t thanh ghi SECONDS, ch c 7 bit ca thanh ghi ny c dng lu m
BCD ca pht, bit 7 lun lun bng 0.
Thanh ghi gi (HOURS): c th ni y l thanh ghi phc tp nht trong
DS1307. Thanh ghi ny c a ch 0x02. Trc ht 4-bits thp ca thanh ghi ny
c dng cho ch s hng n v ca gi. Do DS1307 h tr 2 loi h thng hin
th gi (gi l mode) l 12h (1h n 12h) v 24h (1h n 24h) gi, bit6
(mu green trong hnh 4) xc lp h thng gi. Nu bit6=0 th h thng 24h c
chn, khi 2 bit cao 5 v 4 dng m ha ch s hng chc ca gi tr gi. Do gi
tr ln nht ca ch s hng chc trong trng hp ny l 2 (=10, nh phn) nn 2
bit 5 v 4 l m ha. Nu bit6=1 th h thng 12h c chn, vi trng hp
ny ch c bit 4 dng m ha ch s hng chc ca gi, bit 5 (mu orangetrong
hnh 4) ch bui trong ngy, AM hoc PM. Bit5 =0 l AM v bit5=1 l PM. Bit 7
lun bng 0. (thit k ny hi d, nu di hn 2 bit mode v A-P sang 2 bit 7 v 6
th s n gin hn).
Thanh ghi th (DAY ngy trong tun): nm a ch 0x03. Thanh ghi DAY
ch mang gi tr t 1 n 7 tng ng t Ch nht n th 7 trong 1 tun. V th,
ch c 3 bit thp trong thanh ghi ny c ngha.
Cc thanh ghi cn li c cu trc tng t, DATE cha ngy trong thng (1 n
31), MONTH cha thng (1 n 12) v YEAR cha nm (00 n 99). Ch ,
DS1307 ch dng cho 100 nm, nn gi tr nm ch c 2 ch s, phn u ca nm
do ngi dng t thm vo (v d 20xx).
Ngoi cc thanh ghi trong b nh, DS1307 cn c mt thanh ghi khc nm
ring gi l con tr a ch hay thanh ghi a ch (Address Register). Gi tr ca
thanh ghi ny l a ch ca thanh ghi trong b nh m ngi dng mun truy cp.
Gi tr ca thanh ghi a ch (tc a ch ca b nh) c set trong lnh Write m
chng ta s kho st trong phn tip theo, AVR v DS1307. Thanh ghi a ch c
ti t trong hnh 6, cu trc DS1307.
Hnh 6. Cu trc DS1307.

II. AVR v DS1307.
Phn ny ti hng dn lp trnh iu khin v giao tip vi DS1307 bng
AVR, dng WinAVR. Do DS1307 hot ng nh mt Slave I2C, bn nht thit
phi c li Bi 8 - Giao tip TWI-I2C, nht l l 2 ch Master (Send v
Reveive). Ti s khng cp li ton b giao din I2C nhng tm tt cch thc
hin vi AVR nh sau: thc hin cuc gi ch Master, AVR s gi iu
kin START, tip theo l 7 bit a ch Slave (SLA) +1 bit Write/Read, k n l qu
trnh c hay ghi d liu gia Master v Slave bng cc byte d liu 8 bit (c th
ch 1 byte hoc 1 dy bytes), c sau mi byte s c 1 bit ACK hoc NOT ACK.
Cuc gi kt thc vi vic Master pht iu kin STOP. C mi mt qu trnh, s

c 1 code c sinh ra trong thanh ghi trng thi TWSR, kim tra gi tr code
ny bit qu trnh giao tip c thnh cng khng. Bn cn nh dy code thnh
cng khi Master truyn d liu l: 0x08 -> 0x18 -> 0x28 ->->0x28. V dy code
thnh cng khi Master truyn d liu l 0x08 - > 0x40 - > 0x50 ->->0x50 ->
0x58. Nm c cch ghi v c ca AVR Master l bn nm c 50% cch
giao tip vi DS1307, 50% cn li chng ta phi hiu cch b tr dy d liu ca
ring DS1307. Hy theo di phn tip theo..
V DS1307 l mt Slave I2C nn ch c 2 mode (ch ) hot ng giao tip
vi chip ny. Hai mode ca DS1307 bao gm Data Write (t AVR n DS14307)
v Data Read (t DS1307 vo AVR). Mode Data Write c dng khi xc lp gi
tr ban u cho cc thanh ghi thi gian hoc dng canh chnh thi gian. Trong
ch ny, AVR l 1 Master truyn d liu n DS1307 (Slave nhn d liu).
Mode Data Read c s dng khi c thi gian t ng h DS1307 vo AVR
hin th hoc so snh.Trong ch ny, AVR l Master nhn d liu v DS1307
l Slave truyn d liu. Hnh 7 m t cu trc d liu trong ch Data Write.
Hnh 7. Ch Data Write.

Trc ht hy ni v a ch Slave Address (SLA) ca DS1307 trong mng I2C.
Nh chng ta u bit, trn mng I2C mi thit b s c mt a ch ring gi l
SLA. SLA l con s 7 bit, nh th theo l thuyt s c ti a 128 thit b trong 1
mng I2C. Chip DS1307 l mt I2C Slave nn cng c mt a ch SLA, gi tr
ny c set c nh l 1101000 nh phn, hay 0x68 thp lc phn. Do SLA ca
DS1307 c nh nn trong 1 mng I2C s khng th tn ti cng lc 2 chip ny
(iu ny thc s khng cn thit) nhng c th tn ti cc thit b I2C khc hoc
tn ti nhiu Master AVR. Quan st hnh 7, sau khi iu kin START c gi bi
Master (AVR) s l 7 bit a ch SLA ca DS1307 (1101000). Do ch ny l
Data Write nn bit W (0) s c gi km sau SLA. Bit ACK (A) c DS1307 tr
v cho Master sau mi qu trnh giao tip. Tip theo sau a ch SLA s l 1 byte
cha a ch ca thanh ghi cn truy cp (tm gi l Addr_Reg). Cn phn bit a

ch thanh ghi cn truy cp v a ch SLA. Nh ti cp trn, a ch ca thanh
ghi cn tuy cp s c lu trong thanh ghi a ch (hay con tr a ch), v vy
byte d liu u tin s c cha trong thanh ghi a ch ca DS1307. Sau byte
a ch thanh ghi l mt dy cc byte d liu c ghi vo b nh ca DS1307.
Byte d liu u tin s c ghi vo thanh ghi c a ch c ch nh bi
Addr_Reg, sau khi ghi 1 byte, Addr_Reg c t ng tng nn cc byte tip theo
s c ghi lin tip vo cc thanh ghi k sau. S lng bytes d liu cn ghi do
Master quyt nh v khng c vt qu dung lng b nh ca DS1307. V d
sau khi gi SLA+W, Master gi 8 bytes gm 1 byte u 0x00 v 7 bytes khc th
con tr a ch s tr n thanh ghi u tin (0x00 thanh ghi SECONDS) v ghi
lin tip 7 bytes vo 7 thanh ghi thi gian ca SD1307. y l cch m chng ta s
thc hin trong phn lp trnh giao tip ( xem chng trnh con
TWI_DS1307_wblock pha sau). Qu trnh ghi kt thc khi Master pht ra iu
kin STOP.
Ch , nu sau khi gi byte Addr_Reg, Master khng gi cc bytes d liu m
gi lin iu kin STOP th khng c thanh ghi no c ghi. Trng hp ny
c dng set a ch Addr_Reg phc v cho qu trnh c. Tip theo, chng ta
kho st cch sp xp d liu trong ch Data Read, xem hnh 8.
Hnh 8. Ch Data Read.

Trong ch Data Read, bit R (1) c gi km sau 7 bit SLA. Sau l lin
tip cc byte d liu c truyn t DS1307 n AVR. im khc bit trong cc
b tr d liu ca ch ny so vi ch Data Write l khng c byte a ch
thanh ghi d liu c gi n. Tt c cc bytes theo sau SLA+R u l d liu
c t b nh ca DS1307. Vy th d liu c c bt u t thanh no? Cu tr
li l thanh ghi c ch nh bi con tr a ch, gi tr ny c lu li trong
cc ln thao tc trc o. Nh vy, mun c chnh xc d liu t mt a no ,

chng ta cn thc hin qu trnh ghi gi tr cho con tr a ch trc. ghi gi tr
vo con tr a ch chng ta s gi chng trnh Data Write vi ch 1 byte c ghi
sau SLA+W nh phn ch trn.
Chng ta chun b y giao tip vi DS1307. Phn tip theo ti s
trnh by chng trnh v m phng giao tip gia AVR v DS1307. Hy v mt
mch in bng Proteus nh trong hnh 9. Trong v d ny, ban u chng ta s ci
t thi gian cho DS1307, sau tin hnh c thi gian t chip ng h ny v
hin th ln 1 Text LCD.
Hnh 9. V d giao tip AVR DS1307.

Ti s chia chng trnh thnh 2 phn, phn giao tip vi DS1307 thng qua
I2C c vit trong file myDS1307RTC.h v phn v d ghi-c, hin th c vit
trong file DS1307RTC_Test.c.
List 1. myDS1307RTC.h.
Cc phn nh ngha trc dng 35 c trch t bi TWI nn ti khng gii

thch li. Chng ta bt u t dng 36. C 3 chng trnh con c vit giao
tip gia AVR vi DS1307 l: ghi 1 dy d liu vo DS1307 tc chng trnh
con TWI_DS1307_wblock(uint8_t Addr, uint8_t Data[], uint8_t len), chng
trnh ny c vit theo cch sp xp d liu ca ch Data Write trnh by
trn. Chng trnh con c d liu t DS1307 lTWI_DS1307_rblock(uint8_t
Data[], uint8_t len ) v mt chng trnh con dng set a ch thanh ghi cn
truy
cp
c
tn TWI_DS1307_wadr(uint8_t
Addr).
Chng trnh con TWI_DS1307_wblock(uint8_t Addr, uint8_t Data[],
uint8_t len) nm t dng 54 n dng 77. Trong chng trnh con ny, tham s
Addr l a ch thanh ghi cn truy cp, Data[] l mng d liu s ghi vo DS1307
v len l s byte d liu s ghi (khng tnh byte Addr). Dng 55, AVR pht ra iu
kin START bt 1 cuc gi I2C, sau chng ta ch cho bit TWINT c set
ln 1 dng 56 (TWINT = 1, cng vic c thc hin). Dng 57 kim tra nu
iu kin START gi thnh cng hay khng bng cch so snh thanh ghi trng
thi TWSR vi code tng ng (xem li hnh 2 trong bi giao tip TWI). Sau khi
START c gi, dng 59 chng ta gn a ch SLA+W cho thanh ghi d liu
TWDR pht ra trn I2C, TWDR=(DS1307_SLA<<1)+TWI_W. Trong dng
ny, bin DS1307_SLA l SLA ca DS1307 c nh ngha trc dng 15
trong khi TWI_W l bit W (=0) c nh ngha dng 20. Qu trnh pht I2C ch
bt u khi bit TWINT c xa, dng 60 thc hin vic ny, sau phi ch bit
TWINT c set ln 1 chng t qu trnh pht SLA kt thc (dng 61). Cui cng
l kim tra code trong thanh ghi TWSR xem qu trnh pht SLA c thanh cng,
xem dng 62 v hnh 2 trong bi giao tip TWI. Chng ta s lun theo c ch ny
khi lm vic vi TWI ca AVR, do trong cc phn tip theo ti ch gii thch ni
dung truyn-nhn, khng gii thch li c ch. Sau khi pht SLA+W, cc dng 64
n 65 pht a ch thanh ghi cn truy cp (bin Addr) v sau pht mng d liu
lin tip trong cc dng 69 n 74. Cui cng l pht in kin STOP kt thc
cuc
gi.
Trong chng trnh con ghi DS1307 trnh by trn, nu tham s len=0 th cc
dng 69 n 74 khng c thc hin, ngha l ch c a ch Addr c pht m
khng c d liu no km theo. Chng ta c th dng c im ny set thanh
ghi cho qu trnh c. Ti tch ra v vit thnh 1 chng trnh con
tn TWI_DS1307_wadr(uint8_t Addr)trong cc dng t 36 n 52 dng thc
hin
vic
set
a
ch
ny.
Chng trnh con c DS1307 TWI_DS1307_rblock(uint8_t Data[], uint8_t
len ) c trnh by trong cc dng t 79 n 99. Trong , tham s Data[] l
mng cha d liu c v, len l s bytes c v, c bit khng c tham s a ch
thanh ghi v a ch ny s c set ring trc khi gi chng trnh con c
DS1307. Dng 84 mt lnh pht SLA+TWI_R c thc hin, vi bit TWI_R=1
(xem nh ngha dng 21), AVR ang bo cho DS1307 rng n mun c d liu
t DS1307. Qu trnh c c chia thnh 2 phn, trong phn 1 chng ta c len-1
bytes u tin (xem cc dng code t 88 n 92) v phn 2 c byte cui cng
(dng 94 n 96). Chng ta cn tch vic c byte cui ra v nu nhn li ch
c trnh by trong hnh 8, sau mi byte c c, Master phi gi 1 bit ACK n
DS1307, ring byte cui cng Master phi gi bit NOT ACK bo DS1307 rng
Master khng mun c thm (so snh 2 dng 89 v 94). Cui cng, Master gi
iu
kin
STOP
kt
thc
cuc
gi.
kim tra cc hm giao tip DS1307, hy to 1 Project bng WinAVR vi tn
gi DS1307RTC_Test, to file DS1307RTC_Test v vit code nh trong list 2.
List 2. DS1307RTC_Test.c.
Chng trnh demo DS1307 dng cc hm trong file DS1307RTC.h trc ,

bn cn copy file ny vo cng th mc vi chng trnh demo ny. ng thi,
chp c file myLCD.h v v d ny c hin th LCD. C ch ca chng trnh
demo nh sau: trong phn thn chng trnh chnh, ban u chng ta ghi cc thng
s thi gian khi to cho DS1307, ti chn thi im ghi vo l 11h:59p:55s ca
ngy 31, thng 12 nm 09 (2009) cho mc ch kim tra. Vi thi im ny, sau
khi chy chng trnh c 5s bn s thy cc thanh thi gian trong DS1307 t
ng chuyn sang 0h:0p:0s ngy 1 thng 1 nm 10. Ch l ngun clock cho chip
trong v d ny l 8MHz, Ti dng Timer0 to ra 1 khong thi gian delay
khong 32.7ms, c 10 ln ngt Timer0 (tc khong 327ms) ti s c DS1307 v
cp nht kt qu ln LCD. Cc bin ph Second, Minute, Hour, Day, Date, Month,
Year c khai bo dng 8 v 9 cha thi gian (s thp phn bnh thng). Bin
Mode chn h thng gi, Mode =0 l h thng 24h v Mode=1 l h thng 12h.
Bin AP cha bui trong Mode 12h, AP=0 l bui sng (AM), AP=1 l bui chiu
(PM). Mng tData[7] c 7 phn t trong dng 14 cha 7 bytes tm tng ng vi 7
thanh ghi thi gian ghi vo DS1307 hoc c ra t chip ny. Cc dng t 17 n
28 l 2 chng trnh con i t s BCD sang thp phn v ngc li.
Chng ta bt u vi chng trnh con Display (void), hin th kt qu cha
trong mng tData[7] ln LCD (dng 30 n 64). Cc dng t 31 n 37 dng c
gi tr trong mng tData[7] ra cc bin hin th, v tData[7] cha gi tr c v
t cc thanh ghi thi gian ca DS1307 nn n l cc s BCD, chng ta cn dng
hm BCD2Dec i sang s thp phn trc khi gn cho cc bin nh Second,
Minutehin th ln LCD. Ring vi thanh ghi HOURS (tng ng vi sData[2])
chng ta cn kim tra h thng gi, nu l h thng 12h th ch ly 5 bit u ca
thanh ghi ny gn cho bin Hour (xem li phn t chc cc thanh ghi thi gian
hnh 4), nu l h thng 24h th s ly 6 bit (xem 2 dng 33 v 34). Cc dng t 39
n 64 in cc bin thi gian ln LCD. Dng u tin ca LCD dng in gi-phtgiy, dng th 2 in nm-thng-ngy. Phn b tr v tr cc gi tr in ngi c t l
gii.
Chng trnh chnh main bt u t dng 66 v kt thc dng 106. Cc cng
vic thc hin trong main bao gm khi ng Text LCD, khi ng Timer0 ch
thng, Prescaler=1024 v cho php ngt trn (cc dng t 77 n 79). Vi
f=8MHz, gi tr nh th mi ln trn Timer0 l : (1024(Prescaler)/8 (f))*256
(MAX)=32768 us =32.7ms. Cc dng t 83 n 90 gn gi tr cc bin thi gian
vo mng tData chun b ghi vo DS1307. Trc khi gn cc bin ny cho
tData, chng ta cn i gi tr thp phn ca chng thnh BCD vi hm Dec2BCD.
Dng 91 khi ng I2C v dng 92 ghi 7 phn t ca mng tData vo DS1307 vi
hm TWI_DS1307_wblock m chng ta nh ngha trong file DS1307RTC.h.
Ch l a ch bt u ghi l 0x00, v th 7 bytes ca mng tData s c ghi
chnh xc vo 7 thanh ghi thi gian ca DS1307. Sau khi ghi d liu, cn 1 khong
thi gian nh DS1307 x l, _delay_ms(1) l . Cc dng t 97 n 100 tin

hnh c thi gian t DS1307 v v hin th ln LCD. Dng 97
TWI_DS1307_wadr(0x00) dng set a ch thanh ghi cn truy cp trc khi
c, chng ta mun c ht 7 thanh ghi thi gian nn s set a ch v 0 (thanh ghi
SECONDS). Phi delay 1 khong nh trc khi tip tc c DS1307 (dng 98).
Dng 99 chng ta c 7 thanh ghi thi gian vo mng tData v hin th ln LCD
dng 100. Chng trnh chnh kt thc y, vic cn li cho trnh phc v ngt
thc
hin.
Trong trnh phc v ngt trn ca Timer0 (t dng 107 n 125), chng ta tng
1 bin tm tn l Time_count, n khi no 10 ngt xy ra (khong 327ms) th mi
tin hnh c DS1307 mt ln (cc dng t 111 n 113). Do c mi 327ms chng
ta c DS1307 1 ln nn s c trng hp 2 ln c cng 1 gi tr, chng ta ch
thc hin vic cp nht kt qu khi 1 giy qua. Dng 115 so snh kt qu c v
vi bin Second, tc l so snh kt qu mi vi kt qu c, nu chng khc nhau s
cp nht gi tr giy trn LCD (cc dng t 116 n 119). Chng ta iu bit vic
ghi ln LCD s tn kh nhiu thi gian, v vy ch nn cp nht kt qu khi no c
s thay i. Mt khc, khi s giy thay i th cc bin thi gian khc thay i rt
chm, mt cch tt trnh vic xa v ghi LCD nhiu ln l c 60s hy thc hin
hm Display (trong hm ny c c xa v ghi cc bin thi gian). Dng 120 gip
thc hin tng ny, ch khi no bin Second v 0 ( qua 60s) mi gi hm
Display().
n y, ton b vic truy cp DS1307 bng AVR hon tt. Cc tng m
rng ng dng nh thm cc nt chnh thi gian, ci t bo gixin nhng li
cho bn c t pht trin.
Giao tip AVR vi my tnh (I)
5
( 23 Votes )
Ni dung
Cc bi cn tham kho t
1.
Gii thiu
C cho AVR.
2.
S lc v cng COM
UART
3.
To cng COM o cho m phng

TextLCD
4.
S dng th vin xut nhp chun stdio.h trong WinAVR

Bi 2
M phng vi Prot
Download v d
I. Gii thiu
Bi vit ny s ni v cch giao tip gia AVR v my tnh c nhn (PC) theo
mt cch n gin nhng kh ton din. N n gin v ti s dng mt giao din
kh c in giao tip gia AVR v PC, giao din RS232 thng qua cc cng
COM. Ton din v ti s hng dn cc bn t cch mc mch chuyn gia AVR
v PC, cch vit chng trnh giao tip theo chun RS232 trn my tnh v trn
AVR. C th bi ny bao gm:
- S lt s v chc nng cc chn cng COM trn my tnh.
- Mch chuyn kt ni AVR vi PC qua cng COM.
- To cng COM o trn PC cho mc ch m phng.
- S dng cc hm trong th vin xut nhp chun ca C nh printf, scanf
trong WinAVR.
- Vit chng trnh giao tip RS232 cho AVR.
- S dng Hyper Terminal ca Windows trong giao tip RS232.
- Vit chng trnh truy xut cng COM trn PC (Visual C++, Visual Basic)
II. S lc v cng COM
Cng COM hay cng ni tip (COM Port, Serial Port) l cng giao tip thuc
vo dng lo lng trn PC, c my tnh bn v Laptop. Ngy nay vi s xut
hin v bnh trng ca chun USB th cng COM (v c cng LPT hay cng
song song) ang dn bin mt. Giao tip thng qua cng COM l giao tip theo
chun ni tip RS232. Chun ny c tc kh chm nu em so snh vi USB.
Tuy nhin, vi dn robotics hay control th COM-RS232 li rt c a chung v
tnh n gin v cng vs chm chp ny. Cc cng COM trn cc my tnh
hin ti (nu c) a s l dng cng c 9 chn (male 9 pins). Tuy nhin, u
vn cn tn ti loi cng COM 25 chn, loi ny v hnh dng kh ging cng LPT
nhng l loi male trong khi cng LPT l female. Hnh 1 th hin 2 dng ca cng
COM v bng 1 tm tt chc nng cc chn ca cng ny.
Hnh 1. Cng COM 9 chn v 25 chn.
Bng 1: Cc chn trn cng COM
ng ch nht trong cc chn ca cng COM l 3 chn 0V SG (signal

ground), chn pht d liu TxD v chn nhn d liu RxD. y l 3 chn c bn
phc v truyn thng theo chun RS232 v tng thch vi UART trn AVR. Cc
chn cn li cng c th c s dng nu ngi dng c 1 t kin thc v t chc
thanh ghi ca PC. Tuy nhin, trong a s trng hp giao tip qua cng COM th
ch 3 chn trn c s dng.
Nh trnh by trong bi AVR5-UART, chun RS232 v UART nhn chung l

nh nhau v mt khung truyn, tc baudnhng khc nhau v mc in p v
cc. Xem li v d so snh trong hnh 2.
Hnh 2. So snh UART v RS232.

Trong chun UART (trn AVR), mc 1 tng ng in p cao (5V, TTL) trong khi
i vi RS232 th mc 1 tng ng vi in p thp (in p m, c th -12V).
Nh th r rng cn mt cu chuyn (converter) kt ni gia 2 chun ny. May
mn l chng ta khng cn phi t thit k cu chuyn ny v c cc IC chuyn
dng. MAX232 l mt trong cc IC chuyn UART-RS232 c s dng nhiu
nht. Tt nhin, bn hon ton c th t to mt mch chuyn n gin ch vi mt
vi linh kin nh t in, in tr, diode v transisotor nhng tnh n nh th ti
khng m bo. Hnh 3 m t cch dng IC Max232 kt ni gia UART trn
AVR v cng COM ca PC.
Hnh 3. Kt ni AVR vi PC thng qua Max232.

Mch in trn ch c tc dng thay i mc in p cho ph hp gia RS232
v UART, n hon ton khng lm thay i phng thc giao tip ca cc chun
ny v v th vic lp trnh trn PC v AVR u khng c g thay i. Tht ra
Max232 c n 2 cu chuyn, trong hnh 3 chng ta ch s dng cu chuyn 1.
Chn pht TxD (chn 3) ca cng COM c ni vi chn R1IN (Receive 1 Input)
ca Max232 th tng ng chn R1OUT (Receive 1 Output) phi ni vi chn
nhn RX ca AVR. Tng t cho trng hp T1IN v T1OUT. Gi tr cc t in
10uF l tng i chun, tuy nhin khi bn thay bng t 1uF th mch vn hot
ng nhng khong cch truyn (cab ni) s ngn hn (nu di qu s pht sinh li
truyn thng). Cc in tr trong hnh 3 ch c tc dng lm bo v cng COM v
cc IC, bn c th khng cn dng cc in tr ny vn khng nh hng hot
ng ca mch. VCC v GND l ngun ca mch AVR.
Ch : nu mun thc hin giao tip gia 2 my tnh vi nhau thng qua cng
COM, bn cn dng1 cab cho (chn TxD ca PC1 ni vi RxD ca PC2 v ngc
li) ni 2 cng COM li vi nhau.
III. To cng COM o cho m phng
Mun thc hin giao tip gia AVR v PC thng qua cng COM th hin nhin
bn cn c ci cng COM, ngoi ra bn cn t lm mt mch AVR v cu chuyn
Max232. Tht khng may l khng phi my tnh no cng c cng ny, nu bn
ch mun hc cch giao tip AVR-PC hoc ch mun kim tra mt gii thut no
th c l m phng l gii php c a thch hn. Cho mc ch m phng giao
tip RS232, Proteus li mt ln na hu ch khi cho php m phng truyn nhn
d liu vi cng COM. Nh th vn cn li l lm sao to cc cng COM o
trn my tnh v kt ni chng vi nhau thc hin m phng giao tip. Do tnh
cht ca cc cng COM l ch c m (open) 1 ln duy nht, ngha l 2 phn
mm khng th cng m 1 cng. tng ca chng ta l to ra 2 cng COM o
c ni cho sn vi nhau (v d COM2 v COM3). Trong phn mm Proteus
ng ra ca UART c ni vi COM2. Trong phn mm trn PC (v d Hyper
Terminal) chng ta kt ni vi COM3. Bng cch ny chng ta c th thc hin
giao tip gia AVR (m hnh Proteus) vi PC (phn mm Hyper Terminal).
C mt vi phn mm tt c kh nng to cng COM o v kt ni o gia
chng ng nh yu cu ca chng ta. Trong phn ny ti s gii thiu 2 phn
mm nh th, trong c 1 phn mm min ph (Virtual Serial Port Emulator) v 1
phn mm thu ph (Eltima Virtual Serial Port Driver).
Virtual Serial Port Emulator (VSPE): l mt phn mm to cng COM v kt
ni o tt ca Eterlogic. iu c bit l phin bn dnh cho Windows 32 bits hon
ton min ph, v vy y l phn mm u tin bn phi khi mun to dng
cho mc ch hc tp.
Trc tin bn hy download phn mm VSPE bn mi nht ti website chnh
thc ca Eterlogic:http://www.eterlogic.com/Products.VSPE.html (nhn vo nt
Download pha cui trang web). Gii nn file zip v chy file SetupVSPE.exe
ci t. Sau khi ci t hy tm v chy chng trnh VSPE. Giao din ca VSPE
nh trong hnh 4.
Hnh 4. Giao din phn mm VSPE.

S dng VSPE kh n gin, bn ch vic nhn vo nt Create New Device
c t trong hnh 4, hoc vo menu Device v chn Create, to 1 cng
COM o. Trong hp thoi Specify device type bn chn nh bn di v nhn
Next. Sau bn c th chn tn cho cng COM mnh mun to trong (v d
COM2).
Hnh 5. To cng COM2 o bng VSPE.

Bn c th tin hnh to bao nhiu cng COM o ty thch. V d bn to 2
cng COM2 v COM3, bc tip theo chng ta s u cho 2 cng ny vi nhau
m phng vic truyn d liu qua RS232. T giao din chnh ca VSPE bn
nhn tip vo nt Create new Device. Ln ny, trong hp thoi Specify
device type bn khng chn Connector na m chn Serial Redirector nh
trong hnh 6. Sau nhn next, chn 2 cng COM o to lc trc v nhn vo
nt Finish.
Hnh 6. To kt ni gia 2 cng COM.

Sau khi hon tt bn s thy cc cng COM o v kt ni gia chng c th
hin trong giao din VSPE nh hnh 7. Bn c th minimize giao din VSPE
n n vo taskbar. Ch l nu bn ng chng trnh VSPE li (tt) th cc
cng COM o cng bin mt.
Hnh 7. Cc cng COM o v kt ni to bng VSPE.

Virtual Serial Port Driver (VSPD): l mt phn mm to cng COM v kt ni
o tt ca Eltima Software. y l phn mm c thu ph, bn c th download bn
dng th 14 ngy ti website chnh thc ca Eltima
Software:http://www.eltima.com/products/vspdxp/
So vi VSPE th VSPD d s dng v n nh hn (v l phn mm thng
mi). Sau khi download bn trial v tin hnh ci t, bn hy tm v chy file
Configure Virtual Serial Port Driver. Giao din ca VSPD nh trong hnh 8.
Hnh 8. Giao din phn mm VSPD.

Trong tab Manager ports phn mm t ng ngh 1 cp cng COM o c
th c to ra, bn c th chn li ty thch v nhn Add pair to 2 cng
COM ny. Khc vi VSPE, cng COM o do VSPD to ra s xut hin trong
Device list ca Windows v khng b mt i khi ngi dng tt phn mm
VSPD. Hy chy trnh Device manager ca Windows, trong mc Ports (COM &
LPT) bn s thy cc cng COM o c to thnh (xem v d trong hnh 9).
Hnh 9. Cc cng COM o v kt ni gia chng c to bi VSPD.

IV. S dng th vin xut nhp chun stdio.h trong WinAVR
Nhng ai tng hc ngn ng lp trnh C chc s khng qun chng trnh
hello world u tin ca
mnh:
Chng trnh ny ch lm 1 vic n gin l in dng ch hello, world ln mn

hnh. Vic in dng ch c thc hin bi lnh printf trong dng 3. Lnh printf
nm trong th vin stdio gi l th vin xut nhp chun (standard input/output).
Lnh printf trong stdio khng ch c dng in ln mn hnh m c th in ln
bt k thit b xut no (output device), ngay c in ra 1 file trn cng my tnh
Cho AVR, nu bn s dng trnh dch CodevisionAVR ca HPinfotech, khi bn gi
lnh printf th chui d liu s c in ra (xut ra) module UART (tt nhin bn
phi ci t cc thanh ghi ca UART kch hot UART trc). Nh th
CodevisionAVR t hiu UART l thit b xut/nhp mc nh cho cc lnh trong
th vin stdio (printf, scanf). Tuy nhin, vi WinAVR (avr-gcc) mi chuyn li
khc, s dng cc lnh xut nhp chun chng ta cn khai bo mt thit b xut
nhp v hm xut nhp c bn. Hm xut nhp c bn l hm do ngi dng
nh ngha, nhim v ca n l xut (hoc nhp) mt k t ra mt thit b xut
nhp no . V d trong bi AVR5 - giao tip UART chng ta nh ngha mt hm
uart_char_tx xut k t ra UART nh sau:
Hoc trong bi TextLCD chng ta kho st hm putChar_LCD xut mt k t ra

LCD nh bn di:
C 2 hm uart_char_tx v putChar_LCD nh v d trn u c th c

dng lm hm xut nhp c bn cho cc hm nh printf...trong th vin xut
nhp chun sdtio. Nu gi s hm uart_char_tx c dng th khi gi hm hm
printf, chui d liu s c xut ra UART. Ngc li, trng hp hm
putChar_LCD c s dng nh hm c bn th hm printf ca stdio s xut
chui d liu ln LCD. Bng phng thc ny, trnh dch avr-gcc cho php chng
ta tip cn th vin stdio mt cch mm do hn, bn c th dng cc hm ca
stdio xut/nhp d liu vo bt k thit b no nh UART terminal, TextLCD,
Graphic LCD hay thm ch SD, MMC cardmt khi bn nh ngha c hm
xut nhp c bn.
minh ha cho cch s dng cc hm trong th vin stdio, ti s trnh by
mt v d xut d liu ra TextLCD v uart bng cc hm printfca stdio. Mch
in m phng cho v d c ny th hin trong hnh 10 bn di.
Hnh 10. M phng v d xut d liu vi th vin stdio.

Tt c cc d liu hin th trn LCD v uart terminal trong hnh 10 u c
thc hin thng qua cc hm printf v fprintf. Ngoi ra trong v d ny, ngi dng
c th nhp 1 k t t bn phm v m ASCII ca phm s c in ra trn
Terminal. on code trnh by trong List1.
List 1. Xut d liu ra LCD v UART bng th vin xut nhp chun stdio
s dng cc hm trong th vin xut nhp chun, chng ta cn include file

header ca th vin nh trong dng code 4 #include <stdio.h>. Ch khi s
dng avr-gcc, cc hm lin quan n avr (avr-libc) nm trong th mc con /avr/
ca th mc include nn khi knh km phi ch r th mc con ny. V d header
io.h hoc interrupt.h cha cc hm chuyn bit cho avr, khi nh km cc file ny
chng ta ghi c th nh: #include <avr/io.h>Tuy nhin, cc file header ca
ngn ng C chun (nh stdio.h, math.h, ) th nm trc tip th mc include,
khi nh km cc file ny phi ghi trc tip nh trong dng code 4. Ngoi ra do v
d ny c s dng LCD, bn cn copy v include th vin myLCD.h nh trong
dng 5 (xem li bi TextLCD).
Nh trnh by trn, s dng cc hm trong stdio chng ta cn c cc
hm xut/nhp c bn. Cc dng code t 7 n 11 l hm xut d liu ra uart c
tn uart_char_tx, hm ny s c dng lm hm c bn cho cc hm xut ca
stdio sau ny. Thc cht hm uart_char_tx c trnh by trong bi hc v
UART, y c mt thay i nh l dng code 8 if (chr==\n)
uart_char_tx(\r), dng ny c ngha l khi gp ngi dng mun xut ra k
t \n th hm uart_char_tx s xut ra thm k t \r . Nh th, nu sau ny
bt gp mt du hiu xung dng \n (c m ASCII l 10, gi l Line Feed LF)
cui cu th mt t hp m '\r'+'\n' (m '\r' = 13 gi l Carriage Return CR) s
c gi thc hin xung dng. nm r hn vn ny bn tm hiu thm
v CRLF (Carriage Return Line Feed) trong Windows.
Hai dng code 13 v 14 rt quan trng khi mun s dng th vin stdio.
ngha ca 2 dng ny l to 2 FILE o (hay cn gi l stream) dnh cho vic
xut d liu. Chng ta kho st dng 14: to stream cho UART.
static FILE uartstd= FDEV_SETUP_STREAM(uart_char_tx,
NULL,_FDEV_SETUP_WRITE);
Chng ta to 1 bin tn uartstd (ngi dng t t tn ty ) c kiu l FILE
(mt dng thit b o), sau dng macro FDEV_SETUP_STREAM khi to
v ci t cc thng s cho uartstd. Macro ny c chc nng m 1 thit b xut
nhp (fdevopen) v gn cc cng c cho vic xut nhp ra thit b.
#define FDEV_SETUP_STREAM(put, get, rwflag)
Cc thng s km theo FDEV_SETUP_STREAM bao gm 1 hm c bn
gi l put, mt hm c bn gi l get v mt c ch chc nng xut hoc nhp
ca thit b c m. C th, trong dng code 13, bin uartstd l mt thit b o
c dng cho vic xut d liu (do thng s _FDEV_SETUP_WRITE). Cng
c xut ra uartstd l hm uart_char_tx m chng ta to pha trn. Khng
c hm nhn d liu v t uartstd (thng s get = NULL). Bn c th hnh dung
th ny: bin uartstd l mt t giy, hm uart_char_tx l mt con du (stamp)
cho php in mt k t ln t giy uartstd. Chng ta gn uart_char_tx cho
usrtstd th sau ny tt c vic in n ln t giy uartstd s do con du

uart_char_tx thc hin. Hm uart_char_tx v th gi l hm xut c bn.
Tng t nh th, trong dng code 13 chng ta to 1 t giy khc
tn lcdstd v hm c bn cho n l hm putChar_LCD, hm ny c nh
ngha sn trong th vin myLCD.h.
Cc dng code trong chng trnh chnh t dng 17 n 25 dng khi ng
UART v TextLCD, bn c th xem li cc bi lin quan hiu thm. Sau khi
khi ng, UART v LCD sn sng cho vic xut d liu. By gi chng ta c
th dng cc hm trong th vin stdio nh printf hay sprint xut d liu. Bn
hay quan st hnh 10 v ti s dng n so snh i chiu vi cc dng code sau.
Dng 27 printf("In lan 1"), mc ch l in chui In lan 1 ln LCD bng hm
printf. Tuy nhin, xem trn hnh 10 bn khng nhn thy chui ny xut hin. Xem
tip dng code 28 fprintf(&lcdstd," www.hocavr.com ") v xem li hnh 10,
ln ny bn thy chui k t www.hocavr.com xut hin trn LCD, ngha l
vic in thnh cng vi hm fprintf. Hm fprintf l hm xut d liu ra mt thit
b o, trong tham s th nht ca hm tr n thit b v tham s th hai l
chui d liu cn in. Trong trng hp ny chng ta dng fprintf xut chui
www.hocavr.com ra thit b o lcdstd v thnh cng. Vy vi hm printf
dng 27 th sao? Hy kho st tip cc dng t 30 n 32. Dng 30 chng ta li
mt ln na dng hm printf printf("In lan 3") in dng In lan 3 ln LCD
nhng vn khng thnh cng (xem LCD trong hnh 10). dng 31 chng ta gn
stdout=&lcdstd trong stdout l mt bin (tht ra l 1 stream hay mt thit b
o) c sn ca ngn ng C, bin ny qui nh thit b mc nh dng cho vic xut
nhp d liu, khi gn stdout tr n lcdstd nh dng 31 ngha l chng ta khai bo
LCD l thit b xut nhp mc nh. V vy, trong dng 32 chng ta gi hm printf
printf("In lan 4: %i", x) chng ta thnh cng. Ln ny, quan st trn LCD
bn s thy dng In lan 4: 8205 xut hin. y 8205 l gi tr ca bin x trong
cu lnh dng 32. Tm li, hm fprintf cho php in trc tip ra mt thit b o
c ch nh trong khi mun dng hm printf chng ta cn gn thit b xut
nhp mc nh trc cho bin stdout. Hy quan st on code t dng 34 n 37 v
ba dng u trong Terminal hnh 10, chc chn bn t l gii c cc dng
code ny.
Cui cng l trnh phc v ngt nhn d liu ca UART trong cc dng code t
41 n 44. Trong trnh ny, chng ta ch thc hin vic n gin l in dng Ma
ASCII: km theo l gi tr nhn v t UART cha trong thanh ghi UDR:
fprintf(&uartstd,"Ma ASCII: %i\n", UDR).
tm hiu y v th vin stdio trong WinAVR bn cn c ti liu avr-libc
Manual, phn Standard IO facilities.
Trong bi 2 chng ta s tm hiu v Terminal trn my tnh v cch vit chng

trnh giao tip trn my tinh bng Visual Basic v Visual C++ 6.
Giao tip AVR vi my tnh (II)
5
( 15 Votes )
Ni dung
Bi 1
Cc bi cn tham kho
C cho AVR.
1.
RS232 Terminal
UART
2.
Lp trnh giao tip vi cng COM bng VB v Visual C++
TextLCD
Download v d
M phng vi Pro
IV. RS232 Terminal

RS232 Terminal l thut ng dng ch cc phn mm my tnh c kh nng
nhn v pht d liu ra cng COM (nh mt thit b u cui). Cc RS232
Terminal rt ha dng kim tra cc chng trnh truyn nhn d liu qua cng
COM. H iu hnh Windows c sn mt RS232 Terminal gi l Hyper
Terminal. Cng c ny kh tt cho mc ch giao tip thng thng. s dng
Hyper Terminal bn hy vo All Programs/ Accessories/Communications/Hyper
Terminal hoc n gin l vo Run v g lnh hypertrm. Mt hp thoi c tn
Connection Description xut hin, hy in mt tn bt k cho cuc gi v nhn
OK. Trong hp thoi tip theo, Connect to, hy chn cng COM m bn mun
giao tip, v nhn OK. Cui cng l hp thoi COM Properties cho php bn thit
lp cc thng s giao tip nh Baudrate, Parity bit, Stop bit nh trong hnh 11, ch
hy chn Flow control l "none"v nhn OK.
Hnh 11. Thit lp cuc gi.

Gi s bn chy chng trnh v d trong phn demo ca stdio, bn thu c
giao din HyperTerminal nh trong hnh 12.
Hnh 12. Giao din Hyper Terminal.

Trong bi hc ny, ti gii thiu mt chng trnh Terminal c tn Hercules ca
HW group (http://www.hw-group.com/products/hercules/index_en.html). y l
mt Terminal min ph rt tt, d s dng v n nh. Ngoi chc nng RS232
Terminal, Hercules cn c dng cho cc giao din khc nh TCP, UDPBn
ch cn download chng trnh v v chy file Hercules.exe. Bn thu c giao
din Hercules nh sau:
Hnh 13. Giao din phn mm Hercules.

Hy chn tab Serial giao tip vi cng COM, thit lp cc thng s nh tn
cng, Baudrate, Data frameri nhn nt Open, bn sn sng s dng
Hercules.
Gi s bn c 3 cng COM o tn l COM2, COM3 ni vi nhau. Hy s dng
v d trong phn stdio, trong mch in m phng Proteus ca v d hy xa thit
b o Terminal. Hy thm vo mt thit b tn l COMPIM bng cch search vi
keyword l COMPIM (hoc chy file AVR_STD_Terminal.DSN trong th mc
AVR_STD ca v d trn). Kt ni nh trong hnh 14. Sau right click vo
COMPIM vo hp thoi Edit component, i thng s Physical port thnh
CM, i Virtual Baud Rate thnh 38400. Chy li m phng bn s thy kt qu
hin th trn Hercules nh trong hnh 14. Type 1 phm bt k thy m ASCII.
y l v d cho php bn giao tip gia chng trnh AVR m phng trong
Proteus v ng dng chy trn Windows thng qua cc cng COM o. N thc
cht l mt dng giao tip my tnh bng cng COM, dnh cho trng hp bn
cha c mch AVR tht. Mu cht nm thit b COMPIM trong Proteus.
COMPIM thc cht l m hnh cng COM tn ti trn my tnh ca bn. Trong
trng hp ny chng ta dng Eltima VSPE (hoc VSPD) to 2 cng COM o
trn my tnh l COM2 v COM3, chng c u cho vi nhau. Chng ta set
COMPIM trong Proteus l COM2 trong khi cng trn Hercules l COM3. Khi
chy m phng, AVR s gi d liu ra COMPIM (tc COM2), COM2 truyn n
COM3 v hin th trn Hercules. Chng ta c th t vit cc chng trnh trn
Windows nhn v gi gi tr qua COM thay cho Hercules. Trong phn tip theo
ti s hng dn bn to chng trnh nh th.
Hnh 14. Kt hp m phng v Hercules.

V. Lp trnh giao tip vi cng COM bng Visual Basic v Visual C++
Cc chng trnh Terminal cp trn l mt dng ng dng giao tip gia
my tnh v vi iu khin mc n gin. Trong nhiu trng hp, yu cu
giao tip i hi mc phc tp cao hn, v d lu tr d liu hay v th bin

thin, th ngi dng cn phi t vit cc chng trnh trn my tnh ca ring
mnh. Phn ny ti hng dn bn cc vit chng trnh trn my tnh truyn v
nhn d liu t cng COM bng 2 ngn ng lp trnh Visual Basic v Visual C++
(6.0) trn nn Windows. Ch , mc ch bi vit ny l v AVR nn phn vit ng
dng trn Windows ti ch trnh by mt cch n gin ct cho bn nm c
nguyn l. pht trin cc ng dng phc tp hn ngi c cn t trang b cho
mnh kin thc v lp trnh trn Windows. Trong tt c cc hng dn bn di ti
gi s l ngi c t nht bit c cch to Project trong Visual Basic hoc/v
Visual C++.
1. Vit chng trnh giao tip cng COM bng Visual Basic 6.0
K t cc phin bn Windows 2000 v sau, vic giao tip vi cc cng my tnh
truyn thng, nh cng LPT, trong Windows tng i kh khn. Tuy nhin, vi
cng COM th c iu may mn l Microsoft c cung cp mt cng c (tht ra l
mt control iu khin) c tn gi l Microsoft Communication Control hay
vit tt l MSComm. MSComm xut hin trong cc phn mm lp trnh ni ting
ca MS nh Visual Basic hay Visual C++ di dng mt iu khin. V l mt
iu khin c thit k sn cho cng COM nn MSComm cha tt c cc cng
c cn thit giao tip vi cng ny, cng vic ca ngi vit chng trnh ch
n gin l khai bo v s dng. minh ha cch s dng MSComm trong
Visual Basic, hy lm theo hng dn bn di.
Chy Visual Basic 6, vo menu File/New Project v to mt Standard EXE.
Bn s thy mt Project c tn l Project1 km mt hp thoi nn (form chnh)
c tn Form1 xut hin. Bn c th t tn bt k cho Project v form chnh. Hy
quan st v d trong hnh 15. T thanh cng c Toolbox hy click vo control
textbox v v ln form chnh 2 textbox tn l txtOuput v txtInput (xem hnh
15) (i tn cc textbox trong ca s Properties nm gc thp, bn phi). vi
txtOutput, hy set thng s Multiple thnh True v ScrollBars thnh 3 Both
Hnh 15. Giao din Visual Basic 6.

Tip theo hy a control MSComm vo form chnh. Theo mc nh, control
MSComm khng c sn trong Toolbox ca Visual Basic, chng ta cn thm vo
Toolbox trc khi s dng. thm MSComm vo Toolbox, chn Menu
Project/Components bn s thy mt hp thoi tn Components xut hin nh
trong hnh 16. Tm v click chn vo Microsoft Comm Control 6.0 nh trong
hnh v nhn OK. Lc ny, quan trong Toolbox ca VB bn s thy icon ca
MSComm xut hin. Click vo icon ny v v 1 i tng MSComm ln form
chnh (xem li hnh 15). Gi tn mc nh ca i tng ny l MSComm1.
Hnh 16. Thm cng c MSComm vo Project.
Vit code:
Mc ch ca v d ny nh sau: d liu nhn v t cng COM s hin th trn
textbox txtOutput, v khi ngi dng type 1 k t vo txtInput k t s c
truyn i qua cng COM.
Trc ht, hy doubleclick vo form chnh, vit on code sau vo s kin
Form_Load():
Mc ch ca on code ny l ci t cc thng s cho MSComm1.

- Thng s CommPort = 3 ngha l chng ta mun kt ni vi cng COM3.
Thng s ny do ngi dng thay i ty theo cng COM chng ta mun giao
tip.
- Thng s Setting = 38400, N, 8,1 ngha l tc Baud=38400, khng s
dng bit Parity, di khung truyn bng 8 v c 1 bit Stop.
- RThreshold = 1 ngha l khi c 1 k t n cng COM, ngt nhn d liu s
xy ra.
- InputLen = 1 ngha l khi c d liu t b m nhn, chng ta s c ln
lt 1 k t (1 byte).
- PortOpen = True tc cho php m cng COM sn sng giao tip.
Tip theo, doubleclick vo biu tng ca MSComm1 trn form chnh vit
code vo s kinMSComm1_onComm():
S kin onComm() thc cht l trnh phc v ngt nhn d liu ca

MSComm. Khi c 1 byte d liu gi n b m ca cng COM (s lng byte do
RThreshold quy nh) th s kin onComm s xy ra (ngt xy ra), trong s kin
ny chng ta s vit code nhn v x l d liu. Dng 2 chng ta khai bo 1
bin tm thi tn l InputText vi kiu d liu string. Ch l s kin onComm c
th xy ra do nhiu nguyn nhn, y chng ta ch quan tm n trng hp d
liu truyn n, dng 3 l mt dng lc s kin, chng ta ch thc hin cc dng
code bn trong khi m s kin comEvReceive xy ra (d liu c nhn v): If
Me.MSComm1.CommEvent = comEvReceive Then. Vic quan trng duy nht
c d liu c gi n COM l c b m Input ca MSComm nh trong
dng code 4: InputText = MSComm1.Input. Sau dng lnh ny d liu s c
cha trong bin tm InputText. Tip theo chng ta ch cn cng dn cc k t nhn
v vo ni dung ca Textbox txtOutput hin th ln mn hnh (dng
5) : txtOutput.Text = txtOutput.Text + InputText. Dng code 6 lm nhim v
a con tr n cui ni dung ca txtOutput tin cho vic quan st d liu.
Cui cng, doubleclick vo Textbox txtInput v tm s kin KeyPress vit cc
dng code sau:
S kin txtInput_KeyPress xy ra khi ngi dng nhn 1 phm no vo

txtInput. Dng codeMe.MSComm1.Output = Chr(KeyAscii) thc hin vic gi
gi tr ca KeyAscii ra cng COM, trong KeyAscii l m Ascii ca phm c
nhn.
Bn hon tt vit chng trnh truyn nhn d liu qua cng COM bng
Visual Basic. kim tra chng trnh ca bn, hy thc hin m phng theo cc
bc sau:
- Dng 1 trong 2 phn mm VSPD hoc VSPE to 2 cng COM o l
COM2 v COM3, u cho chng vi nhau (xem li phn cng COM o).
- Tm trong th mc cha v d AVR_STD v chy file m phng bng phn
mm Proteus AVR_STD_Terminal.DSN.
- Quay li Visual Basic, nhn nt Run hoc F5 chy Project va mi vit.
- Nhn Run trong Proteus m phng mch
in AVR_STD_Terminal.DSN. Bn s thy kt mt s text xut hin trng
txtOutput nh trong hnh 17. Click vo txtInput v type bt k mt phm no
xem kt qu. So snh vi m phng trong hnh 14 bn thy nt tng ng. Nh
th bn thnh cng khi t vit cho mnh 1 ng dng giap tip vi cng COM
bng Visual Basic.
2. Vit chng trnh giao tip cng COM bng Visual C++ 6.0
Phn ny chng ta s thc hin mt v d truyn nhn qua cng COM tng t
nh v d phn trn nhng s dng Visual C++ (VC++) ca Microsoft. Mc ch
chnh l hng dn cch s dng MSComm trong VC++, v th ti s trnh by rt
s si nhng phn nh to Project trong VC++. Bn c cn t trang b thm kin
thc v lp trnh VC++. Mt trong nhng ti liu rt hay cho ngi mi hc lp
trnh VC l Teach Yourself Visual C++ 6 in 21 Days ca Sams Teach
Yourself, bn c th tm c nu thy cn thit.
T VC++ hy vo menu File/New to 1 Project mi. Chn loi Project l
MFC AppWizard (exe), trong Project Name t tn cho Project l AVR_PC,
nhn OK. Trong hp thoi th 2 hy chn Dialog based cho loi Project, v nhn
Finish to Project (cc bc khc mc nh).
Hnh 17. To Project MFC trong VC++6.
Khi Project mi c to s c 1 hp thoi chnh (Dialog) xut hin vi 2

button OK v Cancel trn . Dng cng c Edit thm vo 2 Edit box
v sp xp li giao din nh hnh 19. Right click vo cc Edit box v chn
Proterties t cc Popup_menu, ln lt i ID ca 2 Edit box thnh IDC_OUTPUT
v IDC_INPUT.
Cng ging nh trong VB, Control MSComm khng xut hin mc nh trong
Toolbox ca VC++, chng ta cn thm vo khi mun s dng control ny. Hy vo
menu Project/Add to Project/ Components and Controls. Khi hp thoi
Components and Control Gallery xut hin bn chn vo th mc Registered
ActiveX Controls v tm n file Microsoft Communications Control, Version
6.0 ri nhn nt insert, nhn OK khi c hi bt k cu hi g, sau nhn nt
Close ng hp thoi li. Lc ny icon ca MSComm s xut hin trong
Toolbox ca VC++ nh trong hnh 19. Click chn icon ca MSComm v v 1
control vo Dialog chnh ca Project. Theo mc nh Control ny c tn
IDC_MSCOMM1.
Hnh 18. Thm Control MSComm vo Toolbox trong VC++.
Hnh 19. Giao din chng trnh trong Visual C++.

Vic lp trnh trong VC++ tng i kh hn VB (cho ngi mi tm hiu).
Cc thuc tnh ca cc Control nh Edit box khng c truy cp trc tip nh
Textbox trong VB. V d gn v hin th mt chui hay s ln Edit box chng ta
phi thc hin gn v cp nht d liu qua cc bin trung gian. bc ny chng
ta i to 2 bin cho 2 Edit box. Nhn vo menu View/ClassWizard hoc t hp
phm Ctrl+W , trong hp thoi MFC ClasWizard hy chn tab Member
Variables. Click vo dng IDC_OUTPUT (chnh l edit pha trn), nhn vo nt

Add vatiable v in tn bin l m_txtOutput vi kiu bin
l CString nh trong hnh 20. Lp li cc bc trn to 1 bin tn
m_txtInput cho IDC_INPUT. Cui cng l to 1 bin c tn m_comm cho
IDC MSCOMM1. Nhn OK ng hp thoi MFC ClassWizard. T by gi,
chng ta ch cn nh 3 bin m_txtOutput, m_txtInput, m_comm khi
mun truy cp cc Edit boxes v MSComm trong lc vit code.
Hnh 20. To bin txtOutput cho Edit box IDC_OUTPUT.

Vit Code:
Nhn Ctrl+W m li ClassWizard, ln ny chn tab Message Maps",
trong Class name m bo rng CAVR_PCDlg c chn. Trong

Object IDS hy chn "CAVR_PCDlg, Messages tm v chn
"WM_INITDIALOGS sau nhn vo nt Edit Code (xem hnh 21).
Hnh 21. Bt u vit code.

By gi bn c th vit code cho s kin OnInitDilaog(), y l s kin xy
ra khi bn chy chng trnh v Dialog chnh c khi ng. V th chng ta s
ci t cc thng s cho m_comm vo y (m_comm l tn bin i din cho
control IDC_MSCOMM1 m chng ta to cc bc trn). Hy thm cc
dng sau vo sau dng // TODO: Add extra initialization here:
Nm dng code trn tng ng vi 5 dng trong phn Form_Load() khi vit
Project bng VB m chng ta kho st trn, v th ti khng cn gii thch
thm cho cc dng code ny.
Tip theo chng ta s vit code cho s kin onComm (ngt nhn) ca control
MSComm, trc khi vit code hy nhnCtrl+W hin hp thoi ClassWizard v
thc hin 6 bc nh trong hnh 22 thm s kin onComm vo Project.
Hnh 22. Thm s kin onComm nhn d liu t cng COM.

Vit on code sa vo s kin onComm:
Nh trnh by trn, m_comm l bin i din cho MSComm vic thao tc

vi cng COM by gi thc hin thng qua bin m_comm. Trong dng 4 chng ta
khai bo 1 bin ph strInput c kiu CString dng cha gi tr nhn v sau ny.
Cng ging nh trong VB, s kin onComm c th xy ra do nhiu nguyn nhn,
chng ta ch quan tm n trng hp c d liu n b m, dng 5 cho php
lc ra s kin cn thit: if (m_comm.GetCommEvent()==2 ). Dng 6 chng ta
khai bo 1 bin ph tn in_dat vi kiu COleVariant. COleVariant l lp (class)
ca MFC, tn gi ca n l s kt hp ca C + OLE +VARIANT trong OLE l
Object Linking Embedded l mt kiu i tng khng c sn m c
nhng vo, MSComm l mt loi OLE. VARIANT l mt kiu bin cha xc
nh. Khi bn c mt bin x, i khi bn mun gn gi tr s cho x nhng cng c
khi bn li mun gn chui k t cho x. Khi hy khai bao x l VARIANT.
Trong trng hp MSComm, d liu vo v ra ca i tng ny thuc dng
cha xc nh hay VARIANT. Trong dng 7 chng ta ch n gin nhn gi tr t
m_comm v bin in_dat: in_dat = m_comm.GetInput(). Dng tip theo chng ta
trch thnh phn chui k t t bin in_dat v gn cho bin
strInput:strInput=in_dat.bstrVal (mt cch tng i c th hiu i in_dat thnh
CString v gn cho strInput). Chng ta phi trch CString v cc Edit box ch hin
th c CString. hin th d liu nhn v ln Edit box (IDC_OUTPUT) chng

ta cng dn bin m_txtOutput (bin i din ca Edit box IDC_OUTPUT) bng
dng lnh 9:m_txtOutput+=strInput. Cui cng, cho gi tr ca bin
m_txtOutput cp nht ln Edit box chng ta phi gi hm UpdateData vi tham s
FALSE nh dng 10: UpdateData(FALSE) (y l cch lm vic ca Visual C++).
Cc dng code t 12 n 14 c dng vi mc ch a con tr v cui dng
ca Edi box sau khi kt thc qu trnh nhn d liu. Bn c th b qua nu thy
khng cn thit.
Vic cui cng l vit code cho Edit box bn di (IDC_INPUT) khi chng
ta g (type) vo y, k t s c gi n cng COM. Nhn Ctrl+W v thc hin
cc bc bn di thm vo s kin onChange.
Hnh 23. Thm s kin onChange cho IDC_INPUT.

Hy vit on code sau vo s kin onChange ca Edit box Input:
Khi ngi dng type 1 k t no vo Edit box, s kin onChange xy ra, khi
chng ta s trch k t cui cng trong ni dung ca Edit box bn di m i
din l bin m_txtInput bng dng lnh 11: tmpStr=m_txtInput.Right(1).Trong
tmpStr l mt bin tm khai bo dng 9. Ch rt quan trong khi mun c
ni dung ca Edit box chng ta cn gi hm UpdateData vi tham s TRUE trc
nh trong dng 10. Sau cng, gi phng phng thc SetOutput ca i tng
MSComm gi gi tr ra cng
COM: m_comm.SetOutput(COleVariant(tmpStr)). gi mt k t (hay chui
k t) ra cng COM trc ht chng ta cn p kiu k t v COleVariant v
nh trnh by, MSComm ch lm vic vi COleVaraint.
on COleVariant(tmpStr) thc hin vic p kiu ny.
Sau khi vit xong on code cho s kin onChange bn c th nhn t hp
phm Ctrl+F5 chy chng trnh. Dng mch
in AVR_STD_Terminal.DSN v chy m phng nh trong phn lp trnh vi
VB. Kt qu thu c s nh trong hnh 24.
Hnh 24. Giao tip gia AVR v Visual C++.

Mi bn tham kho thm phn mm gCOM, mt cng c giao tip, lu tr d
liu v v th cng COM
C cho AVR
5
( 109 Votes )
Ni dung
1.
Mt s khi nim C cho AVR.
Lm quen AVR.
2.
Cu trc iu khin v hm.
Cu trc AVR.
3.
V d minh ha.
WinAVR.
Nh ti trnh by cc bi hc trc, khi bn hiu AVR, thc hin

cc ng dng, bn c th khng nht thit phi lun lp trnh bng
Assembly(ASM). Ngn ng cp cao nh C s gip cho bn xy dng cc ng
dng nhanh chng v d dng hn, tuy nhin khng v th m bn qun ASM,
lp trnh bng C kt hp ASM l gii php hay nht. Mt ch l chng ta ch
s dng C n gin ha lp trnh tnh ton, cu trc iu khinlp trnh C
cho AVR khng c ngha l bn khng cn bit cu trc v cch thc hot ng
ca chip. Ti khng c nh ni v ngn ng C y nhng ch gii thiu
mt cch c bn nht v cch vit chng trnh cho AVR bng C, c th l C
trong avr-gcc. c th hiu v vit nhng chng trnh phc tp hn, bn cn
t trang b kin thc v C, ti liu ny s khng gip bn phn . Tuy nhin,
nu bn cha tng lp trnh bng C th bn cng yn tm c ti liu ny, v t ra
ti s gii thch nhng g ti vit.
I. Mt s khi nim C cho AVR.
Mt chng trnh C cho AVR thng bao gm cc thnh phn nh: ch

thch (comments), biu thc (expressions), cu lnh (statements), khi (blocks),
ton t, cu trc iu khin (Flow controls), hm (functions)
Ch thch (comments): c 2 cch to phn ch thch trong C l ch thch
tng dng bng 2 du // nh trong dng u ca on v d //day la chu thich,
khong duoc bien dich hoc ch thch block bng cch kp block cn ch thch vo
gia /* .*/ v d:
/*
Ban co the type bat ky chu thich nao trong block nay
Ngay ca khi ban xuong dong
Phan chu thich thuong co mau chu la green
*/
Tin x l (preprocessor): l mt tin ch ca ngn ng C, cc preprocessor
c trnh bin dch x l trc tt c cc phn khc, cc preprocessor c chc
nng tng t cc Directive trong ASM cho AVR.Cc preprocessor c bt u
bng du #, trong s cc preprocessors trong ngn ng C c hai preprocessors
c s dng ph bin nht l#include v #define. Preprocessor #include ch nh
1 file c nh km trong qu trnh bin dch (tng ng .INCLUDE trong
ASM) v #define nh ngha 1 chui thay th hoc 1 macro. Xem cc v d sau:
#include "avr/io.h" *nh km ni dung file io.h trong lc bin dch (file io.h
nm trong th mc con avr ca th mc include trong th mc ci t ca
WinAVR).*/
#define max (a,b) ((a)>(b)? (a): (b)) /*nh ngha mt macro tm s ln nht
trong 2 s a v b, trong chng trnh nu bn gi x=max(2,3) th kt qu thu
c x=3.*/
Biu thc (Expressions): l 1 phn ca cc cu lnh, biu thc c th bao
gm bin, ton t, gi hm, biu thc tr v 1 gi tr n. Biu thc khng phi
l 1 cu lnh hon chnh. V d: PORTB=val.
Cu lnh (Statement): thng l 1 dng lnh hon chnh, c th bao gm cc
keywords, biu thc v cc cu lnh khc v c kt thc bng du ;. V d:
unsigned char val=1; val*=2; l cc cu lnh.
Khi (Blocks): l s kt hp ca nhiu cu lnh thc hin chung 1 nhim
v no , khi c bao bi 2 du m khi { v ng khi }: v d 1 khi:
while(1){
PORTB=val;
val*=2;
if (!val) val=1;
}
Ton t (Operators): l nhng k hiu bo cho trnh bin dch cc nhim v

cn thc hin, cc bng bn di tm tt cc ton t C dng cho lp trnh AVR:
Bng 1 cc ton t i s: dng thc hin cc php ton i s quen thuc,

trong ng ch l cc ton t ++ (tng thm 1) v -- (bt i 1), ch phn
bit y=x++ v y=++x, v d ta c x=3 trong khi y=x++ ngha l gn x cho y ri
sau tng x thm 1, iu ny khng nh hng n y (cui cng y=3, x=4) trong
khi y=++x ngha l tng x trc ri mi gn cho y (cui cng y=x=4), tng t cho
cc trng hp ca ton t -- .
Bng 2 Ton t truy cp v kch thc: ton t [] thng c s dng khi

bn dng mng trong lc lp trnh, phn t th ca mng s c truy xut thng
qua [i], ch mng trong C bt u t 0.
Bng 3 Ton t Logic v quan h: thc hin cc php so snh v logic,

thng c dng lm iu kin trong cc cu trc iu khin, ch ton t so
snh bng ==, ton t ny khc vi ton t gn =, trong khi y = x ngha l ly
gi tr ca x gn cho y th (y== x) ngha l nu y bng x.
Bng 4 Ton t thao tc Bit (Bitwise operator): l cc ton t thc hin

trn tng bit nh phn ca cc con s, cc ton t dch tri << v dch phi
">>" rt thng c s dng khi x l s.
Bng 5 cc ton t khc: l 1 s ton t c bit rt hay s dng nhng

chng ta thng khng v vai tr ca chng rt d nhn thy. c bit ch
ton t ?: l 1 ton t rt c bit ca C so vi cc ngn ng lp trnh khc, ?:

l ton t 3 ngi duy nht c th dng thay th cho cu trc if n gin.
II. Cu trc iu khin v hm.

2.1 Cu trc iu khin (Flow Controls).
Cc cu trc iu khin bin tng ca bn thnh hin thc. Mt s cu trc
iu khin c bn trong C nh sau:
If (iu kin) statement;: nu iu kin l ng th thc hin statement
theo sau, statement c th c trnh by cng dng hoc dng sau iu khin If.
iu kin c th l mt biu thc bt k, c th l s kt hp ca nhiu iu kin
bng cc ton t quan h AND (&&), OR (||)iu kin c cho l ng khi n
khc 0, v d if (1) th iu kin hin nhin l ng. Xt mt vi v d dng cu
trc if nh sau:
If (!val) val=1; ngha l nu val bng 0 th chng trnh s gn cho val gi tr
l 1, ! l ton t NOT, NOT ca mt s khc 0 th bng 0, ngc li, NOT ca 0
th thu c kt qu l 1. Trong v d ny, nu val bng 0 th !val s bng 1, nh
th iu kin s tr thnh ng v cu lnh val=1 c thc thi.
If (x==1 && y==2) result=A; ngha l nu x bng 1 v y bng 2 th gn k
t A cho bin result. Trong v d ny, ton t logic && c s dng ni
2 iu kin li, bn hon ton c th s dng nhiu ton t logic khc nu cn thit.
Trong trng hp bn mun thc thi nhiu cu lnh cng lc nu mt iu kin
no tha th bn cn t tt c cc cu lnh trong 1 khi nh bn di:
If (iu kin) {
Statement1;
Statement2;
If (iu kin ) statement1; else statement2; : nu iu kin ng th thc

hin statement1, ngc li thc thi statement2. Vic t cc statement v else..trn
cng 1 dng hay trn nhng dng khc nhau u khng nh hng n kt qu.
Tng t trng hp trn, nu c nhiu statements th cn t chng trong 1 khi.
If (iu kin) {
Statement1;
Statement2;
}else {
Statement1;
Statement2;
}
Ngoi ra, bn cng c th t nhiu cu trc ifelse lng vo nhau.
Cu trc switch: trong trng hp c nhiu kh nng c th xy ra cho 1 biu
thc (hay 1 bin), ng vi mi kh nng bn cn chng trnh thc hin mt vic
no , khi ny bn nn s dng cu trc switch. Cu trc ny c trnh by nh
bn di.
switch (biu thc) {
case hng_s_1:
cc statement1;
break;
case hng_s_2:
cc statement2;
break;
default:
cc statement khc;
}
Hy xt 1 v d bn kt ni 2 chip AVR vi nhau, 1 chip lm Master s ra cc
lnh iu khin chip Slave, chip Slave nhn m lnh t Master v thc hin cc
cng vic c tho hip trc. Gi s m lnh c lu trong bin Command,
di y l chng trnh v d cch x l ca chip Slave ng vi tng m lnh.
switch (Command) {
case 1:
PWM=255;
ON_Motor();
break;
case 2:
PWM=0;
OFF_Motor();;
break;
default:
Get_Cmd();
break;
}Ngoi ra, bn cng c th t nhiu cu trc ifelse lng vo nhau.
Nu Command=1, gn gi tr 255 cho bin PWM v gi chng trnh con
ON_Motor(). Trong trng hp ny, break c s dng, break ngha l thot khi
cu trc iu khin hin ti ngay lp tc, nh vy sau khi thc hin 2 lnh, switch
kt thc m khng cn xt n cc trng hp khc. By gi, nu Command=2,
gn gi tr 0 cho bin PWM v gi chng trnh con OFF_Motor(), trong tt c cc
trng hp cn li (default), thc hin chng trnh con Get_Cmd().
while (iu kin ) statement1;: l mt cu trc lp (Loop), ngha ca cu
trc while l khi iu kin cn ng th s thc hin statement1 (hoc cc
statements nu chng c t trong 1 khi {} nh trong trng hp ca if c
gii thiu trn). Cn thn, bn rt d ri vo mt vng lp khng li thot vi
while nu iu kin lun lun ng.
for (biu_thc_1; biu_thc_2; biu_thc_3) statement;: l mt cu trc
lp khc, trong cu trc for, biu_thc_1 thng c hiu l khi to,
biu_thc_2 l iu kin v biu_thc_3 l biu thc c thc hin sau. Cu trc
for ny tng ng vi cu trc while sau:
biu_thc_1;
while (biu_thc_2){
statement;
biu_thc_3;
}
Cc biu thc trong cu trc for c th vng mt trong cu trc nhung cc
du ; th khng c b. Nu bn vit for( ; ; ) tng ng vi vng lp v tn
while (1).
Cu trc for thng c dng thc hin 1 hay nhng cng vic no
trong s ln no , v d bn di thc hin xut cc gi tr t 0 n 200 ra
PORTB, sau mi ln xut s gi lnh delay trong 65000 chu k my.
for (uint8_t i=0; i<=200; i++){
PORTB=i;
}
Ch , bn c th thc hin vic khai bo 1 bin (xem phn khai bo bin bn
di) ngay trong cu trc for nu bin ln u c s dng. V d trn c hiu
nh sau: khai bo 1 bin i kiu byte khng m, gn gi tr khi u cho i=0 (ch
thc hin 1 ln duy nht), kim tra iu kin i<=200 (nh hn hoc bng 200), nu
iu kin cn ng, thc hin 2 statements trong block {}, sau quay v thc
hin i++ (tng i thm 1) ri li kim tra iu kin i<=200 v qu trnh lp li. Nh
th on code trong {} c thc thi khong 201 ln trc khi bin i bng 201 v
iu kin i<=200 sai.
2.2 Hm (Functions).
Ngn ng C bao gm tp hp ca rt nhiu hm, mi hm thc hin mt chc
nng c th, cc hm trong C thng c thit kt rt nh gn, c cc hm
phc tp ngi dng cn t to ra. Hm C cho AVR c nh ngha trong th vin
avr-libc, ngoi cc hm C thng thng, avr-libc cn cha rt nhiu cc hm ring
dng ring cho chip AVR, cc hm ny c khai bo trong cc file header ring,
s dng hm no, bn cn #include file header tng ng (tham kho ti liu
avr-libc user manual bit thm chi tit, trong ti liu ny, khi cn s dng mt
hm no ti s ni r file header cn thit).
V d: _delay_loop_2(65000) l mt hm c nh ngha trong file delay.h
(trong th mc C:\WinAVR\avr\include\util), hm ny thc hin vic delay khong
65000 chu k my. C 4 hm delay bn c th s dng sau khi include file l:


(Ch : thc cht 2 hm delay trn c nh ngha trong file header

delay_basic.h).
_delay_us(double __us): delay 1 microsecond.
_delay_ms(double __ms): delay 1 milisecond.

Ch : dng 2 hm _delay_us v _delay_ms cn nh ngha tn s xung
clock trong Makefile (bin F_CPU), s dng 2 hm ny trc tip thng cho kt
qu khng nh mong mun, ti s trnh by cch s dng 2 hm ny trong v d
bn di.
Main: mt chng trnh C cho AVR phi bao gm 1 chng trnh chnh main,
tt c cc ni dung chnh s c t bn trong chng trnh chnh. Cu trc
chng trnh chnh c th nh sau:
int main(void){
//noi dung chinh
return 0; //gia tri tra ve cho chuong trinh chinh
}
Trong , int l kiu gi tr tr v ca main, t kha void ni rng chng
trnh chnh ca chng ta khng cn bt k tham s no km theo.
Cn rt nhiu cc vn lin quan n C cho AVR, chng ta s tm hiu trong
lc vit cc v d c th.
III. V d minh ha.
minh ha cc khi nim v phng php lp trnh C cho AVR, ti s gii
thch v d qut LED vit bng C m chng ta thc hin trong bi hng dn
WinAVR. on code c trnh by trong List 1.
List 1. v d qut LED bng C.
1
2
3
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//file: main.c
//Description: Cung hoc avr, www.hocavr.com
#include <avr/io.h>
#include <util/delay.h>
unsigned char val=1;
int main(void){
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15 }
DDRB=0xFF; //x dng PORTD lm ng xut d liu

while(1){
PORTB=val;
val*=2;
if (!val) val=1;
}
return 0;
Trc ht l preprocessor nh km cc file khi bin dch, #include l nh

km file header io.h, file ny thc ra khng phi l file cha cc thng tin v chip
nhng n s lm mt nhim v trung gian l nh km 1 file khc tng ng vi
bin MCU trong Makefile, v d trong Makefile, MCU=atmega8 th dng
#include c thc thi, file iom8.hc t ng nh km km vo v file
iom8.h mi thc cht cha cc nh ngha cho chip ATmega8 (cc nh ngha v
a ch thanh ghi, kch thc b nh,). iu ny gip bn khng cn nh ht tt
c cc file header ca tng chip AVR. Nu khng an tm, bn c th thm
dng #include iom8.h sau khi include io.h (iu ny khng tht s cn thit).
Ngoi ra, mi ln include file io.h s c 4 file header khc c t ng nh
km l avr/sfr_defs.h, avr/portpins.h, avr/common.h, v
avr/version.h. Tm li bn cn (hoc phi) include file io.h v khai bo loi
chip AVR trong file Makefile (dng MFile, nh hng dn trn) l c th an
tm vit chng trnh C cho AVR.
- Dng th 4 include file header delay.h s dng lnh delay nh cp
trn.
- Dng 5 : khai bo 1 bin tn val trong b nh SRAM, kiu ca val l
unsigned char l kiu d liu 8 bit khng du c khong gi tr t 0 n 255. Bin
val c dng lm bin tm cha gi trc khi xut ra PORTB. Bin trong C
c khai bo bng cch t kiu bin trc sau tn bin. Mt s kiu d liu
c bn trong C c tm tt trong bng 6.
Bng 6 cc kiu d liu trong C.
type)
Khong d liu (Range)
char
127 to 127 or 0 to 255

type)
Khong d liu (Range)
unsigned char
0 to 255
signed char
127 to 127
int
32,767 to 32,767
unsigned int
0 to 65,535
signed int
Nh kiu int
short int
Nh kiu int
unsigned short int
0 to 65,535
signed short int
Nh kiu short int
long int
2,147,483,647 to 2,147,483,647
signed long int
Nh kiu long int
unsigned long int
0 to 4,294,967,295
long long int
(2631) to 2631 (C99 only)
signed long long int
same as long long int (C99 only)
unsigned long long int 8
0 to 2641 (C99 only)
float

type)
Khong d liu (Range)
double
long double
12
Mt s kiu d liu thng dng nht l char (1 byte), int (2 byte) v float. T
kha unsigned c thm trc 1 kiu d liu nguyn ch nh cc s nguyn
dng, khi khong gi tr nguyn s c tng ln gn 2 ln. V d char ch cc
s nguyn t -127 n 127 thng c dng ch m ASCII ca cc k t trong
bng m ASCII, nhng unsigned char s bao gm cc s nguyn dng t 0 n
255 v thng c dng khi lm vic vi cc thanh ghi 8 bit.
Ngoi ra, avr-libc cn nh ngha mt s kiu d liu thay th, chng ta c th
dng cc kiu d liu ny thay cho cc kiu thng thng, xem tm tt nh bn
di.
Mt khai bo uint8_t val tng ng usigned char val, s dng kiu khai
bo no l do thi quen ca ngi s dng. Ch l theo mc nh, mt bin mi
c khai bo theo cch thng thng nh trn s c t trong SRAM, nh cc
bn bit SRAM trong AVR tng i nh v th nn khai bo v s dng hp l
bin, ng khai bo qu nhiu bin nu bn khng s dng ht, ng khai bo kiu
bin qu ln so vi gi tr tht s dng, tuy nhin cng khng c khai bo kiu
d liu c kch thc qu nh so vi gi tr m bin c th vn ti. S dng b
nh chng trnh (flash program memory) lu tr d liu khng i l mt k
thut khc tit kim b SRAM, ti s cp vn ny trong 1 bi khc.
Cui cng v vic khai bo bin, mt bin c th c gn gi tr khi to

ngay lc khai bo nh trong trng hp ca chng ta, bin val=1 lc c khai
bo.
- Dng 6 int main(void){ bt u chng trnh chnh.
- Dng 7: DDRB=0xFF gn gi tr hexadecimal 0xFF (11111111) cho thanh
thi iu khin ca Port B, DDRB, Port B khi s tr thnh Port xut
- Dng 8 while (1){: bt u 1 vng lp v tn.
- Dng 9 v dng 10: xut val ra PORTB v gi lnh delay.
- Bn cn ch 11 v 12, 2 dng ny c chc nng xoay gi tr ca bin val
xut ra PORTB to hiu ng xoay vng. val*=2 c hiu l val=val*2, y l
1 kiu vit thu gn ca C, nu ton hng th nht v kt qu tr v l cng 1 bin,
chng ta c th b bt 1 tn bin v di chuyn ton t v bn phi ton t gn =.
V d: i = i + 6 c rt gn thnh i + = 6.
Nh th sau cu lnh val*=2 gi tr ca val c tng ln 2 ln. ngha tht

s ca vic gp i bin val l g? Hy nhn vo gi tr nh phn ca val, lc khai
bo val, chng ta gn cho val = 1 hay val = 00000001 (nh phn), sau khi gp i
ln th nht, val = 2=00000010, tip tc gp i ln th hai, val = 4=00000100
c th bn thy chuyn g xy ra? y l cu tr li: trong thao tc vi s nh
phn, gp i mt s ngha l di chuyn s sang tri 1 v trQu trnh gp i
s tip din n lc val = 128=10000000, nu tip tc gp i, bn ngh val = 256 ?
Tuy nhin bn nh rng chng ta khai bo bin val c kiu unsigned char (8
bits), trong khi 256=100000000 (9 bits), nu gn val = 256, ch c 8 bits thp
(00000000) ca 256 s c gn cho val, kt qu l val = 0. Ni mt cch khc,
sau khi val=128, val = 0, cu lnh: if (!val) val=1; s gip cho qu trnh qut
lp quay li t u nu val = 0. Mi th r.
Cui cng v chng trnh chnh ca chng ta c kiu int (int main) chng ta
cn tr v mt gi tr no , return 0; thc hin tr v 0 (bn c th tr v gi
tr no ty ).
Assembly cho AVR
5
( 31 Votes )
Ni dung
1.
Instruction ch dng cho Register Files.
2.
Instruction cho cc thanh ghi I/O.
3.
Cc con tr X, Y, Z v cch truy cp ton b khng gian b nh.
4.
R nhnh v vng lp.
Cc bi cn tham kh
Lm quen AVR.
Cu trc AVR
WinAVR
Phn ny ti gii thiu mt s instruction m chng ta rt hay s dng khi

lp trnh cho AVR. Ti s chia cc instruction ny ra thnh nhiu nhm da theo
phm vi tc ng v chc nng ca chng.
Trc ht chng ta thng nht mt s cch s dng k hiu trong cch vit
c php ca cc instruction nh sau:
Rd: thanh ghi ngun v cng l ch thuc Register File.
Rr: thanh ghi ngun thuc Register File.

Khi nim ngun (Source), ch (Destination) l ch cc ton hng v kt qu trong
cc php ton i s v Logic, v d ADD R1, R2 l lnh cng 2 gi tr cha trong
2 thanh ghi R1, R2, trong trng hp ny c R1 v R2 u c gi l ngun v
cha gi tr trc khi thc hin php cng. Sau khi php cng c thc hin, kt
qu c cha li trong R1 v v th R1 c gi l ch trong trng hp ny. R1

va l ngun, va l ch trong khi R2 ch l ngun, nu vit v d ny di dng
tng qut s l : ADD Rd, Rr.
R: kt qu sau khi lnh c thc thi.
K: hng s.
k: hng s ch a ch tuyt i ca thanh ghi.
b: (0 n 7) s th t bit trong cc thanh ghi ca Register File v vng nh

I/O.
s: (0 n 7) s th t bit trong thanh ghi trng thi SREG.
X,Y,X: cc thanh ghi a ch tng i (X=R27:R26, X=R29:R28,

X=R31:R30).
A: a ch I/O.
q: dch chuyn ca a ch tuyt i.

I. Instruction ch dng cho Register Files.
- LDI (LoaD Immediate).
C php: LDI Rd,K
Chc nng: Load hng s K vo thanh ghi Rd.
Gii hn: ch p dng cho cc thanh ghi t R16 n R31.
V d: LDI R16, 99 kt qu l thanh ghi R1 mang gi tr 99.
- MOV (MOVE).
C php: MOV Rd, Rr
Chc nng: Copy gi tr trong thanh ghi Rr vo thanh ghi Rd.
Gii hn: p dng cho tt c cc thanh ghi trong RF.
V d: MOV R15, R16 kt qu l R15 c cng gi tr vi R16

(R15=R16=99).
- CLR (CLEAR Register).
C php: CLR Rd
Chc nng: Copy gi tr trong thanh ghi Rr vo thanh ghi Rd.
V d: p dng cho tt c cc thanh ghi trong RF.

- SER (SET Register).
C php: SER Rd
Chc nng: set tt c cc bit tronh thanh ghi Rd ln 1, sau lnh ny thanh ghi
Rd=0xFF.
V d: SER R16 kt qu l R16 = 0xFF.

- CBR (CLEAR Bit in Register).
C php: CBR Rd, K
Chc nng: xa cc bit trong thanh ghi Rd vi mt n K, nu Bit no

trong K l 1 th Bit tng ng trong Rd s b xa.
V d: CBR R16, 0xF0 kt qu l 4 bit cao nht ca R16 b xa v

K=11110000 (B).
- SBR (SET Bit in Register).
C php: SBR Rd, K
Chc nng: set cc bit trong thanh ghi Rd vi mt n K, nu Bit no trong

K l 1 th Bit tng ng trong Rd s c set ln 1.
V d: SBR R16, 0xF0 kt qu l 4 bit cao nht ca R16 c set ln 1 v

K=11110000 (B).
- BLD (Bit LoaD from T Flag).
C php: BLD Rd,b
Chc nng: Load gi tr trong c T ca thanh ghi SREG vo bit th b trong

thanh ghi Rd. y cng chnh l chc nng chnh ca c T.
V d:
SET ; set bit T ln 1
BLD R16, 4
Kt qu l bit 4 ca thanh ghi R16 c set ln 1 v gi tr ca bit T l 1.
- BST (Bit Storage from T Flag).
C php: BST Rd,b
Chc nng: Copy bit th b trong thanh ghi Rd vo trong c T ca thanh ghi
SREG. y cng chnh l chc nng chnh ca c T.
V d: BST R16, 4 kt qu l c T cha gi tr ca bit 4 ca thanh ghi R16.

- CPI (COMPARE with Immediate).
C php: CPI Rd, K
Chc nng: so snh thanh ghi Rd vi hng s K, lnh ny lm thay i nhiu

bit trong thanh ghi SREG trong s thay i ca c Zero l quan trng nht, nu
Rd = K c Z=1, ngc li Z=0, s dng c im thay i ca c Z kt hp vi
lnh BRNE hoc BREQ chng ta c th to thnh mt lnh r nhnh.
V d:
LDI R16, 10
CPI R16, 10
Kt qu l c Z c set thnh 1 v lc ny R16 =10.
- ANDI (AND with Immediate).
C php: ANDI Rd, K
Chc nng: thc hin php Logic AND gia thanh ghi Rd vi hng s K v
kt qu t li trong Rd.
V d: ANDI R17, 0x00 kt qu l R17 c 0x00.

- AND (Logical AND).
C php: AND Rd, Rr
Chc nng: thc hin php Logic AND gia 2 thanh ghi Rd v Rr , kt qu
t li trong Rd.
V d:
LDI R1, 0xFF ;(11111111)
LDI R17, 0xAA; (10101010)
AND R1, R17
Kt qu l R1=0xAA v 11111111 & 10101010 =10101010.
- ORI (Logical OR with Immediate).
C php: ORI Rd, K
Chc nng: thc hin php Logic OR gia thanh ghi Rd vi hng s K v
kt qu t li trong Rd.
V d: ORI R17, 0xFF kt qu l R17 c 0xFF.

- OR (Logical OR).
C php: OR Rd, Rr
Chc nng: thc hin php Logic OR gia 2 thanh ghi Rd v Rr , kt qu t

li trong Rd.
V d:
LDI R1, 0xFF ;(11111111)
LDI R17, 0xAA; (10101010)
OR R1, R17
Kt qu l R1=0xFF v 11111111 or 10101010 =11111111.
- LSL (Logical Shift Left).
C php: LSL Rd
Chc nng: dch tt thanh ghi Rd sang tri 1 v tr, Bit 7 (bit ln nht) ca
Rd s c cha trong c nh C, bit 0 ca Rd b xa thnh 0. Thc cht LSL tng
ng vi php nhn thanh ghi Rd vi 2. Bn xem hnh minh ha bn di.
V d:
LDI R1, 0B11000011 ; (dng nh phn ca 195)
LSL R1
Kt qu l R1=10000110 v c C =1 v thanh ghi R1 c dch sang tri 1 v tr,
trc khi dch bit 7 ca R1 l 1 nn sau khi dch bit ny c cha trong C, cho
nn C=1.
- LSR (Logical Shift Right).
C php: LSR Rd
Chc nng: dch tt thanh ghi Rd sang phi 1 v tr, Bit 0 (bit nh nht) ca
Rd s c cha trong c nh C, bit 7 ca Rd b xa thnh 0. Thc cht LSR
tng ng vi php chia thanh ghi Rd cho 2. Bn xem hnh minh ha bn di.
V d:
LDI R1, 0B11000110 ; (dng nh phn ca 195)
LSR R1
Kt qu l R1=01100001 v c C =1 v thanh ghi R1 c dch sang phi 1 v

tr, trc khi dch bit 0 ca R1 l 1 nn sau khi dch bit ny c cha trong C, cho
nn C=1.
- ADD (ADD without Carry).
C php: ADD Rd, Rr
Chc nng: thc hin php cng 2 thanh ghi Rd v Rr , kt qu t li trong

Rd. C nh C khng c s dng.
V d:
LDI R16, 30
LDI R17, 25
ADD R16, R17
Kt qu l R16=55.
- INC (INCrement).
C php: INC Rd
Chc nng: tng thanh ghi Rd 1 n v v kt qu t li trong Rd. Lnh ny

c bit thch hp cho cc ng dng lp, kt hp vi BREQ hay BRNE c th to
thnh 1 vng lp FOR.
V d: INC R17 kt qu l R17 c tng thm 1 n v.
- SUB (SUBtract without Carry).
C php: SUB Rd, Rr
Chc nng: thc hin php tr 2 thanh ghi Rd - Rr , kt qu t li trong Rd.

C nh C khng c s dng.
V d:
LDI R16, 30
LDI R17, 25
SUB R16, R17
Kt qu l R16=5.
- SUBI (SUBtract Immediate).
C php: SUBI Rd, K
Chc nng: thc hin php tr thanh ghi Rd vi hng s K, kt qu t li

trong Rd.
V d:
LDI R16, 30
SUBI R16, 20
Kt qu l R16=10.
- DEC (DECrement).
C php: DEC Rd
Chc nng: gim thanh ghi Rd 1 n v v kt qu t li trong Rd. Lnh

ny c bit thch hp cho cc ng dng lp, kt hp vi BREQ hay BRNE c th
to thnh 1 vng lp FOR.
V d: DEC R17 kt qu l R17 c gim i 1 n v.
- MUL (MULtiply unsigned).
C php: MUL Rd, Rr
Chc nng: thc hin php nhn khng du 2 thanh ghi 8 bit Rd, Rr, kt qu
l 1 s 16 bit t trong 2 thanh ghi R1:R0. Ch nu Rd v Rr l cc thanh ghi R1
v R0 th kt qu sau khi tnh c s c vit ln. Xem hnh minh ha
instruction MUL bn di.
V d:
LDI R16, 30
LDI R17, 25
MUL R16, R17

Kt qu l R1=0x2, R0=0xEE, v 30x25=750=0x02EE.
II. Instruction cho cc thanh ghi I/O.
Bn instruction sau y c thit k ring truy cp vng nh I/O, cc
instruction ny s dng a ch I/O ca cc thanh ghi trong vng nh ny. V l
thit k ring cho vng nh I/O, bn khng th s dng cc thanh ghi ny truy
cp RF hay SRAM. Trong cc c php ca instruction ny, khi nim a ch A l
a ch I/O, 0 A 63, nu trong v d A=0x00 th l thanh ghi u tin ca
vng I/O, khng phi l thanh ghi R0.
- OUT (OUTPUT Data).
C php: OUT A, Rr
Chc nng: xut gi tr t thanh ghi Rr ra thanh ghi c a ch A trong vng

nh I/O. y l cch ph bin nht xut gi tr ra vng I/O.
Gii hn: Rr l thanh ghi RF bt k, A b gii hn t 0 n 63.
V d:
LDI R16, 0xFF
OUT 0x11, R16
Kt qu l thanh ghi c a ch 0x11 trong vng I/O, tc thanh ghi DDRD, c gi
tr bng 0xFF.
- IN (INPUT Data).
C php: IN Rr, A
Chc nng: Load gi tr t thanh ghi c a ch A trong vng nh I/O vo

thanh ghi Rr. y l cch ph bin nht nhn gi tr t vng I/O.
Gii hn: Rr l thanh ghi RF bt k, A b gii hn t 0 n 63.
V d:
IN R16, 0x10
Kt qu l thanh ghi R16 nhn c gi tr ca thanh ghi c a ch 0x11 trong
vng I/O, tc thanh ghi PIND, y chnh l v d c gi tr cc chn ca PORTD
vo R16.
- SBI (Set Bit in I/O Register).
C php: SBI A, b
Chc nng: Set bit th b trong thanh ghi c a ch A trong vng nh I/O.
Tuy nhin lnh ny khng c tc dng trn ton b vng I/O m ch c tc i vi
32 thanh ghi u (a ch t 0 n 31).
Gii hn: b l s th cc bit trong thanh ghi, 0b7; A b gii hn t 0 n

31.
V d:
SBI 0x12, 2
Kt qu l bit 2 ca thanh ghi c a ch 0x12 trong vng I/O, tc thanh ghi
PORTD, c set ln 1. y chnh l v d set chn PD2 ca PORTD.
- CBI (Clear Bit in I/O Register).
C php: CBI A, b
Chc nng: xa bit th b trong thanh ghi c a ch A trong vng nh I/O.

Tuy nhin lnh ny khng c tc dng trn ton b vng I/O m ch c tc i vi
32 thanh ghi u (a ch t 0 n 31).
Gii hn: b l s th cc bit trong thanh ghi, 0b7; A b gii hn t 0 n

31.
V d:
CBI 0x12, 2
Kt qu l bit 2 ca thanh ghi c a ch 0x12 trong vng I/O, tc thanh ghi
PORTD, b xa thnh 0. y chnh l v d xa chn PB2 ca PORTD.
III. Cc con tr X, Y, Z v cch truy cp ton b khng gian b nh.
Trong Register File ca AVR, cc thanh ghi t R26 n R31ngoi cha nng
thanh ghi thng thng cn c chc nng l con tr (Pointer) trong vic truy cp
b nh (c b nh data v b nh Program). Nu c s dng nh cc Pointer,
cc thanh ghi trn c bit n vi tn gi X, Y, Z. nh ngha nh sau:
X=R27:R26, Y=R29:R28, Z=R31:R30. Chng l 3 thanh ghi 16 bit c nh
ngha trc cho tt c cc AVR. Ngoi ra trong cc file nh ngha cho chip chng
ta c thm 6 nh ngha khc l XL, XH, YL, YH, ZL, ZH cng chnh l tn gi
ca R26-> R31. Phn ny chng ta kho st mt s instruction dng truy cp ton
b khi nh ca AVR bng cch s dng a ch trc tip v bng cch s dng
Pointer.
- LDS (LoaD direct from data Space).
C php: LDS Rd, k
Chc nng: load gi tr 1 byte t thanh ghi c a ch k trong SRAM vo

thanh ghi Rd, k l dng a ch tuyt i c gii hn t 0 n 65535(2^16-1).
Gii hn: Rd l thanh ghi bt k trong RF nhng gi tr ln nht ca k l

65535, v th vi lnh ny ta khng th truy cp vt qu khong khng gian
64KB. Nu mun truy cp vng khng gian ln hn 64KB chng ta cn mt s h

tr, tuy nhin y ti gi s b nh ca chip (thng l b nh data) khng vt
qu 64KB (thc t cha c chip AVR no c SRAM hay EEPROM vt qu
64KB).
V d:
LDS R2, 0x0060
Kt qu l thanh ghi R2 cha gi tr ca thanh ghi c a ch 0x0060, y l thanh
ghi u tin trong khong SRAM (sau RF v vng I/O) ca AVR.
- STS (STorage direc to data Space).
C php: STS k, Rr
Chc nng: instruction ny hon ton ging LDS nhng dng xut d
liu t thanh ghi Rr ra RAM, ngi c c th tham kho phn gii thch cho LDS.
S dng a ch trc tip th cu lnh s n gin nhng rt kh nh phn a ch,
thng thng SRAM l vng chng ta hay s dng cha bin tm thi, trong
cc ngn ng cp cao ta ch cn nh tn bin nhng vi ASM chng ta phi nh
a ch ca chng. Mt cch tt trnh vic ny l dng ch th (DIRECTIVE,
bn xem li bi 1) . EQU gn tn bin cho 1 a ch, v d .EQU bientam =
0x0060 v sau s dng bientam thay cho 0x0060.
Mt cch khc c dng truy cp b nh m khng dng a ch tuyt i l
s dng s dng con tr. C 2 instruction h tr con tr l LD(LoaD indirec from
data Space), v ST (STorage indirec to data Space), LD c d liu t SRAM vo
thanh ghi cn ST lu d liu t thanh ghi vo SRAM. C 3 con tr X, Y v Z u
c th c dng nhng c mt s im lu : c 3 u dng c trong trng
hp truy xut thng thng nhng vi cch truy cp c offset, con tr X khng s
dng c. truy xut b nh chng trnh bng con tr th Z l gii php duy
nhtDi y l 1 s cch s dng LD, ST kt hp vi con tr, chng ta xt
thng qua cc v d.
V d 1:
CLR R27 ; xa R27, tc xa byte cao ca pointer X

LDI R26, 0x60 ; load gi tr 0x60 vo R26, tc byte thp ca pointer X
; sau 2 dng trn, gi pointer X l 0x0060, sn sng tr n v tr u tin trong
SRAM.
LD R1, X+ ; Load gi tr nh 0x0060 vo R1 (v X tr n 0x0060), sao
tng gi tr ;X ln 1, nh th sau lnh ny X=0x0061
LD R2, X+ ; Load gi tr nh 0x0061 vo R2, sao tng gi tr ;X ln 1, nh
th sau lnh ny X=0x0062
LD R3, X ; Load gi tr nh 0x0062 vo R3 v khng thay i X
LD R4, -X ; Gim gi tr ca X trc (X=0x0061), sau load gi tr nh
0x0061 vo R4
T v d ny chng ta thy c 3 cch c bn load d liu t SRAM bng con
tr, cch Load trc tip trong trng hp LD R3, X, cch load post-increment
(hoc post-decrement) nh trong trng hp LD R1, X+ v cch load predecrement (hoc pre-increment) trong trng hp LD R4, -X.
Chng ta c th vit li v d trn nhng s dng con tr Y hoc Z thay cho X. V
d vit cho instruction ST cng hon ton tng t.
Tuy nhin cch truy cp theo cch pre hay post u lm thay i gi tr ca con tr,
iu ny c 1 bt li l nu chng ta mun quay li v tr nh no , chng ta
phi tip tc thay i con tr. trnh vic lm ny, 1 cch truy cp khc c h
tr l truy cp Offset. Xt v d sau:
LD R1, Y+1
y chnh l cch truy cp Offset dng con tr Y, cch vit trn l tng ng vi
cch vit
LD R1, Y+
Nhng im khc bit y l cch vit Offset khng lm thay i gi tr ca con
tr Y. S dng Offset c u im nh s dng mng (array) trong cc ngn ng lp
trnh cp cao. Cn ch l gi tr offset khng vt qu 63 v phng php ny
ch dng cho 2 thanh ghi Y v Z.
IV. R nhnh v vng lp.
Khng ging nh cc ngn ng cp cao, khi lp trnh bng ASM bn khng c
h tr cc cu trc iu khin nh If, For, Whilengi lp trnh ASM phi t xy
dng cho mnh cc cu trc ny t nhng instruction c bn. Nu bn c trong tay
ti liu tra cu instruction cho AVR bn s thy c rt nhiu instruction c dng
BRxx, vi BR l vit tt ca t Branch (r nhnh). y l cc instruction c bn

gip bn xy dng cc cu trc iu khin tng ng If, For, Whilecho ring
mnh.
Trc ht ta s kho st instruction BRNE bng cch xem li v d trong bi "Lm
quen AVR", y l on chng trnh con DELAY:
DELAY:
LDI R20, 0xFF
DELAY0:
LDI R21, 0xFF
DELAY1:
DEC R21
BRNE DELAY1
DEC R20
BRNE DELAY0
RET
Bn hy ch 4 dng lnh nm gia on chng trnh trn (bt u t dng 4),
dng u tin th bn bit - load gi tr 255 vo thanh ghi R21, sau ti t 1
label DELAY1- xem nh l 1 ct mc, dng 3, instruction DEC bn mi c hc
hm nay - gim gi tr thanh ghi R21 i 1 n v, v cui cng BRNE DELAY1,
BRNE l vit tt ca BRanch if Not Equal r nhnh nu khng bng, thc ra bn
cht ca lnh ny l r nhnh nu c Zero khng bng 1. Nh th cu lnh BRNE
DELAY1 ca chng ta c AVR thc hin nh sau: kim tra c Z, nu Z=1 tip
tc thc hin dng tip theo sau m khng quan tm n nhn DELAY1, nhng
nu Z=0 th nhy n nhn DELAY1. Bn thy rng ban u R21 =255, sau khi
gim 1 bi DEC, thanh ghi R21=2540, c Z =0, r nhnh xy ra, b m chng
trnh nhy v nhn DELAY1. Qu trnh ny lp li khong 255 ln trc khi R21
=0 dn n Z=1.
Bao bn ngoi vng lp ca nhn DELAY1 l vng lp ca nhn DELAY0, cch
hiu hon ton tng t nhng trc khi lnh DEC R20 c thc thi th phi ch
cho vng lp DELAY1 kt thc. Bn thn DELAY0 cng l 1 vng lp 255 ln. kt
qu cui cng l ta thu c 1 vng lp khong 255x255 ln m khng lm g c,
chnh l ngha v cch hot ng ca on chng trnh con DELAY.
Bn cnh BRNE chng ta c 1 s instruction phc v r nhnh khc nh:
- BREQ (BRanch if EQual).
C php: BREQ LABEL
Chc nng: Nhy n nhn LABEL nu c Z =1. C Z chu tc ng ca rt

nhiu instruction nh CP, CPI, SUB, SUBIv th BREQ thng c s dng
sau cc instruction ny.
V d:
LDI R16, 0xFF
LDI R17, 0xFF
CP R16, R17 ; so sanh 2 thanh ghi R16, R17
BREQ RENHANH
..
RENHANH:
; thc hin nhng vic khi r nhnh.
Kt qu l vic r nhnh xy ra v khi so snh bng CP, R17=R16 nn c Z t
ng c set bng 1, lnh BREQ c thc thi v nhy n nhn RENHANH. V
d ny tng ng cu trc if (R16=R17) {thc hin nhng vic khi r nhnh}.
- BRLO (BRanch if LOwer).
C php: BRLO LABEL
Chc nng: bn cht ca cu lnh l nhy n nhn LABEL nu c C =1.

Tuy nhin, thng thng lnh ny s dng theo sau cc instruction nh CP, CPI,
SUB, SUBIkhi vic r nhnh s xy ra nu thanh ghi Rd
V d:
EOR R16, R16 ;XOR R16 vi chnh n, tng ng CLR R16
VONG LAP:
INC R16 ;tng R16 thm 1 n v

CPI R16, $10 ;so snh R16 vi s hexadecimal $10
BRLO VONGLAP ;nhy v VONGLAP nu R16 <$10
NOP ;cu lnh ny s c thc thi nu iu kin r nhnh trn khng tha,
; NOP l 1 instruction, chc nng l khng lm g c.
Kt qu l phn lnh bn trong VONGLAP s c thc hin khong 16 ln
($10=16) trc khi thc hin lnh NOP.
- BRSH (BRanch if Same or Higher).
C php: BRSH LABEL
Chc nng: bn cht ca cu lnh l nhy n nhn LABEL nu c C =0.

Tuy nhin, thng thng lnh ny s dng theo sau cc instruction nh CP, CPI,
SUB, SUBIkhi vic r nhnh s xy ra nu thanh ghi Rd Rr.
V d:
SUBI R16, 4 ;tr R16 i 4 n v
BRSH RENHANH ; nhy n RENHANH nu R16 4
.
RENHANH:
NOP
Cn rt nhiu instruction r nhnh bn c th s dng to cu trc iu khin,

ch l cc instruction ny u hot ng da trn trng thi ca 1 c no , do
bn cn la chn 1 lnh ph hp thc thi trc cc instruction r nhnh ny,
lm c nh vy bn cn xem k ti liu hng dn INSTRUCITON cho

AVR.
Lp trnh vi AVR Studio
5
( 40 Votes )
Ni dung
1.
Lp trnh Asembly bng AVR Studio.
2.
Lp trnh C bng AVR Studio.
Lm quen AVR.
Download AVRStudio
Trong bi ny ti hng dn cch s dng b cng c AVRStudio to cc
Project lp trnh bng ngn ng Assembly v C. Ti s dng v d chng trnh
qut LED bi 1 minh ha cho c 2 cch to mt Project Assembly v C.
I. Lp trnh Assembly bng AVRStudio.
Vic ci t AVRStudio tng i n gin. Bn hy download bn mi nht
ca phn mm ny t website Atmelhoc bn 4.623 ti y (hoc mt mirror
khc) v ci t vo my. Theo mc nh, chng trnh s c ci vo a C
ti: C:\Program Files\Atmel\AVR Tools.
Bt u vi AvrStudio4: bn chy AvrStudio t Start/ All Programs/ Atmel
AVR Tools/ AvrStudio 4. ln u chy AvrStudio, 1 dialog Welcome to
AvrStudio 4 xut hin, hy b check show dialog at Startup v nhn cancel.
Hnh 1. Welcome to AVR studio 4 Diaolg.

Bn thy giao din AVR Studio 4 nh sau:
Hnh 2. Giao din AVR Studio.

Giao din AVR Studio rt d s dng, v vy chng ta s kt hp tm hiu trong
lc vit v d.
To Project mi: t menu Project, chn Project/New Project.
Hnh 3. To Project mi.

Mt dialog mi xut hin cho php bn setting Project ca bn, trong vng
Project Type chn Atmel AVR assembler, tc lp trnh bng ngn ng
Assembly v trnh dch l Atmel AVR assembler (trnh dch tch hp trong AVR
Studio); Location, chn ni cha Project (trong v d ny ti chn th mc
D/AVR1); Project name, tn Projetc ca bn, hy t l avr1.
Hnh 4.Setting Project.

Nhn Next tip tc chn Platform v device, vic ny phc v cho mc ch
debug chng trnh hay m phng bng avr simulator. Bn hy chn AVR
Simulator trong Platform v Atmega8 trong device (chng ta s vit chng
trnh cho chip Atmega8).
Hnh 5. Chn Platform v device.

Nhn finish kt thc setting project, bn thy cc ca s ca Project cha
cc thng tin Project ca bn, bn thy trong mc Source files c 1 file
avr1.asm l source code ca bn. Bn c th nhn vo switch tab bn di ca
s Project xem ca s I/O View, ca s ny cha thng tin chip dng khi m
phng. Ca s Build cha thng tin kt qu bin dch. Editor l vng vit
chng trnh, trong trng hp ny l file avr1.asm ca bn.
Hnh 6. Ca s lp trnh.
Vic cn li l vit code vo ca s Editor sau dch chng trnh bng
phm F7.
II. Lp trnh C bng AVRStudio.
V bn cht AVRStudio khng h tr lp trnh ngn ng C v khng c trnh
dch C. Tuy nhin n cho php tch hp trnh dch C ca b cng c WinAVR. V
th, nu mun s dng AVRStudio lp trnh C cho AVR bn phi ci t trnh
dch v th vin avr-gcc t GNU hoc n gin l ci t WinAVR cng
AVRStudio. Bn tham kho thm bihng dn WinAVR bit cch download
ci t WinAVR. Cc hng dn bn di gi s rng bn ci t thnh cng
AVRStudio v WinAVR.
Vic to 1 Project lp trnh bng ngn ng C trong AVR Studio khng khc
my so vi vic to Project ASM. iu duy nht cn ch l bc chn trnh bin
dch. Xem li hnh 4 khi to Project ASM, chng ta chn Atmel AVR Assempler
lm trnh dch chnh, to Project C chng ta chn AVR GCC lm trnh bin dch
nh trong hnh 7. Cn lu l trnh dch AVR GCC ch xut hin trong danh sch
la chn ca AVR Studio khi bn ci WinAVR vo my trc .
Hnh 7. Chn AVR GCC lm trnh bin dch chnh.

Xem hnh 7, gi s bn t tn Project l avr1 trong Project name, bn s
thy AVR Studio ngh t to ra 1 file chng trnh chnh tn l avr1 c phn m
rng l ".c", khc vi phn m rng ".asm" khi to Project Assembly.
Cc vic cn li hon ton tng t trong trng hp to Project ASM nn bn
c th xem li phn trn. Sau khi to Project lp trnh C trong AVR Studio, bn
save Project ri vo th mc cha Project mi to, bn s thy 1 file Makefile
c t ng to ra. Makefle c AVR Studio to t ng trong lc to Project,
bn khng cn dng n trnh MFile. Ngn ng C cho AVR Studio hon ton l
AVR GCC nh trong WinAVR, v th bn c th copy, load 1 file source t
WinAVR vo m khng cn bt k chnh sa no.
Mt trong nhng u im khc khi bn lp trnh C trong AVR Studio l bn c
th tn dng trnh AVR Simulator debug code C trc tip. ng thi, trnh bin
tp (Editor) ca AVR Studio cng gip bn vit code thun tin hn Programmer
notepad.

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Asembly

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Bi 1 - Lm quen AVR

Cc bi cn tham kho trc

Gn nh chng ta khng cn mc thm bt k linh kin ph no khi s dng

Thit b lp trnh (mch np) cho AVR rt n gin, c loi mch np ch

Bn cnh lp trnh bng ASM, cu trc AVR c thit k tng thch C.

Ngun ti nguyn v source code, ti liu, application notert ln trn

Hu ht cc chip AVR c nhng tnh nng (features) sau:

C th s dng xung clock ln n 16MHz, hoc s dng xung

Chc nng Analog comparator.

nhng li nh gn (gi PDIP c 28 chn) v low cost nn cc bn c th mua t

AvrStudio: l trnh bin dch ASM chnh thc cung cp bi Atmel, y l

Wavrasm: cng c cung cp bi Atmel, n chnh l tin thn ca

WinAVR hay avr-gcc: l b trnh dch c pht trin bi gnu, ngn ng s

code C c vit bng b ny, v vy n rt l tng cho bn khi vit cc ng dng

CodeVisionAvr: mt chng trnh bng ngn ng C rt hay cho AVR, h tr

ICCAVR: lp trnh C cho avr, download bn demo.

V cn rt nhiu trnh bin dch khc cho AVR m ti khng k ra y, nhn

Mch np: tham kho bi vit gii thiu mch np AVR.

19 OUT PORTB, R16

Bn thy 1 s t c mu BLUE (v d LDI, OUT, RJMP, RCALL,

Mt s t bt u bng bng du chm . l cc DIRECTIVE (v d

Thng thng 1 INSTRUCTION c theo sau bi 2 ton hng operand

Cc t theo sau bi du : l cc nhn label (v d MAIN, DELAY),

Phn i sau du ; gi l gii thch comment, phn ny khng c bin

phn 2 l khi to mt s iu kin u cho Stack Pointer v PORT, phn 3 l

RJMP: Relative Jump l lnh nhy khng iu kin n 1 v tr trong b nh,

Bn ch 2 dng trn v nhng g ti gii thch sau y, 2 dng ny c tc

Hnh 1: chip ATmega8.

C th bn s hi ti sao chng khng s dng 1 dng duy nht l LDI DDRB,

Phn 3: Chng trnh chnh

By gi chc bn on c chng trnh ca chng ta thc hin vic g,

Phn 4: chng trinh con DELAY: on chng trnh ny khng lm g c

Cc bi cn tham kho trc

Thanh ghi trng thi.

Assembly cho AVR.

Hiu c cu trc AVR, cu trc b nh v cch thc hot ng ca chip.

Hiu v Stack v cch hot ng.

Bit c mt s instruction c bn truy xut b nh.

Hc cc instruction r nhnh v vng lp.

Chng trnh con (Subroutine) v Macro.

Vit 1 v d minh ha cch s dng b nh v vng lp.

II. T chc ca AVR.

c tch ring. Data memory bus ch c 8 bit v c kt ni vi hu ht cc thit

Hnh 1. T chc b nh ca AVR.

c truy cp trc tip trong cc instruction.

Cc ton t, php ton thc hin trn cc thanh ghi ny ch cn 1 chu k

Register File c kt ni trc tip vi b x l trung tm CPU ca chip.

Chng l ngun cha cc s hng trong cc php ton v cng l ch cha

Hnh 3. Register file.

chng c tnh t 0x0020 n 0x005F. Nhng nu truy xut nh cc thanh ghi

Hnh 4. Cu trc bn trong AVR.

Stack c hiu nh l 1 thp d liu, d liu c cha vo stack nh

khi ng stack vi 1 a ch khc, tuy nhin v l do an ton, nn khi ng stack

Hnh 6. Ni dung stack trong v d.

RCALL l lnh nhy n 1 v tr trong b nh chng trnh, trc khi nhy, PC

Hnh 7. Thanh ghi trng thi.

Bit 0 C (Carry Flag: C nh): l bit nh trong cc php i s hoc

Bit 1 Z (Zero Flag: C 0): c ny c set nu kt qu php ton i s

Bit 2 N (Negative Flag: C m): c ny c set nu kt qu php ton

Bit 3 V (Twos complement Overflow Flag: C trn ca b 2): hot

Bit 4 S (Sign Bit: Bit du): Bit S l kt qu php XOR gia 1 c N v V,

Bit 5 H (Half Carry Flag: C nh na): c H l c nh trong 1 vi php

Bit 6 T (Bit Copy Storage): c s dng trong 2 Instruction BLD (Bit