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rouiter design using verilog
Descriptiondesign router using verilog.design a 1x3 router using verilog.
By udimudi 20150110

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/************************************************************************
MAVENSILICONCONFIDENTIALThisisanunpublished,proprietarywork
ofMavenSiliconSoftechPvt.Ltd.,Bangalore,andisfullyprotected
undercopyrightandtradesecretlaws.Youmaynotview,use,disclose,
copy,ordistributethisfileoranyinformationcontainedhereinexcept
pursuanttoavalidwrittenlicensefromMavenSiliconSoftechPvt.Ltd.,
Bangalore

DesignName:router_1x3
ModuleName:fsm_router
Date:19/09/2009
Author:PRSIVAKUMAR
Email:siva@vlsitraining.com
Company:MavenSilicon,Bangalorewww.vlsitraining.com
Version:1.0revision0.0
************************************************************************/

//STATEDEFINITIONS

`defineDECODE_ADDRESS4'd0
`defineLOAD_FIRST_DATA4'd1
`defineLOAD_DATA4'd2
`defineLOAD_PARITY4'd3
`defineFIFO_FULL_STATE4'd4
`defineLOAD_AFTER_FULL4'd5
`defineWAIT_TILL_EMPTY4'd6
`defineCHECK_PARITY_ERROR4'd7

//

modulefsm_router(clock,
busy,
fifo_empty,
fifo_full,
packet_valid,
data_in,
parity_done,
low_packet_valid,
detect_add,
write_enb_reg,
resetn,
lp_state,
ld_state,
laf_state,
lfd_state,
full_state,
reset_int_reg
);

inputclock;
inputfifo_empty;
inputfifo_full;
inputpacket_valid;
input[1:0]data_in;
inputparity_done;
inputlow_packet_valid;
inputresetn;

outputbusy;
outputdetect_add;
outputwrite_enb_reg;
outputlp_state;
outputld_state;
outputlaf_state;
outputlfd_state;

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outputfull_state;
outputreset_int_reg;

//PortSignals
wireclock;
wirebusy;
wirefifo_empty;
wirefifo_full;
wirepacket_valid;
wire[1:0]data_in;
wireparity_done;
wirelow_packet_valid;
wireresetn;
wirewrite_enb_reg;
wiredetect_add;//Thissignalstimulatesthesamplingofaddress
wirelp_state;//indicatescurrent_stateisLOAD_PARITY
wireld_state;//indicatescur_stateisLOAD_DATA
wirelaf_state;//indicatescur_stateisLOAD_AFTER_FULL
wirelfd_state;//indicatescur_stateisLOAD_FIRST_DATA
wirereset_int_reg;//resetsinternalregisterstoinitialzerovalue
wirefull_state;//indicatescur_stateisFULL_STATE;

//internalsignals
reg[2:0]cur_state;
reg[2:0]next_state;

always@(posedgeclock)
begin
if(resetn==1'b0)
cur_state<=`DECODE_ADDRESS;
else
cur_state<=next_state;
end

//Next_statelogic
always@(cur_state,resetn,data_in,packet_valid,fifo_full,fifo_empty,parity_done,low_packet_valid)
begin
next_state=`DECODE_ADDRESS;
case(cur_state)
`DECODE_ADDRESS:begin
if(packet_valid==1&&(data_in[1:0]<2'b11))
begin
if(fifo_empty==1'b1)
next_state=`LOAD_FIRST_DATA;
else
next_state=`WAIT_TILL_EMPTY;
end
else
next_state=`DECODE_ADDRESS;
end
`LOAD_FIRST_DATA:begin
next_state=`LOAD_DATA;
end
`LOAD_DATA:begin
if(fifo_full==1'b1)
next_state=`FIFO_FULL_STATE;
elseif(packet_valid==1'b0)
next_state=`LOAD_PARITY;
else
next_state=`LOAD_DATA;
end
`LOAD_PARITY:begin
if(fifo_full==1'b1)
next_state=`FIFO_FULL_STATE;
else
next_state=`CHECK_PARITY_ERROR;
end
`FIFO_FULL_STATE:begin
if(fifo_full==1'b1)
next_state=`FIFO_FULL_STATE;
else
next_state=`LOAD_AFTER_FULL;
end
`LOAD_AFTER_FULL:begin
if(parity_done==1'b1)
next_state=`CHECK_PARITY_ERROR;
elseif(low_packet_valid==1'b1)
next_state=`LOAD_PARITY;
else

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next_state=`LOAD_DATA;
end
`WAIT_TILL_EMPTY:begin
if(fifo_empty==1'b0)
next_state=`WAIT_TILL_EMPTY;
else
next_state=`LOAD_FIRST_DATA;
end
`CHECK_PARITY_ERROR:begin
next_state=`DECODE_ADDRESS;
end
default:next_state=`DECODE_ADDRESS;
endcase
end

//OutputLogic
assigndetect_add=(cur_state==`DECODE_ADDRESS)?1'b1:1'b0;
assignld_state=(cur_state==`LOAD_DATA)?1'b1:1'b0;
assignlp_state=(cur_state==`LOAD_PARITY)?1'b1:1'b0;
assignlfd_state=(cur_state==`LOAD_FIRST_DATA)?1'b1:1'b0;
assignreset_int_reg=(cur_state==`CHECK_PARITY_ERROR)?1'b1:1'b0;
assignlaf_state=(cur_state==`LOAD_AFTER_FULL)?1'b1:1'b0;
assignfull_state=(cur_state==`FIFO_FULL_STATE);
assignwrite_enb_reg=((cur_state==`LOAD_DATA)||
(cur_state==`LOAD_AFTER_FULL)||
(cur_state==`LOAD_PARITY))?1'b1:1'b0;
assignbusy=((cur_state==`FIFO_FULL_STATE)||
(cur_state==`LOAD_FIRST_DATA)||
(cur_state==`LOAD_AFTER_FULL)||
(cur_state==`LOAD_PARITY)||
(cur_state==`CHECK_PARITY_ERROR)||
(cur_state==`WAIT_TILL_EMPTY))?1'b1:1'b0;

endmodule

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2011-09-2623:29

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