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rouiter design using verilog
Descriptiondesign router using verilog.design a 1x3 router using verilog.
By udimudi 20150110

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/************************************************************************
MAVENSILICONCONFIDENTIALThisisanunpublished,proprietarywork
ofMavenSiliconSoftechPvt.Ltd.,Bangalore,andisfullyprotected
undercopyrightandtradesecretlaws.Youmaynotview,use,disclose,
copy,ordistributethisfileoranyinformationcontainedhereinexcept
pursuanttoavalidwrittenlicensefromMavenSiliconSoftechPvt.Ltd.,
Bangalore

DesignName:router_1x3
ModuleName:ff_sync
Date:04/10/2009
Description:Thismoduleprovidessynchronizationbetween
fsmandfifofordatacommunication
Author:PRSIVAKUMAR
Email:siva@vlsitraining.com
Company:MavenSilicon,Bangalorewww.vlsitraining.com
Version:1.0revision0.0
*************************************************************************/
moduleff_sync(clock,
resetn,
detect_add,
data,
empty_0,
empty_1,
empty_2,
full_0,
full_1,
full_2,
write_enb_reg,
write_enb,
fifo_empty,
fifo_full,
vld_out_0,
vld_out_1,
vld_out_2
);

//PortDirection
inputclock;
inputresetn;
inputdetect_add;
input[1:0]data;
inputwrite_enb_reg;
inputempty_0;
inputempty_1;
inputempty_2;
inputfull_0;
inputfull_1;
inputfull_2;

output[2:0]write_enb;
outputfifo_empty;
outputfifo_full;
outputvld_out_0;
outputvld_out_1;
outputvld_out_2;

//Porttypedeclaration
wireclock;
wireresetn;
wiredetect_add;
wire[1:0]data;
wirewrite_enb_reg;
wireempty_0;
wireempty_1;

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wireempty_2;
wirefull_0;
wirefull_1;
wirefull_2;
regfifo_empty;
regfifo_full;
wirevld_out_0;
wirevld_out_1;
wirevld_out_2;

reg[1:0]addr;
reg[2:0]write_enb_sel;

//Thisblockwilldetecttheaddressofchannelandwilllatchittill
//packet_validisasserted,addressandwrite_enb_selwillbeusedfor
//latchingtheincomingdataintothefifoofthatchannel.
always@(posedgeclock)
begin
if(resetn==1'b0)
begin
write_enb_sel=3'b000;
addr=2'b11;
end
elseif(detect_add)
begin
case(data)
2'b00:begin
write_enb_sel=3'b001;
addr=2'b00;
end
2'b01:begin
write_enb_sel=3'b010;
addr=2'b01;
end
2'b10:begin
write_enb_sel=3'b100;
addr=2'b10;
end
default:begin
write_enb_sel=3'b000;
addr=2'b11;
end
endcase
end
end
//writeenablegenerationforfifo
assignwrite_enb[0]=((write_enb_sel[0])&&(write_enb_reg));
assignwrite_enb[1]=((write_enb_sel[1])&&(write_enb_reg));
assignwrite_enb[2]=((write_enb_sel[2])&&(write_enb_reg));

//outputdatawillbevalidatchannelswhenvld_outwillbehigh
assignvld_out_0=~empty_0;
assignvld_out_1=~empty_1;
assignvld_out_2=~empty_2;

//fifo_emptyandfifo_fullaregeneratedfromthe
//fullandemptyofthefifo,selectedbyaddressbits
always@(addr,empty_0,empty_1,empty_2,full_0,full_1,full_2)
begin
case(addr)
2'b00:begin
fifo_empty=empty_0;
fifo_full=full_0;
end
2'b01:begin
fifo_empty=empty_1;
fifo_full=full_1;
end
2'b10:begin
fifo_empty=empty_2;
fifo_full=full_2;
end
default:begin
fifo_empty=1'b0;
fifo_full=1'b1;
end
endcase
end

146
147

endmodule

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