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Abstract
Mobile devices are entering in every sphere of our life. With the introduction of
newer features these devices are becoming more and more data centric. Apart from
data storage another major concern in such scenarios is data movement. Many
protocols exist to aid in data movement within the mobile devices as well as to
communicate with the outside world. Among these protocols serial communication
protocols are most widely used protocols due to their low pin requirement and ease
of implementation. Usually the protocol followed by a device depends on the
amount of data that it needs to transfer as well as the speed with which it is
required to communicate. But there are situations when a single device has
different protocol requirements in two different situations. In such situations a
bridge is required such that device can follow communication protocol according
to the situational requirement rather than being bound to one kind of protocol.
In this research, a serial protocol bridge has been designed that consists of two
most widely used serial protocol controllers. It helps a particular device to
communicate with either of the protocol seamlessly. The bridge has been designed
using UML 10.0. All the design modules of bridge have been coded in VHDL and
simulated using Model Sim Altera 6.5e. Further these modules were compiled for
EP4CE115F29C7 FPGA chip on Cyclone IV Altera DE115 board using Quartus II.
ii
iii
Acknowledgement
Neena Sharma
iv
Contents
1. Introduction..1
1.1. Motivation..1
1.2. Research summary.4
2. Background..6
2.1. Introduction6
2.1.1. RS232...7
2.1.2. RS-422 and RS-485.7
2.1.3. I2C...7
2.1.4. SPI...8
2.2. Hardware architecture for mobile devices.9
2.2.1. Evolution of mobile phones..10
2.3. Embedded system design.13
2.4. FPGA based design..14
2.5. Conclusion15
3. Design.16
3.1. Introduction..16
3.2. Basics of I2C protocol..17
3.3. Basics of SPI protocol..19
3.4. Design methodology20
3.4.1. Designing I2C master.21
3.4.2. Designing I2C slave26
3.4.3. Designing SPI master..30
v
vi
List of Figures
1.1
2.1
2.2
2.3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
3.16 Sequence diagram for SPI slave data exchange use case..33
3.17 SPI master writes to I2C slave through serial protocol bridge34
3.18 I2C master writes to SPI slave through serial protocol bridge35
3.19 SPI master performs read on I2C slave through serial protocol bridge36
3.20 I2C master performs read on SPI slave through serial protocol bridge36
3.21 Complete Bridge37
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
4.10 SPI master writes to I2C slave through serial protocol bridge..52
4.11 SPI master reads I2C slave through serial protocol bridge...52
4.12 Camera example revisited.55
viii
List of Tables
2.1
4.1
4.2
4.3
4.4
ix
ACRONYMS
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
SS slave select
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
1G first generation
30.
3G third generation
xi
Chapter 1
Introduction
1.1 Motivation
Mobile devices are entering into every part of our lives. As consumer expectations
from these devices keeps on increasing with time, the data movement required
inside the system in order to incorporate the newly introduced features. This makes
mobile devices more and more data centric. With the increase in data handling
capacity of the mobile devices there increases the need for smarter communication
protocols so that overall system performance can also meet the user expectations.
Serial communication is the most widely used method of data transfer in today's
mobile embedded world due to its speed and the number of pins required for data
transfer. Efficiency of a mobile embedded system depends on the speed with which
it can transfer data to the inside as well as the outside world. Hence any equipment
that can enhance the speed of data movement can be of great importance for the
overall efficiency of the system. Considering the importance of speed of data
movement, a lot of effort is being put into improving the serial communication
protocols used inside mobile devices. There are many serial communication
protocols available, each having different characteristics such as speed, hand
1
A deeper look into the mobile embedded world reveals that each of these protocols
uses a master-slave configuration. Some of the protocols support multiple masters
on the same communication bus. Some are capable of communicating with
multiple slaves. In a typical mobile embedded system, each peripheral is slave to
one of these protocols and is capable of transferring data on command of its
respective master. Hence along with the main controller there are several other
controllers handling each type of serial protocol being used in the mobile system.
In a typical mobile system each peripheral is connected to the master of one of the
serial communication protocol according to its speed and latency requirements.
Inside the mobile system, some data transfers can be low speed and high latency
while others are needed to be high speed with low latency. Hence we need to
incorporate different protocols and use them as per the need. As long as the
peripherals inside these mobile devices, with different speed demands, are in
separate spheres, there will not be any issue while deciding which protocol is
appropriate for which peripheral. But the problem is when the same peripheral
requires low data rate in one situation and high data rate in another situation. For
example, inside a mobile phone when a user decides to click an image, the user
2
sends a capture command to the camera by pressing a button on the device. This
command is going to be a short command and it needs to be served as fast as
possible. But the situation is totally opposite when the image has been captured
and the user press the save button. In this situation the data that needs to be
transferred is a huge amount but the user doesn't mind if it takes a while to save the
image into the memory especially if the device is transferring the image data in the
background. Hence the mobile device will use two different protocols for two
different types of data exchange with the same peripheral, which is the camera in
the above example. One way to handle this will be making the peripheral slave to
both the protocols. This will require additional space and routing overhead for the
designer because we need to make the camera available to both the protocols and it
should be able to respond to both the above situations accordingly. Figure 1.1
depicts the above scenario.
A simpler way to handle the above situation is to have a bridge through which the
master of one protocol will be able to send and receive data from the slave of
another protocol. This will require each peripheral in the mobile device to be slave
of only one of the protocol. It will be made accessible to other protocols through
the bridge. This is one feasible solution to the problem and is the main motivation
behind this research.
In the design phase of the project we will be exploring UML (unified modeling
language) and using its features such as use case diagrams, sequence diagrams and
state machines to describe the protocol bridge fully and design its components.
State machine are the most common way of implementing embedded systems on
4
an FPGA (field programmable gate array). We will also be implementing the serial
protocol bridge design on ALTERA ModelSim STARTER EDITION 6.5e that is
standard for the ALTERA DE115 board. After successful designing and
implementation of the serial protocol bridge state machine, we will be generating
test waveforms and demonstrating its use for sending and receiving data across the
two different protocols. We will also be implementing our designs on FPGA chip
present on ALTERA DE115 board.
Success of this project will demonstrate a way of handling the above described
situations in a better and more efficient manner. This bridge is ultimately going to
reduce the wiring on PCB board and result in the reduction of overall size of the de
vice. As now each device will be slave to only one protocol and other protocols can
reach it through the bridge. It will also serve as a base for implementing serial
protocol bridge for other protocols.
Chapter 2
Background
2.1 Introduction
Embedded systems are becoming common in every sphere of our life. One
common feature of embedded system is communication between different
peripherals. Embedded system designers have a large number of choices when it
comes to moving data both within the embedded world and between the system
and the outside world. Various attempts have been made to distinguish these
protocols based on the way data is being transferred-for example, serial vs parallel,
or based on the speed with which the data is being transferred. There are many
different reasons why serial communication is preferred over parallel
communication. These include the low pin count as well as the need for connecting
systems with a PC during development and/or in the field [1].
Various serial protocols for communication buses are available in the market have
their own advantages and disadvantages. A thorough study of protocols is
necessary before deciding which protocol will suffice for the system. The choice of
serial bus should not only meet the speed requirement but it should also consider
other factors such as the life of the product and the number of devices to be
connected. A detailed analysis of available serial protocols is required. We will
6
2.1.1 RS-232: It is the most common interface found on every computer these
days. It is a FULL DUPLEX if 2 pairs of Transmitter and receiver are deployed at
each end. Varying levels of voltages are transmitted in order to transmit logic 0
and 1. It is capable of speed up to 115.2Kbps.
winning master. This protocol is used for rather low speeds and low distances
typically within the system.
2.1.4 SPI: Serial Peripheral Interface is a full duplex bus targeted for small
distance communication within the embedded system. It consists of four signals
with maximum achievable data rates up to 1Mbps. Disadvantage of SPI over I2C
is the requirement of dedicated select line for each slave.
Table 2.1 summarizes the various serial protocols discussed above along with their
typical properties.
Name
Sync
Type
Duplex
Max
Pin Count
Devices
(KBPS)
Distance Ft
RS-232
No
peer
full
20
30
RS-422
No
multi drop
half
10
10000
4000
RS-485
No
multi point
half
32
10000
4000
I2C
Yes
master/ slave
half
*1
3400
<10
SPI
Yes
master/ slave
full
*1
>1000
<10
3+1
on bus capacitance.
10
The third generation of mobile phones is responsible for moving from voice to data
centric systems. Now a days a single device can be used for telephony, a database,
a general purpose computer, a gaming machine, a music player and/or a digital
camera [3] . This also calls for an intelligent power management tackled by an
increased parallelism in the architecture. Various techniques applied for achieving
this include pipeline control, cache hit prediction, variable instruction length and
data compression for transmission. Current research in mobile devices
architectures for low power devices has concentrated in exposing the data pipeline
to the software, handling efficiently compressed variable length code, reducing
power consumption of caches and memory, and also in exploring extreme data
11
compression for saving transmission power [3]. Moore's law is increasing the
available computational power exponentially [3]. With more and more data centric
applications, mobile phones are evolving to be a more general device incorporating
everything that a modern computer has along with the basic voice transfer
functionality. This calls for an increased parallelism in mobile phone architecture.
Figure 2.3 depicts the TI OMAP44X architecture contained in most smart phones.
12
2.5 Conclusion
So far, we have discussed how each new generation of embedded mobile devices is
becoming smarter and more capable and how important it is to have powerful
design tools for designing such smart devices. In all these devices buses play a
vital role for transferring data within the system as well as enabling the device to
communicate with the outside world.. These have been discussed in detail to give a
better understanding of each protocol. Since there are many buses available for use,
choosing the right bus becomes a matter of high importance. With this arise other
issues such as what should be the deciding factor to choose the bus for your
embedded system. Even inside a specific set of buses there are questions about
how to deal with the overhead of switching between different buses and how this
overhead can be minimized to increase the overall efficiency of the system. In my
research an attempt has been made to address the above issues and a system has
been devised to reduce the switching overhead among various buses and thus
improve the overall efficiency of the system. I will be focusing mainly on serial
protocols used inside mobile phone embedded systems and will be exploiting UML
for designing a serial protocol bridge and implementing the same on FPGA.
15
Chapter 3
Design
3.1 Introduction
As discussed in the last chapter, serial communication plays an important role in
embedded systems. In this research a serial protocol bridge intended for mobile
phone applications is implemented. I2C and SPI serial protocols are invariably
deployed in all mobile applications. Thus an I2C SPI protocol bridge will provide
a way to communicate between various slave devices. This project will be based on
one of the available UML platform descriptions and will not be focusing on
making changes to the UML as such. Rather the focus will be on exploring serial
protocols used inside todays mobile devices.
A typical mobile phone mother board consists of a high speed processor at its heart
and various other peripherals such as keypad, LCD, camera, GPS, TV out, speakers,
microphone, etc. The processor uses some protocol to communicate with each of
these peripherals depending on the speed requirement. It contains a controller for
each of the protocols and each device is considered as a slave to one of the
controllers. For example, an I2C master is required for communication with an I2C
slave and an SPI master is required for communicating with an SPI slave. We will
be implementing a serial protocol bridge such that inter protocol communication is
16
There are various design methodologies for implementing such a protocol bridge.
First of all the detail of the various components of the bridge is to be decided.
Further each component will be implemented independently as a state machine
based on flow charts and state diagrams. Thus we will implement a module based
design. In rest of this chapter I will be putting some light on design methodology
used for implementing the serial protocol bridge.
winning master among various masters. Then the winning master generates the
clock and sends a start bit followed by the 7 or 10-bit address of the slave. All
communications in I2C are carried as an 8-bit transfer. The 10 bit address is broken
down into 7 bits and 3 bits and sent as 2 byte transfer. The 7-bit address is
appended with 1 additional R/W bit indicating whether a read or a write operation
is to be performed. In case a slave is not ready for data transfer it can keep the
clock line low as long as it is not ready for the transfer. This phenomenon is known
as clock stretching. After each successful byte transfer, an acknowledgment is sent
by the receiver. In case the master wants to stop a read operation it sends not
acknowledge signal (NACK). A more detailed description on I2C can be found at
[8]. Figure 3.1 shows a waveform for a typical I2C transaction. An I2C transaction
begins with a 'start' condition, followed by the address of the device we wish to
speak to, a bit to indicate if we want to read or write, the data written or read, and
finally a 'stop'. An I2C master is capable of communicating at 4 different speeds100kbits/s (standard mode), 400kbits/s (fast mode), 1Mbits/s (fast plus mode) and
3.4Mbits/s (high speed mode). Typical voltages used are 3.3 V and 5 V.
18
waveform for a typical SPI transaction. The line MOSI is 'master output' and
MISO is the 'slave output'. The master pulls SSEL down to indicate beginning of
communication to the slave. Since SPI is full duplex, both lines toggles
simultaneously, with different data going from master to slave and slave to master.
Master pulls SSEL up to indicate transfer is over. Master can keep SSEL low until
communication is not over and pulls SSEL high only to indicate that transfer is
over. Typical SPI frequency is 100MHz.
21
22
23
Figure 3.5 Sequence diagram for I2C master write use case.
24
Figure 3.6 Sequence diagram for I2C master read use case
25
26
27
Figure 3.9 Sequence diagram for I2C slave write use case.
28
Figure 3.10 Sequence diagram for I2C slave read use case.
29
30
Figure 3.13 Sequence diagram for SPI master data exchange use case.
31
32
33
Figure 3.17 SPI master writes to I2C slave through serial protocol bridge.
34
Figure 3.18 I2C master writes to SPI slave through serial protocol bridge.
Similarly a read can be done in the reverse order. That is, the master inside the
bridge can do a read operation on its corresponding slave which is outside the
bridge and store the read data into the shared memory. And then the master
(outside the bridge) of the other protocol can perform a read operation on the slave
device which is part of the bridge. The goal achieved is a read operation performed
on the slave of one protocol by the master of another protocol. Figure 3.19 and
Figure 3.20 depicts the operation described above.
35
Figure 3.19 SPI master performs read on I2C slave through serial protocol bridge.
Figure 3.20 I2C master performs read on SPI slave through serial protocol bridge.
36
37
3.6 Conclusion
So far we have discussed various ways in which the serial protocol bridge can be
implemented. We have also seen how we can break the whole design into 4 main
modules and we have used UML 10.0 to design each of the modules
independently. Use case diagrams, state diagrams and sequence diagrams have
been used to design the fully working modules and further block diagrams have
been used to combine these modules into the serial protocol bridge. Now we can
move further into implementation of each of the designed modules. Next chapter
will comprise the implementation details along with simulation of the four
modules that we have designed in this chapter.
38
Chapter 4
Implementation
4.1 Introduction
In the previous chapter we have designed the four basic modules for an I2C-SPI
serial protocol bridge using UML 10.0. We have also seen how each of these
modules can be represented using a state machine diagram. In this chapter we will
be focusing on how each of these state machines can be implemented using HDL
(hardware description language). In industry standards two main hardware
languages are used in order to simulate and test the designs before actually
experimenting with the hardware. These are VHDL (very high speed integrated
circuit hardware descriptive language) and Verilog [11, 13]. Both these languages
have their specific uses. Verilog is used where gate level implementation is
required whereas VHDL is more useful while implementing system level modules.
While implementing a state machine we will define certain commands that will
decide transition from one state to the next. Here each command will be driving
signals and data through multiple states. All the commands will have one common
state that helps in easy transitioning between successive commands. In the rest of
the chapter we will describe the four basic modules of the serial protocol bridge
along with their combinations which we have implemented in order to form the
complete bridge. Each of our designs has been implemented in VHDL and
instantiated on ALTERA DE-115 board with a CYCLONE IV E chip. In this
chapter we will be describing simulation waveforms. All the simulations have been
done in ModelSim ALTERA STARTER EDITION 6.5e.
commands. Master also has an 8-bit memory in order to save the received bit.
Figure 4.1 shows typical I2C master state machine waveforms. It depicts the
transitions on SDA line during each command. Table 4.1 describes various state
transitions involved in each of the valid I2C master commands.
Command Name
Command Code
State Transitions
SDA Transitions
START
010
1011
STOP
010
101
READ
100
sent by master 1
WRITE
101
1
NOP
000
idle
41
jumps to either read or write state depending on the value of read/write bit sent by
I2C master. Hence I2C slave cannot be commanded to read or write directly by the
host. Figure 4.2 shows typical I2C slave waveform.
43
44
Command Name
Command Code
State Transitions
Signals Involved
CONFIG
010
idle config_a
SCLK
config_b config_c
idle
EXCHANGE
idle exchange_a
100
SCLK,MISO,MOSI,SS
exchange_b idle
NOP
000
idle
45
none
46
47
Figure 4.6 SPI interface waveform (master is reading back after writing)
48
Now, as we have two interfaces ready, we will be combining these two interfaces
together in order to form the complete bridge. Hence the bridge now is going to
have these two interfaces as its components rather than 4 modules as its component.
The state machine for the complete or full serial protocol bridge is then going to
have four different modes- I2C_WRITE_SPI, I2C_READ_SPI, SPI_WRITE_I2C
and SPI_READ_I2C. These four modes are basically four different ways bridge
can be used. Along with two interfaces complete bridge will also be having shared
memory. There are two 8-bit registers in order to share data. One register is used
for sharing data between I2C slave and SPI master and the other one is used in
order to share data between I2C master and SPI slave. This has been done so that
the serial protocol bridge can be used in any of the four possible modes. Figure 4.7
depicts block diagram of serial protocol bridge having two interfaces and two
shared memories. Figure 4.8 depicts waveform of serial protocol bridge in
I2C_WRITE_SPI mode. Figure 4.9 depicts waveform of serial protocol bridge in
I2C_READ_SPI mode. Figure 4.10 depicts waveform of serial protocol bridge in
SPI_WRITE_I2C mode and Figure 4.11 depicts waveform of serial protocol bridge
in SPI_READ_I2C mode.
49
50
Figure 4.8 I2C master writes to SPI slave through serial protocol bridge
Figure 4.9 I2C master reads SPI slave through serial protocol bridge
51
Figure 4.10 SPI master writes to I2C slave through serial protocol bridge
Figure 4.11 SPI master reads I2C slave through serial protocol bridge
52
53
Core Voltage
1.2V
Logic Elements
114480
I/O pins
529
Memory Bits
3981312
532
PLL
Global clocks
20
temperature
0-85(Celsius)
55
4.9 Conclusion
In this chapter we have successfully done the simulation of all the modules
designed in the previous chapter. Two interfaces were designed, simulated and
implemented successfully. We have also successfully demonstrated the fully
functional serial protocol bridge in all possible modes. Hence the inter protocol
communication was made possible using the bridge and the same has been
depicted in the waveforms generated through test benches.
56
Chapter 5
Conclusion
Firstly we have discussed the available protocols needed for transmitting data from
one peripheral to another. The background chapter also sheds light on the
57
During the design phase we have used an existing UML platform for designing the
modules in our design. We described the four basic modules of serial protocol
bridge- I2C slave, I2C master, SPI slave and SPI master using use case diagrams,
sequence diagrams and state diagrams. The elaborated sequence diagrams and state
diagrams helped us in clarifying the basic concepts of I2C and SPI protocol
communication. In the end of the chapter final bridge formation was discussed and
block diagrams were included to demonstrate how the basic modules could be
combined to allow communication between I2C and SPI devices.
state machine was implemented that included the two previously generated
interfaces as its components along with two shared 8-bit registers. This final state
machine could work in four modes. Below is a list of the four modes in which the
state machine could be used
a) I2C master writing to SPI slave
b) I2C master reading from SPI slave
c) SPI master writing to I2C slave
d) SPI master reading from I2C slave
By using this bridge we are able to solve the issue discussed in chapter 1 where
each device was required to be slave to all the protocols it was communicating
with. With this bridge each peripheral needs to be slave to only one protocol. This
will reduce the wiring and as a result reduce the overall size of the device.
59
Future prospects
This research has been concluded with a fully functional I2C-SPI serial protocol
bridge. It has been simulated for ALTERA board and can be used in real time
scenarios by adding protocol compatible slave devices to the board. All the
simulations have been done in VHDL and can be done for other languages as well.
This bridge can be tested for actual size reduction of mobile devices. This can
improve the on-board communication among different peripherals and thus can
improve overall efficiency of the system. A good exercise will be
1.
To add ALTERA specific protocol to the bridge and communicate with the
Add USB protocol to the bridge and communicate with the mouse and other
USB devices.
3.
Add RS-232 protocol to the existing bridge and make it communicate with
the PC.
4.
We can also add parallel protocols to the existing serial protocol bridge and
We can add I2C or SPI specific slave devices and use bridge to communicate
with them. Most widely used I2C device for test purposes is RTC chip. Dont
forget to change clock speeds of the prototype before using it with actual I2C or
SPI slave.
60
References
[1]http://www.eetimes.com/design/embedded/4023975/Serial-Protocols-Compared,
May 31 2002
[2] A. K. Oudjida, M. L. Berrandjia, R. Tiar, A. Liacha, K. Tahraoui, FPGA
Implementation of I2C & SPI protocols: a comparative study, 16th IEEE
International Conference on Electronics, Circuits, and Systems, December 2009,
pp. 507-510.
[3] Margarita Esponda, Trends in Hardware Architecture for Mobile Devices,
Technical Report B-04-17, Freie Universitt Berlin, Fachbereich Mathematik und
Informatik, November 2004
[6] http://en.wikipedia.org/wiki/Field-programmable_gate_array
[7] Jan Jrjens, Secure Systems Development with UML, Springer Publications,
2005, ISBN 978-3-540-00701-2
61
[10] http://www.ti.com/lit/ml/swpt034b/swpt034b.pdf
[11] Douglas J Smith, HDL Chip Design: A Practical Guide for Designing,
Synthesizing and Simulating ASICs and FPGAs using VHDL or Verilog, Doone
Publications, 1996 ISBN 0-9651934-3-8
[12] http://www.angelfire.com/in/rajesh52/verilogvhdl.html
[13] G. Martin, L. Lavagno, J. Louis-Guerin, Embedded UML: a merger of realtime UML and co-design, Proceedings of CODES 2001, Copenhagen, Apr. 01, pp.
23-28
62
Appendix A
63
64
----------------------------------------------------------------------Clocks
----------------------------------------------------------------------Clock Name Type Period Frequency Rise Fall
SCL
Base 1.000 1000.0 MHz 0.000 0.500
-------------------------------------------------------------------------------------------------------------Slow 1200mV 85C Model Fmax Summary
-------------------------------------------------------------------------------------------------------------Fmax
Restricted Fmax Clock Name Note
297.53 MHz 237.53 MHz
SCL
limit due to minimum period restriction
--------------------------------------------------------------Slow 1200mV 85C Model Setup Summary
---------------------------------------------------------------Clock Slack End Point TNS
SCL -2.361 -32.188
----------------------------------------------------------------Slow 1200mV 85C Model Hold Summary
----------------------------------------------------------------Clock Slack End Point TNS
SCL 0.384 0.000
---------------------------------------------------------------------------------Slow 1200mV 85C Model Minimum Pulse Width Summary
---------------------------------------------------------------------------------Clock Slack End Point TNS
SCL -3.210 -58.465
66
--------------------------------------------------------------------Clocks
--------------------------------------------------------------------Clock Name Type Period Frequency Rise Fall
clk
Base 1.000 1000.0 MHz 0.000 0.500
-----------------------------------------------------------Slow 1200mV 85C Model Fmax Summary
------------------------------------------------------------Fmax
Restricted Fmax Clock Name
211.15 MHz 211.15 MHz
clk
--------------------------------------------------------Slow 1200mV 85C Model Setup Summary
---------------------------------------------------------Clock Slack End Point TNS
clk -3.736 -115.546
---------------------------------------------------------Slow 1200mV 85C Model Hold Summary
----------------------------------------------------------Clock Slack End Point TNS
clk 0.384 0.000
-----------------------------------------------------------------------------Slow 1200mV 85C Model Minimum Pulse Width Summary
-----------------------------------------------------------------------------Clock Slack End Point TNS
clk -3.000 -65.965
68
-----------------------------------------------------------------Clocks
------------------------------------------------------------------Clock Name Type Period Frequency Rise Fall
SCLK
Base 1.000 1000.0 MHz 0.000 0.500
---------------------------------------------------------Slow 1200mV 85C Model Fmax Summary
---------------------------------------------------------Fmax
Restricted Fmax Clock Name
101.64 MHz 101.64 MHz
SCLK
-----------------------------------------------------Slow 1200mV 85C Model Setup Summary
------------------------------------------------------Clock Slack End Point TNS
SCLK -8.839 -345.742
70
72
73
------------------------------------------------------------Clocks
------------------------------------------------------------Clock Name Type Period Frequency Rise Fall
clock
Base 1.000 1000.0 MHz 0.000 0.500
-------------------------------------------------------------------------------------------------------------Slow 1200mV 85C Model Fmax Summary
----------------------------------------------Fmax
Restricted Fmax Clock Name Note
185.25 MHz 185.25 MHz
clock
----------------------------------------------------------------------------------Slow 1200mV 85C Model Setup Summary
----------------------------------Clock Slack End Point TNS
clock -4.398 -275.261
---------------------------------------------------------------------Slow 1200mV 85C Model Hold Summary
---------------------------------Clock Slack End Point TNS
clock 0.384 0.000
-----------------------------------------------------------------------------------Slow 1200mV 85C Model Minimum Pulse Width Summary
------------------------------------------------Clock Slack End Point TNS
clock -3.000 -119.935
-------------------------------------------------
74
----------------------------------------------------------------------------Fitter Summary
----------------------------------------------------------------------------Fitter Status
Successful - Thu Aug 09 18:11:18 2012
Quartus II Version
10.0 Build 218 06/27/2010 SJ Web Edition
Revision Name
I2C_SPI_BRIDGE
Top-level Entity Name
I2C_SPI_BRIDGE
Family
Cyclone IV E
Device
EP4CE115F29C7
Timing Models
Final
Total logic elements
386 / 114,480 ( < 1 % )
Total combinational functions 385 / 114,480 ( < 1 % )
Dedicated logic registers
163 / 114,480 ( < 1 % )
Total registers
163
Total pins
69 / 529 ( 13 % )
Total virtual pins
0
Total memory bits
0 / 3,981,312 ( 0 % )
Embedded Multiplier 9-bit elements 0 / 532 ( 0 % )
Total PLLs
0/4(0%)
75
------------------------------------------------------------Clocks
-------------------------------------------------------------Clock Name Type Period Frequency
Rise Fall
clk
Base 1.000 1000.0 MHz 0.000 0.500
--------------------------------------------------------------
76