1

IEEE PES General Meeting 2014, July 27-31, Washington DC

Lighting systems
Light sources in modern buildings:
characterization, modeling and simulations
Panel Session: New Harmonic Sources in Modern Buildings

Jiri Drapela
Brno University of Technology, Czech Republic

Roberto Langella
Second University of Naples, Iatly

Lighting technologies for general lighting in modern buildings

About 20% of electricity worldwide is consumed by artificial illumination system, thus by light
sources (lamps) of different types

Direction according to market studies

(residential, public buildings and commercial sectors)
High intensity discharge, halogen lighting and incandescent bulbs in withdrawal
Fluorescent lighting run over and then withdrawal
LED lighting taking market, increasing penetration

Only fluorescent lamps fed by electronic ballasts and LED systems are taken into consideration
in the presentation

Lighting technologies for general lighting in modern buildings

Design of converters for lamps vs. Emissions of harmonic current

Emissions are related to circuitry of supply units (ballast and converters/ drivers) which design is subject to
following factors:
application (replacement of lamps, for designated luminaires, for illumination systems with specific
distribution system, )
qualities (dimming, communication, etc.)
requirements of related standards
production costs

Design variations related to application

light source

integrated design
(converter inseparable from lamp)

mains

external converter for specific no. of lamps

mains

converter feeding specific distribution system

with independently controlled lamps

mains

conv.
luminaire

conv.

conv.

luminaire

luminaire

conv.

conv.

Requirements for converters for lamps (standards)

to ensure correct operation of a lamp (fluorescent tube, LED) in all operational states
requirements for safety
EMC requirements in terms of immunity
limitation in emissions

Lighting technologies for general lighting in modern buildings

Direct or indirect requirements on /specifications for ballasts and converters design according to
the (EU) standards (brief overview)

Luminaire general (particular),

performance and safety
requirements and tests

Lamp controlgear general

(particular), performance and
safety requirements

EN 60598-x-y standard series.

EN 61347-x-y standard series.

EN 60921. Ballasts for tubular

fluorescent lamps.

EN 60921. Ballasts for tubular

fluorescent lamps.

..

Lamp performance and safety

specifications
EN 60081 and EN 61195. Doublecapped fluorescent lamps.
EN 61167. Metal halide lamps.

Luminaire, controlgear EMC requirements and tests

EN 61547. EMC Immunity requirements.
EN 61000-4-y standard series.

EN 55015. Radio frequency emission limits.

EN 61000-3-2. Limits for harmonic current emissions
.

Electronic Ballast (EB) for Fluorescent Lamps (FLs) - topologies

Typical circuits of EB for FLs

i

Rectifier
L

Inverter

vB

FL is fed from a Half-bridge resonant

voltage source (or from a Push-Pull)
inverter which is supplied from a source of
DC voltage

iI

vL iL

230V ~

CB

EMI Filter
Driver

Ouput stage

with capacitive PFC

circuit

rectifier

with inductive PFC

circuit

LPF

/2

screw-based
screw-based
CFLs (P25 W)
CFLs

NPF

Single-Stage (S-S)
topology

i
/2

with active PFC

circuit

double stage
topology

i
/2

screw-based CFLs
(small choke
Discontinuous
Current Conduction
(DCC) - LPF)
external EB for
LFLs (big choke
Continuous CC

HPF

external EB
for LFLs
and CFLs

/2

screw-based
CFLs
external EB for
CFLs and LFLs

Drivers (power supplies) for LEDs - topologies

Typical circuits of Drivers/Power supplies for LEDs

v
N

CB

non-isolated

CD
i
Voltage
L
divider, used v
for very low
inp. power N
i

CB

There are used the same PFC

techniques as in case of EBs.
A map is at at next slide

vL

iI

iL

Optimized to supply voltage level;

series string of 10-35 mA LEDs (LowPower LEDs)

LBK

vL

PWM

iL

vB
iI

isolated

vL

PWM

iI

iL

Buck conv. universal input;

Const. Current (CC) or Const. Voltage
(CV) output; driver for LP or power
LEDs
Flyback conv. universal input; CC
or CV output; driver for power LEDs
or power supply for LED track,
luminaries or lamps

Cr

vL
Lr1 Lr2

iL

Half-Bridge (HB)
resonant conv.
universal input; CC or
CV output; driver for
power LEDs or power
supply for LED track,
luminaries or lamps

Drivers (power supplies) for LEDs - topologies

Typical circuits of Drivers/Power supplies for LEDs Power Factor Correction

i
L

iI

CB

vL

iL

vB PWM

with capacitive PFC

circuit

rectifier

with inductive PFC

circuit

LPF

/2

NPF

Single-Stage (S-S)
topology

i
/2

with active PFC

circuit

double stage
topology

i
/2

screw- or other external drivers screw- or other capcap- based

for LEDs
based LED lamps
LED lamps
(small choke
(P25 W)
Discontinuous
also external
Current Conduction
drivers for high
(DCC) - LPF)
power apps
(P>25 W)

HPF

/2

external drivers external drivers

for LEDs and
for LEDs and
power supplies
power supplies
for tracks,
for tracks,
luminaries or
luminaries or
lamps
lamps

Modeling of lamps with converters

Modeling in time domain

Full / switching models even if simplified/ optimized for specific purposes
Utilization of an accurate model of lamp itself if fed from an electronic converter is not
so important for input to input response as the convertor model is. (For Low/Frequency
(LF) conducted disturbances study).
Simulations of switching models behaviour are very time consuming.and thus are
not suitable for response prediction of large systems or for simulation of long term
disturbances
Since information about switching components in input current for mentioned studies is
very minor simplifications in modeling can be made
Simplified models
linearization
linearized models
averaging
averaged models
Simplified models are created to keep information about LF bandwidth behaviour, i.e.
about LF conducted disturbances
Modeling in frequency domain
There are also models and procedures to obtain models for modeling of disturbing
loads in frequency domain
Fixed current sources based equivalent models
Norton equivalent models cross-harmonic complex admittance models

Basic EB for CFL

Modeling of FL at HF
Rectifier
L

Inverter

vB

iI

vL iL

230V ~

CB

EMI Filter
Driver

Ouput stage

Based on dynamic AV characteristic curve of a discharge in

normal operation if supplied by HF current, a FL can be
substituted by a resistance
It is acceptable if DC voltage ripple (vB) is reasonable (up to
30%), otherwise different model has to be used to keep
correctness, for instance voltage driven resistance, etc.

Lamp voltage and current .Line voltage and current, .

DC bus voltage
vL (V), iL /300 (A)
v (V), i /300 (A), vB (V)

Experimental results: CFL of about 20 W, 230 V @ 50Hz

Lamp voltage and current .

vL (V), i L /300 (A)

Then model (switched model) of an EB can be drawn as

follows:
ZS

LF

RF

LR
RL

CF

CF
CB

350
250
150

vB
i

50
-50
t TO

-150
-250
a)
-350
150
vL

100

iL

50
0
-50
-100
-150

d)
0

10

150

vL

100

15

20

25

30

Time (ms)

50
0

iL

-50
-100
-150
0

0.05

Time (ms)

0.1

0.15

200
150
Lamp voltage vL (V)

for

100
50
for

0
-50
-100
-150
-200
-0.4

-0.2

0
Lamp current i L (A)

0.2

0.4

10

Basic EB for CFL

Simple switched model of a CFL with basic EB
Simulation results

+
D4

M1
IRF840

6.8

V4

.05

D6

VOFF = 0
VAMPL = 325
FREQ = 50
N

R5

D2

2mH
3

0.4

R10
2

L2
1

R1

Model in PSpice of a 18W CFL

R8
10k

V1 = 0
V5 V2 = 10
TD = 10u
TR = 0.5u
TF = 0.5u
PW = 9u
PER = 20u

C6
6.8u

0
D3

M2

R7

D7
D5

.05

IRF840

R9
-

10k

0A

lamp_L
33n

V1 = 0
V6 V2 = 10
TD = 0
TR = 0.5u
TF = 0.5u
PW = 9u
houtN
PER
= 20u

700mA

400mA

L4
houtL
C7

400V

200V

0V

2.3mH
C8

R6
430

-400mA

-200V

6.8n
lamp_N

Switching models are only necessary when switching

ripples are of interest or detailed transient information is
needed
It slows down computing (switching frequency is
thousand times higher then system frequency) and
information about High Frequency (HF) ripple is useless
from point of view of Low-Frequency (LF) disturbances
propagation study

>>
-700mA

-400V
20ms
1

I(R1)

30ms
V(L)- V(N)

40ms
V(+)- V(-)
Time

50ms

60ms

120mA

1.0A

80mA
1.0uA

40mA

1.0pA
0Hz

125KHz
I(R1)

250KHz

375KHz

0A
0Hz

2.0KHz

4.0KHz

I(R1)
Frequency

Frequency

Waveforms of supply voltage (red), input current

(green) and of DC bus voltage (blue);
Spectra of input current: full and LF part,
THDI=146% (up to h=50)

11

Basic EB for CFL

Simplification of the inverter stage
Rectifier
L

Inverter

vB

iI
vL iL

230V ~

CB

Line voltage and current, .

DC bus voltage
v (V), i /300 (A), vB (V)

Experimental results: CFL of about 20 W, 230 V

@ 50Hz

Driver

Ouput stage

Switching frequency of inverter is constant in steady-state and

normal operation; the inverter control circuit does not contain
regulation of the lamp current
Then, for LF phenomena study purposes, the inverter with
output stage and lamp can be replaced by an equivalent linear
resistance of constant value (representing the same limitations
as in case of the lamp substitution). Switching signals of the
inverter are de facto averaged over the switching period.
Simplified model of the basic EB for CFL is as follows:
ZS

RF

LF

350
250
150

vB
i

50
-50
t TO

-150
-250
-350
0.4

a)
i IF

0.3

iI

0.2
0.1
0
-0.1

b)

-0.2
5000
4000
3000
2000
1000

c)

10

REL

15
Time (ms)

REL (t ) =

vB
iIF

*) iIF is filtered current iI

CB

CF

Inverter current
iI (A), iIF /4 (A)

EMI Filter

Equivalent DC bus load .

R EL ( )

20

25

30

12

Basic EB for CFL

Simplified model of the basic EB for CFL
Simulation results

Model in PSpice of a 18W CFL

L2

R1

+
L R10

0.4

2mH

400V

500mA

D4

D2

V4

C6
3

6.8
3

VOFF = 0
VAMPL = 325
FREQ = 50

R6
6.8u

0V

1
D3

0A

5k

-500mA

D5
3

>>

Simulation results in term of LF part of input current conform

with the results obtained for corresponding switching model

-400V
560ms
1

I(R1)

570ms
V(L)- V(N)

580ms
V(+)- V(-)
Time

590ms

600ms

120mA

80mA

40mA

0A
0Hz

2.0KHz

4.0KHz

I(R1)
Frequency

Waveforms of supply voltage (red), input current

(green) and of DC bus voltage (blue);
Spectra of input current: THDI=146% (up to h=50)

13

Basic EB for CFL

Basic EB for CFL performance analysis based on simplified model
Scheme composed only of essential parts
Rser

Lser

CB

REL

Expression of fr comes from circuit series

impedance:

Z = Rser

REL
1
+ j Lser
+
2
2

1 + ( C B REL )
1 + ( C B REL )

2
2 C B REL

10000

Magnitude and shape of input / line currrent (i.e.

power and spectral components) are full given by
value of Rser, Lser, CB and REL and by their correlation
input power is mainly represented and thus
estimated by REL
line current waveform is matter of balance in
charging and discharging process over half
system period given by CB in relation to REL.
An invariant parameter describing the rectifier
load there is C load/converter time constant:

C = C B REL
serial combination of Lser and CB constitutes a
series resonant circuit influencing input current
by self-oscillations at resonant frequency fr. The
resonant frequency is second invariant
parameter of the rectifier.

1000
|Z | ( )

100

L ser = 5H

2H

10
C B =10 F

R EL =5150

0.1

1H

0.5H

0.2H
0.1H
5mH
50mH
2mH
20mH
1mH
0.5mH
10mH

C =51.5 ms

10

100

1000

f r (Hz)

10000

Thus fr is as follows:
fr =

1
1
1
1

2 2 =&
2 C B Lser CB REL 2 CB Lser

the last one component there is Rser which

smooths line current and which can be
normalized by CB in form of series time constant
or by equivalent capacitive reactance at
fundamental frequency:

S = CB Rser

rS =

Rser
= 1C B Rser
X CB

14

Basic EB for CFL

Basic EB for CFL performance analysis based on simplified model (cont.)
Influence of C
To comply with harmonic current emission limits
and to maintain reasonable DC voltage ripple, the
C of CFLs is in range (10)-15-50-(70) ms

350

The larger C the shorter conduction time of the

rectifier and higher content of harmonics in input
current

200

Simulation results for various C while Rser=0 ,

Lser=0 H:

250

I (mA)

THD I(I1) (%), h 40

150
100
50
0
1000

THD I(I) (%), h 40

VB (%)
100

C (ms)

26 ms
52 ms

50

I 1 /I 1

75

103 ms
258 ms
515 ms
1030 ms

10

Chosen circuit quantities vs. load/ converter time

constant
100

C =10 ms

75

V B,avg

300

(Ih/I1 ).100 (%)

100
(Ih/I1 ).100 (%)

I 3 /I 1
I 5 /I 1

50
I 15 /I 1 I 13 /I 1 I 11 /I 1 I 9 /I 1 I 7 /I 1

25

25

37

h (-)
33

29

25

21

17

13

0
1

Relative amplitude spectrum of line current for various

load/converter time constants

0
1000

100

C (ms)

10

Relative amplitudes of chosen harmonics vs. load/

converter time constant

15

Basic EB for CFL

THD I(I) (%), h <40

V B (%)
10
10000

1000

100

100

f r (Hz)

10

f r (Hz)

10

I1
I3

75

I5
I7

50
I9
I 11
I 13

25

I 15
0
10000
100

1000

100

fr=712 Hz
503 Hz
356 Hz
225 Hz
113 Hz
36 Hz

75

1125 Hz
1592 Hz
2251 Hz
16 kHz
Hz

50

25

37

h (-)
33

29

25

21

17

0
13

Simulation results for various fr , for Rser=0 and C=51.5

ms:

THD I(I1) (%), h <40

With decreasing resonance frequency the self-oscillation

wave frequency is traveling to lower harmonic order while
multi conduction of the input current in each half-period can
occur

100

Inductance Lser is composed of three parts representing: a

choke in ac or dc part of rectifier smoothing and improving
current shape, inductance of an EMI filter, if there are
employed; and effective inductance of supply network. The fr
can be practically in range from 17 kHz to 400 Hz

V B,avg (V)

Influence of fr

1000

(Ih/I1 ).100 (%)

Basic EB for CFL performance analysis based on

simplified model (cont.)

(Ih/I1 ).100 (%)

16

Basic EB for CFL

Basic EB for CFL performance analysis based on simplified model (cont.)

Influence of S
Resistance Rser consists of series combination of the supply network effective resistance, used chokes
resistances and resistance of a resistor applied in input side of EB to limit inrush current (~ Ohms).
The Rser attenuates line current shape and possible resonant oscillations in the current and S can be
practically in range from 0.2 s to 0.2 ms
Summary
The input current waveform is invariant if the rectifier invariant parameters C, fr and S are of the same
value
1

En example (simulation results):

120mA

1.2A
2

80mA

0.8A

40mA

0.4A

10A

0A

C=51.5 ms , fr=1592 Hz, S=7.5 s

Rser=7.5 , Lser=1 mH, CB=10 F, REL=5150 (blue)
Rser=0.75 , Lser=0.1 mH, CB=100 F, REL=515 (green)

0A

>>
0A
0Hz
0.5KHz
0Hz
0.5KHz
1 I(R2)
I(R2)

-10A
1.480s 1.485s
I(R2)

1.490s

1.495s

Time

1.0KHz
1.0KHz

1.5KHz
1.5KHz

2.0KHz
2.0KHz

2.5KHz
2.5KHz

Frequency
Frequency

Analytical solution
Except numerical simulation, the resulting input current waveform can be obtained from solution of
analytical description of the simplified model. The most critical part of it there is to find out conduction
angles bounding CB capacitor charging and discharging areas, especially in case of multi-conduction

3.0KHz
3.0KHz

17

EB with passive PFC

Division of the passive PFCs (patterns)

Passive PFC techniques introduced to reduce harmonics content to meet standards requirements for
harmonics emissions
- capacitive passive PFC ValleyFill (VF)

- inductive passive PFC

i

LF,AC

LF,DC
ig

iI

i
CB

vB

ig

- other variants of the Valley-Fill

(some of them)
i

ig

C VF1 D VF3

D VF2

C VF1

vB

Behaviour (contribution) is fully

described in the section of basic
EB for CFL simplified model
performance analysis
Large chokes at DC side for PF
correction of EB with input
power above 25 W are not used
anymore

Utilization of the VF may involve EB

(P>25 W) to comply with current
limits for harmonics
VF capacitors are charged in series
and discharged to load in parallel,
connection is provided by network of
diodes
Due to this, DC bus voltage vary
between rectified voltage peak and
drops at least to half of the peak
value

iI
vB

D VF2 RVF
D VF1

D VF1 C VF2

Proper size to smooth current in

the case of CFLs (P25 W), if
necessary, used on both the AC
and DC sides. Coke size is
usually quite small -> harmonics
content stays very high

D VF3
LVF

ig

C VF1 D VF3

D VF2
D VF1

C VF2

D VF4

C VF2

iI
D VF6

C VF3

CVF1

CpH RpH

vB

D VF5

iI

RVF1

RVF2 vB

CpL RpL
CVF2

18

Double-stage active PFC EB

Typical circuit of double-stage active PFC EB

Measurement results

i
L

230V ~
N

LBT

ig
2xLHF
2xCHF

vg

PWM

Controller

iD
iT

vB
CB

iI
vL iL

PFC circuit

Active boost type PFC, in dependences on employed regulation

loops, emulates EB input to be like a resistor and regulates output
voltage (vB) on reference, i.e. on constant output power, thus whole
the inverter part including lamp can, for modeling, substituted by
resistance again, if interested in the line current
The PFC can work in Discontinues- Continuous- or Critical
Conduction Mode (DCM, CCM, CrCM) with corresponding (various)
switching control strategies, for example:

19

Double-stage active PFC EB

Switching model of an active PFC for EB
Simulation results

Model in PSpice
R1

RsL

L1

Lp

Dout

Rstart
100k

drain
162m

1.1mH

MUR130

1mH

HV
0.0001

U2

FREQ = 50
VAMPL = 325
VOFF = 0

C2

C1

100n

22n

D100
DN4722

RuppM
2.2Meg

D101
DN4722

Rupp
Resr
1.59Meg
70m

XFMR1
0.04692
Rs

Cin
330nF

MTP8N50

Vinput

drv
L2

D1

13m

RlowM
18k

1mH

Rload
X1

4444

Rzcd
Rlow
10k

CMUL
DN4934

Cout
40uF

22k

10nF

cs
100uF
D103
DN4722

D102
DN4722

CVcc

Rsense
2.5
-

Ccmp
0.68uF
U1
cmp
mul

MC33262

FB

VCC

CMP

DRV

MUL

GND

CS

ZCD

MC33262

5.0
4.5
4.0

Again, computing is very time consuming

3.5
3.0
2.5
2.0
1.5

h (-)

Waveforms of supply voltage (blue), input current

(green) and of DC bus voltage (red);
Spectra of input current: THDI=5.1 % (up to h=50)

39

33

27

21

15

1.0
0.5
0.0
9

Content of LF harmonics is very small (THDI practically up to

15%). On other hand PFC causes different time variations in
input current when supply voltage magnitude is varying (in
depencance on regulation scheme)

(IhI1).100 (%) .

Model represents full controlling with CrCM control strategy, it

means switching frequency is changing within period

20

Double-stage active PFC EB

D-S Active PFC EB response to voltage changes
Measurement results
Voltage dip to from 230 to 90 V, duration time of 150 ms

200

-200

-1
v

I(RMS1/2p)

-400
0

50

Line current i, I (A)

400
Supply voltage,v (V)

100

150
Time, t (ms)

200

250

-2
300

Simulations using switching models are extremely time consuming.

The solution is to apply an averaging technique to obtain an Averaged-switch model
Averaged switch modeling allow us to predict steady-state characteristics and Low-bandwidth
dynamics of converters

21

Double-stage active PFC EB

Averaged model of the boost rectifier circuit

Signals are averaged over switching period. Average models change the
discontinuous system into the continuous system

Switch network

Substitute for switch-diode combination of the boost DC/DC conv. suitable

for both the DCM and CCM with fixed switching frequency fs and variable
duty cycle ratio d:

Boost rectifier becomes ideal, assuming

that inner wide/bandwidth current
controlling loop operates ideally
High-frequency switching components
removed by averaging
CCM/DCM boundary:

CCM
d;

d
; DCM
u=
i1
2
d + 2 LBT f S

v2

2
d

u = MAX d ,

i
2
1
d
+
2
L
f
BT
S

v2

Line current low-frequency components

remain
Resulting model in nonlinear and timevarying

22

Double-stage active PFC EB

Averaged model of the boost rectifier circuit (cont.)

Model in PSpice

Simulation results
500V

300mA

400mA

200mA
0V

0A

100mA

>>
-400mA
0.980s
0.985s
V(L)- V(N)
V(+)- V(-) 2

-500V
1

Controlling loop cover Low-bandwidth DC

voltage loop only. A part correcting d based on
input voltage waveform is not employed. Thus
line current distortion is bigger than in case of
full voltage loop implementation
The first order PI controller integral time constant
is about 20 ms, it means that cut-off frequency of
corresponding transfer function is at approx. 8
Hz

0.990s
I(R0)
Time

0.995s

0A
0Hz

0.25KHz
I(R0)

0.50KHz

0.75KHz

Frequency

Waveforms of supply voltage (green), input current (blue) and

of DC bus voltage (red); Spectra of input current: THDI=27.3 %
(up to h=50)
500V

300mA

400mA

200mA
0V

0A
100mA

>>
-400mA
0.980s
0.985s
V(L)- V(N)
V(+)- V(-) 2

-500V
1

0.990s
I(R0)
Time

0.995s

0A
0Hz

0.25KHz
I(R0)

0.50KHz

0.75KHz

Frequency

Waveforms of supply voltage (green) distorted by 3rd and 5th

harm. (10%-0; 5%-180), input current (blue) and of DC bus
voltage (red); Spectra of input current: THDI=17.6 % (up to
h=50)

23

Double-stage active PFC EB

Averaged model of the boost rectifier circuit (cont.)

Response of the model on slow and rapid
supply voltage changes:

Simulation results
1

a) voltage step from 230 to 115 V (sinusoidal

waveform)

500V

0V

1.0A

0A

-500V

>>
-1.0A
400ms
1

450ms
V(L)- V(N)

500ms
V(+)- V(-)

550ms
I(R0)

600ms

650ms

700ms

750ms

800ms

650ms

700ms

750ms

800ms

Time

b) voltage dip from 230 to 115 V for 100 ms

(sinusoidal waveform)

500V

6.0A

4.0A
0V
2.0A

-500V

0A
>>
400ms
1

450ms
V(L)- V(N)

500ms
V(+)- V(-)

550ms
I(R0)

600ms
Time

Waveforms of supply voltage (green), input current (blue) and

of DC bus voltage (red);

24

Single-stage active PFC EB

Typical circuit of Single-Stage (S-S) active PFC EB

i
L

230V ~

S1

ig

v
2xLHF
2xCHF

CB
Lr

DBT
LBT

S2

Some of other variants

vL

Cin1 S1

vB
iL

LBT
S2

Cin2

Cr

Dx

Dy

CB

Cin

S1

Lr

- typically w/o regulation loops

- DC bus voltage is of natural behavior depending on
employed circuit which can lead to:
- up to double of standard DC voltage level or
- serious DC bus voltage variation causing periodical
drift of lamp operating point, it means modeling of
lamp by a resistance could be inaccurate

Cr
DBT1

Cin1

Lin

Cin2
S2

Cr

Some of characteristics:
-switching frequency is fixed in steady-state (normal
operation)

CB

Lr

In order to reduce production costs, Single-Stage

topologies were introduced. S-S topology is able to
provide some of D-S functionalities: input emulates
resistor and feeding of lamp is ensured, EB does not
regulate DC bus voltage and so lamp voltage (current)

DBT2

Measurement results

S1

CB
Lr

Lin
S2

Cr

25

Single-stage active PFC EB

Switching model of an S-S active PFC for EB
Model in PSpice

M2

R7

D3

1
D5

5.0mH

D7

D8

MUR160

IRF840

L3
N

MUR160

.05
R9
10k

V1 = 0
V6 V2 = 10
TD = 0
TR = 0.5u
TF = 0.5u
PW = 9u
PER
houtN
= 20u

1.0KV

0.5KV
0A

lamp_L
L4

0V

3.8mH
C8

R6
304

6.8n

-400mA
lamp_N

Model represents S-S interleaved PCF EB

The model can be again simplified using averaging
technique if just LF phenomena are subject of interest.
Simplification procedure to get averaged-switch model, as in
case of D-S active PFC EB can be adopted. In fact the
included PFC operate with constant switching frequency and
even duty ratio.

>>
-0.5KV
80ms
1

I(R1)

90ms
2

100ms
V(L)- V(N)
Time

110ms
V(+)- V(-)

120ms

8.0

1.0A

6.0

10uA

4.0

2.0

1.0nA
0Hz

50KHz
100KHz
I(R1)
Frequency

0.0
h (-)

Waveforms of supply voltage (red), input current

(green) and of DC bus voltage (blue);
Spectra of input current: THDI=7.9 % (up to h=50)

23

10k

19

R8

MUR160

400mA

15

100n

IRF840

11

35u
D6

C4

V1 = 0
V5 V2 = 10
TD = 10u
TR = 0.5u
TF = 0.5u
PW = 9u
PER = 20u
houtL
C7
33n

M1

D4
3

D2
C5
V4
VOFF = 0
VAMPL = 325 100n
FREQ = 50

R5 .05

+
C6

0.0001
R10

5mH

(IhI1).100 (%) .

L2
L1

0.0001

R1

Simulation results

26

Basic Driver for LEDs

Modeling of LEDs
i
L

v
N

iI

CB

Cr

vL

vB

iL

Lr1 Lr2

LEDs (lamps) can be simply modeled using diode model(s)

of appropriate parameters

Lamp voltage and current, . Line voltage and current, .

DC bus voltage,
vL (V), i L (mA)
v (V), i (mA), vB (V)

Experimental results: Screw/based LED lamp

of about 6 W, 230 V @ 50Hz
350
250
150
50
-50
-150
-250
-350

vB

10

15
Time (ms)

20

25

30

15

20

25

30

vL
iL

60
Inverter current,
i I (mA), i IF (mA)

160
140
120
100
80
60
40
20
0
0

In a case of stable lamp voltage (current) with small ripple

ensured by feeding converter, a resistance can be
employed as substitute

10

Time (ms)

iI

50
40

i IF

30
20
10
0

Equivalent DC bus .
load, REL (k )

10

15
Time (ms)

20

25

30

10

15
Time (ms)

20

25

30

10
8
6
4
2
0

27

Basic Driver for LEDs

Modeling of drivers with LEDs

There is pretty symmetry between LED drivers and EB in modeling:
If the switching converter is of fixed switching frequency and operating with constant
duty ratio, whole the second stage of the converter with the LEDs string can be, using
averaging method, replaced by an equivalent resistance which loads rectifier as in
case of EB. Then following model can be used:
ZS

RF

LF
CB

REL

CF

In a case the driver second stage include controlled switching converter, its averaged
switch model can be utilized, following already described procedure. The same can be
applied for modeling of an active PFC if it is present.

28

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31

Thank you for your attention

QUESTIONS?