Professional Documents
Culture Documents
Chapter 2
Chapter 3
Chapter 4
Chapter 5
iii
Chapter 6
Chapter 7
Chapter 8
Chapter 9
Chapter 10
Parametric Measurements
Discusses using parametric testing to guarantee conformance to electrical
data sheets and presents information on the use of boundary-scan, pattern
sets, and TDL types
Chapter 11
Chapter 12
Chapter 13
Chapter 14
Military ASIC
Summarizes military ASIC documents and the location of military-specific
design information
Appendix A
Glossary
Contains important ASIC words, phrases, and software tools
iv
Notational Conventions
Notational Conventions
This document uses the following conventions.
0011
0012
0013
0014
0005
0005
0005
0006
0001
0003
0006
.field
.field
.field
.even
1, 2
3, 4
6, 3
csr -a /user/ti/simuboard/utilities
The LALK instruction has two parameters. The first parameter, 16-bit
constant, is required. The second parameter, shift, is optional. As this
syntax shows, if you use the optional second parameter, you must
precede it with a comma.
vi
vii
viii
Trademarks
Advantest is a trademark of Advantest Corporation.
ACE, DETECTOR, GOOD, MegaModule, and TI are trademarks of Texas
Instruments Incorporated
Analyzer, Cadence, Design Planner, Gate Ensemble, LeapFrog, QPlace,
SDF, Verilog, Verilog HDL, and Verilog-XL, are trademarks of Cadence
Design Systems, Inc.
DFTAdvisor, FlexTest, FastScan, Mentor Graphics, and QuickSim II are
trademarks of Mentor Graphics Corporation
Behavioral Compiler, DC Expert, DC Professional, DesignPower, dont_touch,
Power Compiler, Primetime, Synopsys, Synopsys VHDL Compiler, Test
Compiler, Test Compiler Plus, VSS, VSS Expert, and VSS Professional are
trademarks of Synopsys, Inc.
Gemini, IKOS, NSIM, Voyager, and Voyager-FS are trademarks of IKOS
Systems, Inc.
HP, HP 700, HP 9000, and HP-UX are trademarks of Hewlett-Packard
Company
IBM is a trademark of International Business Machines Corporation
SPARC, SPARC 20, SPARCstations, and UltraSPARC are trademarks of
SPARC International, Inc., but licensed exclusively to Sun Microsystems, Inc.
Solaris, Sun Sun-5, SunOS, and Sun Workstation are trademarks of Sun
Microsystems, Inc.
Quad Design, and Sunrise are trademarks of Viewlogic Systems,
Incorporated, a subsidiary of Synopsys, Inc.
Vitesse is a trademark of Vitesse Semiconductor Corporation
EMIS is a trademark of Synercom Technology, Inc.
ix
Trademarks
Contents
1-1
xi
Contents
9-1
Contents
xii
Contents
Parametric Measurements
10-1
Overview......................................................................................................................10-2
Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type) ....10-4
Output Voltage Levels (DC_PARA TDL Type) ...........................................................10-10
Three-State High-Impedance Measurements (DC_PARA TDL Type) .......................10-11
Input Current Measurements (DC_PARA TDL Type) ................................................10-12
Quiescent Drain Supply Current (IDDQ TDL Type) ...................................................10-13
11
12
13
14
Military ASIC
14-1
Military-Specific Design Information ............................................................................14-2
Military ASIC Topics Cross-Reference ........................................................................14-3
Contents
xiii
Contents
Glossary
Index
xiv
1
Index-1
Figures
21
22
23
24
25
26
31
51
52
53
54
55
56
57
58
59
510
511
512
513
514
515
516
517
518
519
520
521
xv
Figures
522
61
62
63
64
65
66
67
68
69
610
611
612
613
614
615
71
72
73
81
82
83
84
91
92
93
94
95
96
97
98
99
910
911
912
913
101
Contents
xvi
Figures
102
103
111
112
121
122
123
124
125
126
127
128
129
1210
131
132
133
134
135
136
137
138
139
1310
Contents
xvii
Tables
Table
41
81
82
101
102
103
121
131
141
Page
TDL Pattern Set Requirements Summary ................................................................. 4-5
Example Test-Register TP000 Assignments ............................................................. 8-5
Example Test-Register Test-Selection Codes............................................................ 8-6
Toggle States ........................................................................................................... 10-3
VIL/VIH Test Patterns (Dedicated Control Pins) ...................................................... 10-6
VIH_VIL Test Patterns (Shared Control Pins).......................................................... 10-9
Commonly Used TDL Logic State Characters......................................................... 12-15
Parametric Test Resources ................................................................................... 13-10
Military ASIC Topics Cross-Reference ................................................................... 14-4
xviii
Chapter 1
1-1
By faulting all the nodes in the circuit, the fault simulator produces the test
pattern fault coverage. The fault coverage is the percentage of faults detected
among the total faults tested. The higher the fault coverage, the better the test
pattern separates a faulty circuit from a fault-free circuit. After determining
which faults have not been detected by the current set of test patterns, you
can generate additional test patterns to detect these faults. The higher the
fault coverage of the pattern set (often called fault grade), the greater the
probability of obtaining only fault-free circuits.
The dc parametric testing ensures that a fault-free circuit conforms to the
electrical data sheet. The pattern set for dc parametric testing should provide
one hundred percent toggle of all I/Os.
The IDDQ (quiescent drain supply current) testing ensures a circuit is free from
defects such as resistive bridging or partial gate punch through. Stuck-at-1 or
stuck-at-0 often cannot detect defects of these types.
1-2
Chapter 2
Topic
Page
2-1
2.1
2.2
Test-Time Cost
Test cost, as it relates to time, is a simple calculation. Most commercial
testers cost between $2 million and $3 million. Under normal circumstances,
the tester depreciation, plant, operator, and support personnel costs are
between $.10 and $.20 per test second.
Brute-force test approaches often generate a large number of test patterns.
Because test patterns are run at multiple power supply values and possibly
at multiple temperatures, inefficient pattern sets can severely impact the test
costs of a complex ASIC device.
2-2
Time-to-Market
2.3
Time-to-Market
Surveys indicate that 40 percent of the development cycle time for an ASIC
device is required for test insertion and test pattern generation. This figure is
expected to increase as device complexity increases. The intent of a designfor-testability (DFT) strategy is to achieve high-fault-detection test programs
in reduced time (Figure 21). The obvious cycle-time reductions result from
designed-in testability (elimination of iterative redesigns resulting from poor
design practices), and from automatic test pattern generation (ATPG).
Figure 21.
Fault Grade %
80
60
Without DFT Strategies
40
20
0
Hours
Days
Weeks
Months
2-3
Time-to-Market
Figure 22.
Without DFT
Strategy
Economic
Optimum
1
Cost $
Economic
Optimum
2
With DFT
Strategy
Manufacturing
and Field Cost
Fault Coverage %
Development and
Time-to-Market Cost
Total Cost
A less obvious result of a DFT strategy is the reduction of debug time. You,
as an ASIC designer, must make certain assumptions about system
requirements. Often a new device does not work in the system environment
and requires debugging. If the device is designed for controllability and
observability access, the debugging process is enhanced. Conversely, if
these two features are overlooked, debugging and manufacturing can be
significantly harder to accomplish, if not impossible. Oscilloscopes and
waveform analyzers are not very effective in debugging systems using
complex ASIC devices in a surface-mount environment.
2-4
2.4
D = [1 Y
(1 T)
] 100
where:
D = Defect level in percent
Y = Theoretical functional process yield
T = Fault coverage of the test program used
2-5
Figure 23.
Defect Level %
60%
4
70%
3
80%
2
90%
1
0
90
91
92
93
94
6.7
4.98 4.48 4
3.5
95
96
97
98
99
100
3.41 2.73
2.08 1.38
0.89 0
3.51 3.02
2.52 2.02
1.52 1.01
0.51 0
1.77 1.42
1.06 0.71
0.36 0
0.67 0.45
0.22 0
0.53 0.42
Fault Coverage %
To explore the Williams model briefly, assume that the ASIC vendor has a
silicon and assembly process yield that is 70 percent. If the fault grade of the
test program is also 70 percent, the defect level is projected to be 10.1
percent or 101000 ppm (parts per million) (This is outside the limits of the
chart and was calculated.). At a fault grade of 90 percent, the defect level is
projected to be 3.5 percent, or 35000 ppm.
A study of the model shows that the process yield becomes an insignificant
term when the fault coverage of the test program is very close to 100 percent.
Motorola and Delco2 performed a study in 1980 that supports the Williams
model. Their experimental results are shown in Figure 0-4. A fault coverage
of 99.9 percent was required to obtain defect levels in the range of 100 ppm.
2. Harrison, Holzworth, Motz of Delco and Daniels Thomas, Weimann of Motorola, September
1980.
2-6
Figure 24.
100000
10000
1000
100
10
90
99
99.9
Fault Coverage %
Figure 25 shows the maximum allowable ASIC defect rate to achieve a goal
PCB (printed circuit board) defect rate as a function of the number of ASIC
devices per board assembly. Note that for multiple-device PCB designs, a
goal of 500 ppm requires ASIC defect levels in the range of 100 to 200 ppm.
2-7
Figure 25.
500
400
300
2
200
3
4
5
10
20
100
0
100
200
300
400
500
600
ATPG tool
Fault grader
A testable design that meets the constraints of the ATPG tool
2-8
than that of discovery before assembly onto a PCB. The lowest cost of
ownership is to find defective units before they are shipped from the vendor.
Figure 26.
Cost of Ownership
Customer Site
Discovery Site
System
PCB
Package
Device
1X
10X
100X
1000X
The previous discussions have lead to the conclusion that the lowest cost of
ownership can be obtained by providing the ASIC vendor with an efficient
high-fault-detection set of test vectors. These DFT methodologies provide
lower cost of ownership with the added benefit of reducing the time-to-market.
2-9
2-10
Chapter 3
You should now be aware of the benefits of having a testable circuit and have
a general awareness of testability techniques. This chapter presents a
methodology for developing a testability strategy for your circuits. The
process involves making decisions based upon your application. The
following strategies, listed by section, step you through the process of
testability.
Topic
Page
Selecting a Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Committing to Testability Design Practices . . . . . . . . . . . . . . . . . 33
Establishing a Fault-Grade Requirement . . . . . . . . . . . . . . . . . . . 34
Will IEEE Standard 1149.1 Be a System Requirement? . . . . . . . 35
Selecting a Testability Approach Based on Gate Density . . . . . . 36
Choosing Structured Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Establishing a Diagnostic Pattern Set to Expedite Debug . . . . . 39
Generating High-Fault-Grade Test Patterns . . . . . . . . . . . . . . . . . 310
Simulating Test Patterns and Timing . . . . . . . . . . . . . . . . . . . . . . 311
Converting Test Patterns to TDL . . . . . . . . . . . . . . . . . . . . . . . . . . 312
Planning for Test Pattern/Logic Revision Compatibility . . . . . . . 313
3-1
Selecting a Technology
3.1
Selecting a Technology
When selecting a technology or vendor, make sure there is enough
performance and gate-count margin to allow the insertion of testability. Make
an early recognition that you need a 10 percent ac margin and a 10 percent
to 15 percent gate-count margin. An optimized testability library to support
techniques such as parallel module test (PMT), scan, and IEEE Standard
1149.1-1990, IEEE Standard Test Access Port (TAP) and Boundary-Scan
Architecture (JTAG) can reduce the impact of inserting testability features.
Chapter 7, IEEE Standard 1149.1-1990, describes the standard.
Failure to allow for technology margins puts you in a continual state of
compromise. The result can be a circuit with a low purchase price that has a
high cost of ownership through manufacturing because it is untestable.
3-2
3.2
Review the testability design practices with the design team before
beginning the design.
3-3
3.3
3-4
3.4
3-5
3.5
Designs with more than 10K gates but fewer than 20K gates
Structured techniques should be considered for designs in this density
range. Nonstructured design practices are probably sufficient for highly
combinatorial circuits without memory. Structured approaches should be
considered as complexity is increased by the addition of sequential
circuits, feedback, and memory.
Consider scan for reduced cycle times and high fault grades.
3-6
3.6
Clocked scan
Multiplexed flip-flop scan
Level-sensitive scan design (LSSD)
Clocked level-sensitive scan design
Parallel scan paths
Partial scan
3.6.1
Clocked Scan
A clocked scan flip-flop has separate clock and data inputs for scan and
system-mode operation. It also has separate data outputs for scan and
system-mode operation. The clock-to-scanout propagation delay is
purposely slowed. This reduces the chance of skew in the scan clock
distribution network that could cause timing race conditions in the scan path.
The separate scanout output isolates the loading of the scan-path routing
from the system mode output.
Clocked scan is a suitable choice for partial scan designs. This scan style
uses a separate clock for scan and system-mode operation. This clock
separation means that nonscan flip-flops are not clocked during the scan
operation.
3.6.2
3-7
skew in the clock distribution network to prevent timing race conditions in the
scan path.
Multiplexed scan is not a good choice for partial scan designs. This scan style
uses a common clock for scan and system-mode operation. This clock
sharing means that nonscan flip-flop clock inputs must be gated to disable
them during the scan operation.
3.6.3
3.6.4
3.6.5
3.6.6
Partial Scan
While scan paths can convert sequential circuits into combinatorial circuits for
testing, this procedure adds overhead and degrades performance. The ATPG
tool may be the driving force in making the scan decision. Partial scan could
be a good decision, if you follow good design practices and have an ATPG
tool that can handle partial scan. In these cases, scan elements could be
omitted from portions of the design that cannot tolerate the performance
impact of scan.
3-8
3.7
3-9
3.8
Stage 3:
Generate a dc leakage test. The classic stuck-at fault model is used by
the ATPG tool, but it does not represent some types of CMOS faults. The
dc leakage testing, often referred to as IDDQ testing, is useful in
supplementing stuck-at testing. Implementing IDDQ testing requires a test
mode to turn off all circuits that produce dc current, such as pullup and
pulldown resistors.
3-10
3.9
Inputs and outputs must satisfy the test description language (TDL)
timing restrictions provided by TI.
3-11
3.10
3-12
3.11
3-13
Figure 31.
Yes
Density = Gates
Gates < 10K
No
Yes
Consider
Scan
Recommend
Scan
Minimum time-to-market
3-14
Chapter 4
Topic
Page
Responsibilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TDL Type Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
4-1
Responsibilities
4.1
Responsibilities
You have the responsibility to provide a set of required test patterns to TI.
These test patterns are used to perform dc parametric testing, logic
verification, and propagation delay tests. TI accepts additional usergenerated patterns on a limited basis.
The test patterns for handoff to TI must be described in TDL format. TDL
stands for test description language and is the test pattern format accepted
by TIs internal set of tools. The contents of each TDL set must conform to a
set of test flow constraints. See Test Pattern Generation on page 121 for
information on test pattern generation details.
The designs testability schemes determine which TDL sets are required.
Presently, three testability schemes are supported by TI ASIC:
Scan
TI parallel module test (PMT) for MegaModule testing
Built-in self-test (BIST)
A set of TDL types has been defined by TI ASIC to identify the functions of
each TDL to the set of internal tools. For example, a TDL set written to
facilitate dc parametric and IDDQ tests would be assigned the DC_PARA and
IDDQ TDL types.
4-2
4.2
4.2.1
FUNC
IDDQ
4.2.2
4.2.3
SCAN
TDL used to verify logic integrity. A SCAN TDL set can replace
the requirement for a FUNC TDL set.
SCANCHK
4-3
4.2.4
4.2.5
ANALOG_<name>
PMT
PMTSETUP
PMT_SIM
DIAGNOST
FUNC_AC
GTAPCHK
SCAN_AC
TURNOFF
VIH_VIL
4-4
Required
Optional
Prop Delay
Option
(see Notes: 1)
DC_PARA
FUNC
IDDQ
BIST
BIST_AC
DIAGNOST
N/A
N/A
FUNC_AC
GTAPCHK
SCAN
SCANCHK
SCAN_AC
(see Note
TDL Type
dc Parametric and
Logic Verification
AtSpeed
Notes: 2)
TURNOFF
VIH_VIL
Notes:
1) At least one propagation delay measurement is required per design. The TDL can be used to facilitate a
propagation delay test by the insertion of an ASIC_TEST statement with the PROP keyword into the test vectors.
Propagation delay measurements are not allowed for at-speed TDL types.
2) The maximum scan frequency is the same as for the logic verification constraints. All other at-speed constraints
apply.
4-5
4-6
Chapter 5
This chapter describes various ad hoc techniques that can be used to make
a design testable.
Topic
Page
5-1
5.1
5-2
5.2
Figure 51.
Test Pin
Unused package pins can also be used to control internal nodes that are
difficult to access otherwise. The circuit shown in Figure 51 has been
modified to allow the injection of test signals (ENABLE high) or to operate
normally (ENABLE low). Figure 52 illustrates the reconfigured circuit.
Figure 52.
Test Signal
PAD
ENABLE
PAD
5-3
5.3
Figure 53.
ENABLE
Test Data Out Bus
INA
PAD
Core
Logic
Core
Logic
PAD
Test Data In
5-4
OUTB
5.4
Figure 54.
01
Q
11
QZ
QZ
CLOCK
SELECT
Output
5-5
Figure 55.
Q
QZ
Q
QZ
10
01
11
CLEAR
CLOCK
SELECT
Output
A power-on clear mechanism, which initializes the circuit in the actual system
configuration, is not an adequate test initialization implementation. Although
this function must also be tested, the tester loses many of its utility programs
if initialization is performed only in this manner, and overall testing suffers
dramatically. By adding the special set or reset signal (Figure 55), the circuit
can be directly set into a known state, and the tester is guaranteed to have
the first pulse appear after a known number of cycles. All of the testers utility
programs remain intact.
5-6
5.5
Figure 56.
(b)
S
Y
CLOCK
Y
R
5-7
5.6
Figure 57.
Clock
Gate
Gate Delay
Second
Clock
Gated Clock
Ideal Timing
Slight Delay in
Gate Signal
Output
Ideal Timing
5-8
5.7
Figure 58.
(b)
Oscillator Out
Oscillator
Clock
Signal
Oscillator
Test Clock
Test Select
M
U
X
Clock
Signal
5-9
5.8
Figure 59.
(b)
Divider Out
1-MHz
Clock
1000:1 Divider
1-kHz
Clock
1-MHz
Clock
1000:1 Divider
Test Clock
Test Select
5-10
M
U
X
1-kHz
Clock
5.9
A1
CLR1
QA1
QB1
QC1
QD1
Q0
Q1
Q2
Q3
QA2
QB2
QC2
QD2
Q4
Q5
Q6
2:1 MUX
S
A
B
A2
RESET
CLR2
Dual 4-Bit
Ripple Counter
A1
CLR1
A2
Q7
CLR2
QA1
QB1
QC1
QD1
Q8
Q9
QA
QB
QA2
QB2
QC2
QD2
QC
QD
QE
QF
Dual 4-Bit
Ripple Counter
Test Pin
PAD
5-11
5.10
S
Output
A
DATA IN
Logic
A
PAD
Logic
B
PAD
B
2:1 MUX
S
Output
A
DATA IN
Logic
A
PAD
Logic
B
PAD
B
2:1 MUX
In Figure 513, testability for both logic blocks is enhanced by using both
input and output multiplexing.
5-12
S
Output
PAD
DATA IN
Logic
A
PAD
Logic
B
2:1 MUX
2:1 MUX
Of the three flip-flops shown in Figure 514, only the last flip-flop connects to
a package pin. If a 4:1 multiplexer is added, as shown in Figure 515, each
flip-flop output can be connected individually to the output pin.
Q
D
QZ
CLRZ
Q
D
QZ
CLRZ
PAD
QZ
CLRZ
RESET
CLOCK
A
B
C0
C1
Q
DATA
QZ
CLRZ
RESET
CLOCK
Q
D
QZ
CLRZ
PAD
C2
C3
Q
D
Output
QZ
CLRZ
Hi
Lo
Tie-Off
5-13
5.11
Sequential
Circuit
Sequential
Circuit
Sequential
Circuit
Out
Sequential
Circuit
Out
(b)
In
Sequential
Circuit
Sequential
Circuit
MUX
MUX
MUX
MUX
MUX
TEST IN
5-14
5.12
(b)
Test A
Logic A
In
Logic A
Out
Logic B
In
Out
Logic B
Test B
5-15
5.13
(b)
A
G1
G2
G4
G1+G2+G3
G2
C
G3
G3
TEST
5-16
G1
G4
G1+G2+G3
5.14
Module
2
CONTROL 1
DEGATE
CONTROL 2
Module
3
5-17
5.15
Q
D
QZ
CLRZ
CLK
MCLR
5-18
Q
D
QZ
CLRZ
Q
D
QZ
CLRZ
Q
D
QZ
CLRZ
Q
D
QZ
CLRZ
5.16
CLRZ
CLOCK
TESTDATA
QA
QB
QC
QD
QE
QF
QG
QH
TESTDATA1
TESTDATA2
TESTDATA3
TESTDATA4
TESTDATA5
TESTDATA6
TESTDATA7
TESTDATA8
8-Bit Parallel-Out
Serial Shift Register
5-19
5.17
Module
A
Module
B
Module
C
OUT1
CLK
CKINZ
SERIN
SHLD
A
B
C
D
E
F
G
H
QH
PAD
TESTOUT
QHZ
8-Bit Parallel-Out
Serial Shift-Register
CLK1
5-20
Module
D
PAD
OUT2
Chapter 6
This chapter discusses the benefits and limitations of scan design and
presents several scan design approaches.
Topic
Page
6-1
6.1
6-2
6.2
Figure 61.
D
Q
DATA OUT
SO
SCANOUT
CLOCK
SCANIN DATA
SD
SCAN CLOCK
Interconnecting several clocked scan macros gives the circuit a serial scan
shift capability that reduces the testing of a sequential circuit to the testing of
a combinatorial circuit, as shown in Figure 62. The SO output of one flip-flop
feeds the SD input of the next flip-flop. This is repeated until the scan path is
formed. The TI library offers clocked scan flip-flop macros.
6-3
Figure 62.
DATA IN
SCANIN
Logic
Logic
SO
Logic
DATA
OUT
SD
SD
SD
Logic
SO
SO
SCANOUT
CLOCK
SCAN
CLOCK
6-4
6.3
Figure 63.
/1
D
SD
SCAN ENABLE
1
MUX
DATA OUT
QZ
DATA OUT
CLOCK
Figure 64.
SCANIN
DATA IN
SCANOUT
Logic
SD
D Q
SE
Logic
SD
D Q
SE
Logic
SD
D Q
Logic
DATA OUT
SE
SCAN ENABLE
CLOCK
6-5
There are some disadvantages. Adding logic into the data path limits the
speed at which the circuit can be clocked. The hardware overhead is related
to the number of registers, because each requires a 2:1 multiplexer.
The silicon overhead to implement multiplexed flip-flop scan is in the range of
5 to 15 percent. Up to three additional pins are required to implement this type
of scan. Only the SCAN ENABLE pin must be dedicated; the remainder of the
pins can be shared with primary inputs and outputs.
6-6
6.4
You decide to use a clock signal that is the input to a clock distribution
macro. This clock signal becomes significantly skewed relative to the
clock signal from the clock distribution macros output.
The ATPG tools do not allow gated or internally generated clocks. You
can isolate the gated or internally generated clocks with a SCAN clock
that meets all the scan rules. Typically, this is done by adding a
multiplexer to the clock paths. During normal mode, the multiplexer
selects the gated or internally generated clock. This technique meets
scan design rules but also introduces clock skew.
If two successive scan path flip-flops have significantly skewed scan clocks,
where the first scan flip-flop is clocked before the second scan flip-flop, a
timing race condition may exist. The first scan flip-flop captures the next scan
data bit using the earlier scan clock, and its Q output changes and races to
the second scan flip-flop along with the later scan clock. If the scan data
arrives first, this scan data is clocked into both scan flip-flops. The scan data
appears to jump across the first scan flip-flop directly into the second scan
flip-flop on a single scan clock cycle.
When this type of jump occurs, the ATPG test patterns interpret it as detecting
a stuck-at-fault and reject the circuit. Simulation of the scan shift operation is
the only way to verify that scan clock skew does not cause jumping.
6-7
6.5
Figure 65.
CLOCK
>
SCANIN DATA
SD
TMC
TSC
Q
SQ
DATA OUT
SCANOUT
Interconnecting several clocked LSSD scan flip-flops gives the circuit a serial
shift capability that reduces the testing of a sequential circuit to the testing of
a combinatorial circuit, as shown in Figure 66. The SQ output of one flip-flop
feeds the SD input of the next flip-flop. This is repeated until the scan path is
formed. The TI library offers clocked LSSD scan flip-flop macros.
6-8
Figure 66.
CLOCK
DATA IN
L
O
G
I
C
>
SD
TMC
TSC
SQ
L
O
G
I
C
>
SD
TMC
TSC
SQ
L
O
G
I
C
>
SD
TMC
SQ
L
O
G
I
C
DATA OUT
TSC
SCANIN DATA
SCAN OUT
6-9
6.6
All stored states must be in scan flip-flops. Cross-coupled latches are not
permitted.
All flip-flops in a scan path must have the same common clock. No logicgenerated or asynchronous clocks are permitted.
All resettable scan flip-flops must be resettable only via a master or global
reset. Resettable flip-flops are not required. Initialization can be
accomplished by scanning in the initial state.
Refer to the applicable (TGC2000, TSC4000, etc.) macro library summary for
macros that are available to support flip-flop-based scan designs.
6-10
6.7
Figure 67.
SCANIN
DATA IN
SCANOUT
Logic
SD
Q
D
SE QZ
Logic
SD
D Q
SE QZ
Logic
SD
D Q
Logic
DATA OUT
SE QZ
SCAN ENABLE
CLOCK
6-11
6.8
Figure 68.
SCAN ENABLE
Out
B
C
D1
D Q
SE
SD
D2
D Q
SCANOUT
SE
SD
D3
SCANIN
CLOCK
D Q
SE
SD
Bus contentions can exist if more than one scan register contains a logic
1 during scanin or scanout.
The contention hazard must be removed by the addition of 3-state disabling
circuitry. The disabling circuitry is activated with a scan-enable signal. This is
the same enable signal used to control the multiplexer in the scan flip-flop. An
LSSD or clocked scan design would need a signal generated off a test-mode
pin. Figure 69 shows the circuitry added to eliminate the contention hazard.
6-12
Figure 69.
SCAN ENABLE
Out
B
C
D1
D Q
SE
SD
D2
D Q
Disabling Logic
SCANOUT
SE
SD
D3
SCANIN
D Q
SE
SD
CLOCK
6-13
Test-Isolation Modules
6.9
Test-Isolation Modules
Full scan techniques provide a straightforward approach to ASIC testing for a
high fault grade. For large, register-intensive designs, the full scan technique
results in very long scan paths. Multiple scan path designs reduce the costs
of test vector generation and fault simulation. Parallel testing of the modules
also reduces test time.
6.9.1
ROM
RAM
Serial
Peripheral
Interface
MegaModule
System
Controller
Serial Communications
Interface
Parallel
Scan Blocks
6-14
Test-Isolation Modules
Partition logic to reduce the number of scan macros to fewer than 750 per
logic block. This allows parallel testing of multiple paths rather than serial
testing of one long path. Parallel test time is determined by the longest
path. For this reason, the parallel paths should be of comparable lengths.
In Figure 611, Figure 612, and Figure 613, all the SCANIN and
SCANOUT data pins can be multiplexed with other operational functions.
6-15
Test-Isolation Modules
SCANIN1
SCANOUT1
Block 1
SCANIN2
SCANOUT2
Block 2
SCANIN3
SCANOUT3
Block 3
SCAN CLOCK
6-16
Test-Isolation Modules
SCANIN1
SCANOUT1
Block 1
SCANIN2
SCANOUT2
Block 2
SCANIN3
SCANOUT3
Block 3
SCAN ENABLE
6-17
Test-Isolation Modules
SCANIN1
SCANOUT1
Block 1
SCANIN2
SCANOUT2
Block 2
SCANIN3
SCANOUT3
Block 3
2
MASTER SCAN CLOCK
SLAVE SCAN CLOCK
6.9.2
6-18
Test-Isolation Modules
the tester then applies the input stimuli and the device under test returns to
the normal mode of operation. Afterward, the response of the device is
captured and shifted out for comparison. Normally, the scan result is shifting
out while the new scan data is shifting in.
As stated earlier, the longest scan path determines the length of the scan test
vector. Because all the paths are being tested in parallel, it is necessary to
add elements for the shorter paths so all vectors are equal in length. Figure
614 is an example of the elements added to the short scan vectors. These
elements are dont cares on the inputs and masks on the outputs.
SCANOUT Vector
SCAN
PATH
1
HHLLHLLHLLLHLLLHLH010101101101101101
SCAN
PATH
2
YYYLHLHLHLLHLLHLLH010110110111101MMM
SCAN
PATH
3
YYYYYYYHLHHLLHLLHL11011101110MMMMMMM
First Bit In
Logic One Input = H
Logic Zero Input = L
Dont Care Input = Y
6-19
6.10
A scan path is often used around these circuit structures to ensure that proper
data and control signals are being supplied by surrounding logic. A scan ring
is formed by placing a scannable latch or register on all signals entering or
leaving the circuit structure (Figure 615).
DATA IN
DATA IN
SCANIN
Scan
Element
ADDRESS
RAM
SCAN_ENABLE
MUX
S
DATA OUT
ADDRESS
Scan
Element
I
I
DATA OUT
SCANOUT
Scan
Element
R/W
R/W
Scan
Element
ENABLE
ENABLE
Surrounding
Logic In
6-20
Scan
Element
Surrounding
Logic Out
Chapter 7
This chapter explores the IEEE Standard 1149.1-1990 and the applications
to testing printed circuit boards in a surface-mount environment.
Topic
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
7-1
Overview
7.1
Overview
The IEEE Standard 1149.1-1990, IEEE Standard Test Access Port and
Boundary-Scan Architecture (JTAG) foreword states, This standard defines
a test access port and boundary-scan architecture for digital integrated
circuits and for the digital portions of mixed analog/digital integrated circuits.
The facilities defined by the standard seek to provide a solution to the problem
of testing assembled printed circuit boards and other products based on
highly complex digital integrated circuits and high-density surface-mount
assembly techniques. They also provide a means of accessing and
controlling design-for-testability features built into the digital integrated
circuits themselves. Such features might, for example, include internal scan
paths and self-test functions as well as other features intended to support
service applications in the assembled product.
The IEEE Standard 1149.1 is usually applied by system designers. For this
reason, system designers have a greater role in defining the specifications for
ASICs. To ensure that the ASICs work properly with other IEEE Standard
1149.1 test components, you as the ASIC designer must become familiar with
this standard.
7-2
Boundary-Scan Architecture
7.2
Boundary-Scan Architecture
Figure 71 shows the boundary-scan architecture specified by IEEE
Standard1149.1. The boundary-scan architecture uses the following
hardware components:
Figure 71.
Boundary-Scan Architecture
ASIC Outputs
Core Logic
Register
ASIC Inputs
Boundary
Scan
UTDR
IDR
VCC
BR
TDI
TMS
TCK
TRSTZ
TAP
8-Bit IR
TDO
7-3
Boundary-Scan Architecture
7.2.1
7.2.2
7.2.3
7.2.4
7.2.5
7.2.6
7-4
Boundary-Scan Architecture
7.2.7
Boundary-Scan Macro
The boundary-scan macros are placed around the periphery of the die next
to the I/O structures. The general-purpose boundary-scan macro has the
capability to capture, shift, and update.
Figure 72 and Figure 73 depict the boundary-scan circuitry.
Figure 72.
MODE
G1
SIGNAL IN
1
1
SHIFT/LOAD
SIGNAL OUT
G1
1
1
1D
C1
SCANIN
CLOCK A
1D
C1
CLOCK B
7-5
Boundary-Scan Architecture
Figure 73.
Boundary-Scannable PCB
Boundary-Scan Cell
Serial
DATA IN
Serial
DATA OUT
Serial Test
Interconnect
7-6
System
Interconnect
Chapter 8
This chapter introduces the generic test access port (GTAP), which is the
Texas Instruments ASIC test controller. A dedicated implementation example
is shown in Part 2 of this book, the Generic Test Access Port Application
Report.
Topic
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Test Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Test RegisterBit Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Communication Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
8-1
Overview
8.1
Overview
The generic test access port (GTAP) is the TI ASIC test controller. From the
device pins, the GTAP can be instructed to enable or disable any combination
of the design-for-testability features. Test features are controlled by the GTAP
unless another controller is present.
The GTAP is designed to consolidate all previous ad hoc ASIC test methods
into a single unified test methodology. It is general-purpose, compatible with
a wide range of tests, and expandable to accommodate future test needs,
hence the name generic. The GTAP is divided into two functions. They are
the test register and the GTAP controller. The GTAP block diagram is shown
in Figure 81.
The GTAP implementation requires one dedicated package pin, four smart
control pins, and one smart output pin. Smart pins are pins that have a test
function in the test mode and a user-defined function in the normal operating
mode.
The TEST input to the GTAP controller must be dedicated to the test mode
operation. The remaining GTAP controller inputs (SCAN, MCLK, and SCLK)
are test-access protocol pins and can be implemented as smart pins. The
SCANIN input to the GTAP test register is referred to as the test instruction
pin and can be implemented as a smart pin. The SCANOUT output from the
GTAP test register can also be implemented as a smart pin.
Figure 81.
TEST
SCAN
MCLK
SCLK
GTAP
Controller
(TP012 or
TP0B2)
TEST1
TEST2
GTT
Test Register
(TP000s or
TP0B0s)
GST
SCANOUT
SCANIN
Enable Test
Function 1
8-2
Enable Test
Function 2
...
Enable Test
Function N
Test Register
8.2
Test Register
The test register is an n-bit serial shift register, each bit corresponding to a
specific test feature. Each ASIC test is selected by an n-bit code. Thus, the
test register can also be interpreted as a test instruction register. It is loaded
by shifting in n bits. Its serial nature economizes on ASIC resources (gates
and interconnect).
The test register is composed of TI TP000 (or TP0B0) macros (shown in
Figure 82) daisy-chained together. The TP0B0 is the BiCMOS version of the
TP000. The TP0B0 can substitute for the TP000 in the following descriptive
sections.
Figure 82.
MSEL
Master
SCANIN
GTT
Slave
D
SCANOUT
GST
8-3
Test Register
Figure 83.
GTT
SCANIN
PAD
SCANOUT
TP000
GTAP_SCAN_IN
TP000
MSEL1
MSEL2
TEST1
8-4
TP000
TP000
TP000
MSEL3
MSEL4
MSELn
TEST2
PAD
1
GTAP_SCAN_OUT
1
2:1 MUX
NORMAL
OUTPUT DATA
8.3
Type
Function
PWRDN
TEST1
VIH_VIL
TEST1
SRAM_OFF
TEST1
VIH_VIL CLK
SELECT
TEST2
HI Z
TEST2
PMT_I/O
TEST2
MSELA
TEST2
Enables MegaModule #1
MSELN
TEST2
Enables BIST #1
MSELT
TEST2
Expansion
8-5
Table 82 lists the test register codes for selecting an ASIC test. The test
register order is arbitrary.
TEST2
VIH_VIL
SRAM
CLK
PWRDN VIH/VIL OFF SELECT HI Z PMT_I/O MSELA MSELN MSELT
ASIC Test
PWRDN STATE
VIH/VIL_CLK_A
VIH/VIL_CLK_B
IIH/IIL/IOZ
CURRENT
PU/PD
CURRENT
VOL/VOH
PMT TEST
ENABLE
BIST TEST
ENABLE
EXPANSION
8-6
Controller
8.4
Controller
The GTAP controller is the interface between the external device pins and the
test register. It also controls test function sequencing via a state machine.
Although the test register selects the test to be performed, the GTAP
controller enables the selected test.
The controller consists of five device pins: TEST, SCAN, MCLK, SCLK, and
SCANIN. Only TEST is dedicated; the rest can have normal input functions
but assume GTAP controller input functions when TEST is high.
TEST
SCAN
Shared test pin option. While TEST is low, this pin behaves as a
normal input pin. While TEST is high, this pin behaves as a GTAP
controller input pin, and low-to-high transitions change the
controller state.
MCLK
Shared test pin option. While TEST is low, this pin behaves as a
normal input pin. While TEST is high, this pin behaves as a GTAP
controller input pin; a low level holds each TP000 master latch,
and a high level passes data through each TP000 master latch.
SCLK
Shared test pin option. While TEST is low, this pin behaves as a
normal input pin. While TEST is high, this pin behaves as a GTAP
controller input pin; a low level holds each TP000 slave latch, and
a high level passes data through each TP000 slave latch.
8-7
Communication Protocol
8.5
Communication Protocol
As shown in Figure 84, the device enters test mode when you set the
dedicated TEST pin high. The controller is in TEST1 state, as shown in Figure
84. The controller can be cycled through the remaining states, WRITE,
RESTORE1, TEST2, and RESTORE2, by toggling SCAN low-to-high. At any
time, returning TEST pin low exits the test mode.
Upon entering test mode (TEST high), any smart-controller I/O signals
(excluding TEST) must be internally latched. Thus, the core logic continues
to see the last normal pin values. This isolates the core logic from the
controller signals. These signals remain latched until TEST returns low.
The test port operates in two distinct testing levels, TEST1 and TEST2. These
two levels serve to better control the testing environment.
TEST1
TEST2
WRITE
Permits writing to the test register. Only the GTAP I/O pins
should be active. All remaining device pins remain in
normal mode. Because the shared controller I/O pins were
internally latched on entering test mode, loading the test
register does not disturb the device state if the normal
values are reapplied during the RESTORE1 state. The
scanout data from the test register are selected for the
output buffer.
RESTORE1
RESTORE2
8-8
Communication Protocol
Figure 84.
TEST
1
TEST1
TEST
1
N
L>H
SCAN
Y
WRITE
0
TEST
1
N
L>H
SCAN
Y
RESTORE1
0
TEST
1
SCAN
L>H
Y
TEST2
0
TEST
1
SCAN
L>H
Y
RESTORE2
0
TEST
1
SCAN
L>H
Y
8-9
Communication Protocol
8-10
Chapter 9
Topic
Page
9-1
9.1
9-2
Figure 91.
TEST
SCAN
MCLK
SCLK
TWE
GTAP
Controller
(TP012 or
TP0B2))
Test Register
(TP000s or TP0B0s)
SCANIN
MegaModule
MegaModule
SCANOUT
MegaModule
TEST_INPUT Bus
TEST_OUTPUT Bus
9-3
9.2
Figure 92.
2:1 MUX
S
NORM_IN
TEST_INPUT
9-4
A
B
IN
OUT
NORM_OUT
TEST_OUT
9.3
Figure 93.
A
B
2:1 MUX
S
Core Logic
PAD
B
Input
Buffer
PAD
Output
Buffer
2:1 MUX
S
TEST_INPUT
A
B
MegaModule
TEST_OUTPUT
9-5
9.4
9-6
9.5
9-7
Figure 94.
PMT_IO
A
B
2:1 MUX
S
Core Logic
PAD
A
B
Input
Buffer
2:1 MUX
S
TEST_INPUT
BUS
A
B
A
B
Output
Buffer
MSEL1
MegaModule 1
2:1 MUX
S
PAD
TEST_OUTPUT
BUS
MSEL2
MegaModule 2
Bus Holder
9-8
A dedicated signal pin is required to initiate the test mode of the operation
(TEST signal on the TP012 or TP0B2 GTAP).
The TEST pin and the four GTAP controller pins (SCAN, SCANIN, MCLK,
and SCLK) are not available for PMT data signals.
The IOG12, SW010, and SW012 buffers cannot be used for PMT data
signals.
VREF pins and bias generator pins cannot be used for PMT data signals.
9.6
9.6.1
9-9
Figure 95.
SW010
PAD
S
AC810
PAD
IOG12
AIN
D7
A
B
PAD
PAD
PAD
S
A
B
PAD
Y
S
S
A
B
PAD
D0
Y
A
B
CLRZ
S
PAD
A
B
CONVZ
SLEEP
A
B
PAD
A
B
Normal_Z
PMT_IO
9-10
A
B
Figure 96.
AC811/812
S
A
B
PAD
TESTCLRZ
TEST
S
A
B
PAD
PAD
IOG12
AIN
A
B
SW010
D7
PAD
PAD
PAD
PAD
TDI7
S
A
B
D0
PAD
TDI0
S
PAD
A
B
Normal_Z
PMT_IO
A
B
9-11
9.6.2
9-12
Figure 97.
AC810
S
PAD
SW010
PAD
MSEL1
A
B
A Y
B
AIN D7
IOG12
PAD
S
A
B
PAD
A
B
PAD
PAD
A
B
S
A Y
CLRZ
D0
SLEEP
CONVZ
AC810
PAD
Bus
Hold-
MSEL2
PAD
A
B
PAD
Bus
Holder
AIN D7
S
A
B
S
PAD
A
B
CLRZ
Bus
Holder
D0
S
A Y
S
A
B
CONVZ
SLEEP
PAD
B
Normal_Z
A
B
9-13
Figure 98.
AC811/812
PAD
TEST
A Y
B
S
PAD
TESTCLRZ
S
PAD
IOG12
SW010
IOG1
A
B
MSEL1
AIN
PAD
PAD
S
A Y
B
D7
TDI7
S
A Y
B
D0
PAD
TDI0
AC811/812
Bus
Hold-
TEST
S
A
B
PAD
MSEL2
A Y
B
PAD
AIN
IOG12
SW010
D7
PAD
TDI7
S
PAD
A Y
B
D0
TDI0
Normal
A
B
PMT_IO
9-14
Bus
Holder
TESTCLRZ
PAD
PAD
9.6.3
9-15
Figure 99.
DA811
S
IOG12
AOUT
PAD
A
PAD
A
B
A
B
PAD
TDO7
Y
Y
PAD
PAD
D7
TDO0
S
A
B
PAD
D0
Normal_Z
A
B
PMT_IO
9.6.4
A
B
9-16
A
B
CLRZ
AOUT
IOG12 PAD
S
PAD
AY
B
SLEEPZ
MSEL1
AY
B
S
PAD
A
B
PAD
TDO7
A Y
B
TDO0
S
A Y
B
PAD
D7
S
A
B
PAD
D0
DA810
S
AY
B
CLRZ
AOUT
IOG12 PAD
S
A
B
SLEEPZ
MSEL2
Bus
Holder
S
PAD
AY
B
TDO7
Bus
Holder
S
AY
B
D7
TDO0
S
AY
B
PMT_IO
D0
A
B
9-17
DA811
S
A Y
B
IOG12
AOUT
PAD
MSEL1
S
S
A Y
B
PAD
D7
S
A
B
PAD
D0
A Y
B
TDO0
A Y
B
PAD
IOG12
PAD
MSEL2
D7
TDO7
Bus
Holder
Bus
Holder
S
Y
D0
TDO0
PMT_IO
9.6.5
S
A Y
AOUT
A
B
PAD
DA811
S
PAD
A
B
TDO7
A
B
9-18
DA811
S
A Y
B
IOG12
AOUT
PAD
MSEL1
S
S
PAD
A Y
B
D7
S
PAD
A
B
A Y
B
TDO0
A Y
B
PAD
IOG12
PAD
MSEL2
D7
TDO7
Bus
Holder
Bus
Holder
PMT_IO
S
A Y
AOUT
A
B
PAD
DA811
S
PAD
D0
A
B
TDO7
D0
TDO0
A
B
9-19
9.6.6
DA811
S
A Y
B
IOG12
AOUT
PAD
MSEL1
S
S
A Y
B
PAD
D7
S
A
B
PAD
D0
A Y
B
TDO0
A Y
B
9-20
PAD
IOG12
MSEL2
D7
TDO7
Bus
Holder
Bus
Holder
PMT_IO
S
A Y
AOUT
A
B
PAD
DA811
S
PAD
A
B
TDO7
D0
TDO0
A
B
PAD
In-System Use
9.7
In-System Use
The multiplexed PMT implementation passes all MegaModule test signals
through I/O buffers. At-speed operation of these MegaModules through direct
access is limited only by the MegaModules capabilities and the performance
of the hookup. For this reason, multiplexed PMT ports can be appropriate for
in-system functions such as preload or status checks.
9-21
In-System Use
9-22
Chapter 10
Parametric Measurements
Topic
Page
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Input Threshold Voltage Levels Using a Clocked NAND Tree
(VIH_VIL TDL Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Output Voltage Levels (DC_PARA TDL Type) . . . . . . . . . . . . . . . 1010
Three-State High-Impedance Measurements
(DC_PARA TDL Type) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1011
Input Current Measurements (DC_PARA TDL Type) . . . . . . . . . 1012
Quiescent Drain Supply Current (IDDQ TDL Type) . . . . . . . . . . 1013
10-1
Overview
10.1
Overview
Parametric testing ensures conformance to the electrical data sheet. It
requires functional test patterns to be developed for parametric testing.
Parametric test patterns must be simulated to check for accuracy and for
circuit hazards such as bus contention. If the circuit has IEEE Standard
1149.1 boundary-scan architecture, the boundary-scan feature should be
used to facilitate input threshold, input leakage current, and output voltage
level measurements.
Most parametric testing pattern sets are assigned the DC_PARA TDL type.
The DC_PARA pattern set should provide 100 percent toggle of all I/Os. This
means that it drives all outputs to a logic low and a logic high. Bidirectional
and 3-state outputs are driven to the high-impedance state. It also drives all
inputs to a logic low and a logic high.
Parametric testing is completed with the dc current leakage pattern set that
is assigned the DC_PARA TDL type and the optional input threshold voltage
pattern set that is assigned the VIH_VIL TDL type.
The table below gives the required TDL states for the various signal types.
10-2
Overview
{L H}
{L H | L T}
{L H | F H}
{C | H}
{C | L}
{0 1N1}
{0 1 Z}
{0 1 Z | 0 1 P}
{0 1 Z | 0 1 N}
{0 Z}
{0 Z | 0 P}
{01 | 0P}
{0 1 L H}
{ 0 1 L H | 0 1 L T}
{0 1 L H | 0 1 F H}
{0 L H}
{0 L H | 0 L T}
Bidi (BTL/CTL/GTL)
{0 L H}
{0 1 H L | N1HL}
Parametric Measurements
10-3
Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type)
10.2 Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL
TDL Type)
VIH_VIL TDLs are optional.
Circuits that implement boundary scan can be used to measure VIH and VIL.
The SAMPLE/PRELOAD and EXTEST instructions can be used to capture
the input logic level. The capture is scanned out for comparison to expected
values. Three test patterns are required. They are a safe circuit initialization
pattern, an all-inputs-at-VIL pattern (inputs include bidirectionals), and an allinputs-at-VIH pattern. For more information, see Chapter 13, IEEE Standard
1149.1-Based dc Parametric Testing.
Circuits that are not IEEE Standard 1149.1-compliant need threshold circuitry
to be added. Figure 101 shows the recommended circuitry commonly
referred to as a clocked NAND tree. This approach requires the addition of a
2-input NAND gate to every input pin as well as CLK and VIH_VIL OUT pins.
The NAND tree provides a purely combinatorial path from all inputs to a
single VIH_VIL OUT through a flip-flop. Do not use a bidirectional buffer for
the VIH_VIL OUT. The first NAND gate in the tree has one input connected
to the high terminal of a tie-off cell.
The flip-flop at the end of the NAND tree serves to break up a positive
feedback loop between an input buffer and the NAND tree output. All the input
buffers are driven to VIHmin and VILmax during VIH/VIL testing of the silicon.
When the NAND tree output switches, it causes some power bus noise and
some input threshold voltage shifting. Sometimes this threshold shifting is
sufficient to cause an input buffer to output the opposite state. The input buffer
may cause the NAND tree to switch again, completing the positive feedback
loop. The positivw feedback loop can also exist between asynchronous inputs
and outputs. for this reason, TI recommends that you exclude clocks, resets,
presets, and other asynchronous inputs from the NAND-tree circuitry.
10-4
Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type)
Lo
IN1
To Functional Logic
IN2
To Functional Logic
IN3
To Functional Logic
IN4
To Functional Logic
INM-1
To Functional Logic
INM
To Functional Logic
DTN12
D
Q
CLK
To Functional Logic
(Dedicated)
PAD
(Dedicated)
VIH_VIL_TEST_OUT
Parametric Measurements
10-5
Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type)
The test patterns are specific. The first pattern consists of VIH threshold
voltages on all inputs. The threshold voltages are then applied in accordance
with Table 102. A circuit containing M number of input pins needs 2(M+1)
test patterns to test both VIH and VIL thresholds.
VIH_VIL OUT
CLK
IN1
IN2
...
INM-1
INM
M=EVEN
M=ODD
...
...
...
...
...
...
...
...
...
On designs that have a bidirectional bus, running the normal NAND tree
patterns may cause bus conflict conditions. This problem can be resolved by
placing the TTL or CMOS bidirectional drivers in the high-impedance mode
with a HI-Z signal. For ECL bidirectional pins, the Hi-Z signal puts the output
driver in the cutoff mode. See Figure 102 for an example.
For designs that do not have extra pins available for CLK and VIH_VIL OUT,
these signals can be multiplexed with other signal pins. See Figure 103 for
an example. The test patterns for the example in Figure 103 must be
10-6
Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type)
modified and are shown in Table 103. Test pattern generation is simplified if
CLK1 is placed on the input whose NAND gate is connected to the tie-off cell.
The placement of CLK2 is arbitrary.
Input Types
PAD
To Functional Logic
PAD
To Functional Logic
VREF
PAD
To Functional Logic
PAD
To NAND Tree
Parametric Measurements
10-7
Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type)
To Functional Logic
MU111
S
A
B
IN2
To Functional Logic
IN3
To Functional Logic
IN4
To Functional Logic
To Functional Logic
INM-1
MU111
S
INM
(Shared CLK2)
VIL_VIH Clock
Select (GTAP)
VIL_VIH
Enable (GTAP)
From Functional
Logic
From Functional
Logic
10-8
A
B
To Functional Logic
Y
DTN12
MU111
D
Q
S
A
B
Y
MU111
S
A
B
Shared
PAD VIH_VIL_Test_OUT
Input Threshold Voltage Levels Using a Clocked NAND Tree (VIH_VIL TDL Type)
VIH_VIL OUT
CLK1
IN1
IN2
IN3
...
INM-1
CLK2
INM
M=EVEN
M=ODD
...
...
...
...
...
...
...
...
...
Parametric Measurements
10-9
10.3
10-10
10.4
Parametric Measurements
10-11
10.5
10-12
10.6
Some macros, such as ECL I/O buffers, cannot disable their dc throughcurrent, but are isolated by a power pin independent of the core logics
power pin. This allows IDDQ measurements to be made on the core logic.
Floating internal nodes, floating I/O inputs, and internal bus contention
cause dc through-current and must be avoided.
Parametric Measurements
10-13
10-14
Chapter 11
Topic
Page
11-1
11.1
11-2
Electrical Rules
Checking
Simulation
Test Generation
Fault Simulation
Layout
Fabrication
It is possible that, during the ATPG phase, the need for additional test points
to achieve the target percentage becomes apparent. (See Chapter , Ad Hoc
Testability Practices, and Chapter 6, Structured Testability Practices, for
approaches to designing for testability.) If this is the case, the netlist must be
modified and resimulated. It is important, in terms of efficiency and
effectiveness, that the ATPG software be integrated into the design
environment. ATPG tools require the circuit description at gate level, all circuit
timing information, any pregenerated functional test patterns and any userspecified parameters. The software uses this information to follow a flow
similar to that shown in Figure 112.
11-3
Fault Simulation
Eliminate Additionally
Detected Faults from
Consideration
In this flow, the first step is to check the circuit for adherence to any designfor-testability rules imposed by the ATPG tool. Fault simulation is then
performed with the optional user-generated functional patterns. All faults
detected by these patterns are tagged and eliminated from the ATPG
process. Any remaining undetected faults are passed to the ATPG algorithm
where tests are generated for these faults.
Fault simulation is rerun to check the effects of generating the input patterns
necessary to check the faults under consideration, and to identify any
previously undetected faults that may have been detected by this pattern.
Iteration of this process continues until the desired fault coverage is achieved.
Fault simulation, as an intermediate step, checks the targeted fault as well as
all other undetected faults, thus reducing the number of ATPG iterations.
11-4
Path Sensitization
11.2
Path Sensitization
Test pattern generation programs use a variety of methods to achieve
essentially the same test generation capability. The definition of a good test
for a fault is an input combination that produces an incorrect output when the
fault under consideration is present in the circuit. Thus, the presence of the
fault can be observed at the outputs. Path sensitization is one such method
of generating a test for a fault. The general procedure is:
1) Select a fault (such as node stuck-at-one).
2) Assign the faulty wire a value opposite to the fault condition (such as ode
stuck-at-zero). This allows sensitization for the expected signal.
3) Choose a path from the fault to a circuit output.
4) Sensitize this path by assigning logic values to gate inputs along the path
such that the signal is passed to the circuit output.
5) Execute the test to detect the signal by determining the network inputs
that produce the desired values on gate inputs along the sensitized path.
Some variations of this path sensitization method are used in commercial
ATPG programs. All are effective methods for generating tests for faults in
most combinatorial circuitry (without reconvergent fanout). However, few
tools are effective for ATPG of sequential circuits. This has led to the
development of a set of design rules to simplify test generation in sequential
circuits. Level-sensitive scan design (LSSD) is one such design methodology
that imposes design restrictions that allow the circuit to be forced into a test
mode in which the ATPG methods above can be used to generate tests for
faults.
Another approach is random vector generation. This method has
straightforward applications for some combinatorial circuitry but has not been
extended effectively to sequential circuitry. Certain combinatorial circuits lend
themselves nicely to this approach while others do not.
Current ATPG tools are unable to achieve good results on complex designs
without DFT features. Most of the commercial, general-purpose ATPG tools
use scan techniques. Scan techniques fall into two broad categories: full scan
and partial scan.
11-5
Full-Scan Designs
11.3
Full-Scan Designs
By far the most popular ATPG methodology uses a full-scan approach. This
calls for rigid design rules to be followed that allow the circuit to be placed in
a test mode in which all logic storage elements are connected as shift
registers, breaking up the combinatorial circuitry. When this method is used,
the circuit is placed in the test mode and a test pattern is shifted in, thereby
defining all internal storage states. The circuit is then taken out of the test
mode and operated for a known number of system clock cycles. The circuit is
again placed in the test mode and the internal storage states are shifted out
for comparison to an ATPG-generated signature. It is argued that full-scan
designs are both easily tested and more likely to be correct the first time.
Some ATPG tools work only on full-scan designs.
11-6
Partial-Scan Designs
11.4
Partial-Scan Designs
Partial scan is a technique where only some of the logic storage elements
(those in the most difficult to test areas) are made scannable. This approach
has fewer design restrictions. Some ATPG tools support partial scan and they
can also be used on full-scan designs. Partial-scan ATPG tools can help you
determine where scan elements are required. Because such modifications
are not acceptable in every design, it is essential that these tools are used by
you, the designer, and not by the ASIC vendor.
11-7
11.5
11-8
11.6
No combinatorial-feedback loops
No asynchronous timing
11-9
Summary
11.7
Summary
When embarking on an ATPG methodology, you must consider many aspects
of the total design environment, such as:
11-10
Chapter 12
This chapter discusses test pattern generation. Test patterns must operate on
automated test equipment (ATE).
Topic
Page
12-1
Introduction to Testing
12.1
Introduction to Testing
A logic truth table is used to verify the logic behavior of an integrated circuit
and thereby check for the presence of manufacturing defects. This truth table
is referred to as a test pattern, and a test vector is defined as a line in the truth
table.
Logic simulators are used to explore the Boolean and timing responses of a
circuit by applying a user-defined set of input stimuli. If you have done a good
job, the set of input stimuli can be used to control and observe the behavior
of all nodes in the circuit.
Automated test equipment (ATE) used to screen integrated circuits does not
have the same features as the logic simulator. Access to internal nodes is not
possible, and propagation delays need to be measured from inputs to outputs
of the device. Testing a chip is performed by applying binary patterns (input
vectors) to stimulate the logic inputs and then comparing the output response
to the values predicted by simulation.
In general, the phase relationship and sequence of input stimuli applied to an
integrated circuit to test the functionality and performance of the device are
somewhat different than the simulation patterns used to verify the logic
design. These differences are due mostly to the inherent characteristics of
testing equipment used to evaluate logic devices. For this reason, test
patterns must be simulated using conditions consistent with ATE capabilities.
ATEs are synchronous systems. Described simply, an ATE operates in a
periodic fashion. Input signals change at designated points within the test
period. Output signals are strobed at designated points in the period. Figure
0-1 is a diagram of the phase relationship of input and output data with
respect to the test period for a sample test pattern. The TI test utilities
assume a data input, a clock, then a strobe for the test signal sequence. All
test period timing is referenced to the beginning of the period (to).
12-2
Introduction to Testing
to
to
to
to
to
Data
Input
Primary
Clock
Output
Strobe
Test Period
Each vector applied to the device under test (DUT) is stored in the ATE
pattern memory. If the number of test vectors exceeds the ATE pattern
memory capacity, two or more memory reloads from disk would be required,
greatly increasing the test time. Minimizing the number of test vectors is
desirable not only to reduce the test run time, but also to reduce simulation
and fault grading times.
The number of primary clocks and strobe times that can be applied to the
DUT is a function of the number of timing generators available in the ATE. By
programming these timing generators, you can select multiple clocks or
strobe timing relationships with respect to the test period.
Figure 122 shows a simplified block diagram of an ATE.
12-3
Introduction to Testing
CC
OO
Output
LLIIIIIUU
KKNNNNNTT Pattern
Data
121234512
SETR P := CCHHLLHAA;
SETR P := CCLHLHL11;
Strobe
SETR P := CCHLHHH1Z; Enable
SETR P := CCHHLLH10; Timing
Test Patterns
(TDL Data)
CLK1
CLK2
IN1
IN3
IN4
IN2
OUT2
OUT1
IN5
Logic
Control
DUT
Test Data
Compared Pass
-1
The minimum duration of the test period varies from system to system and
determines the frequency range at which a device can be tested. Typically,
however, there are other constraints that require the testing frequency to be
much lower than the capability of the tester.
A major factor influencing testing is called period slip. In some cases, the
exact time in which the output signal becomes valid is not critical to the
system operation. It is very important to the ATE. Testing systems compare
the output states to the expected responses on a period-by-period basis by
activating strobe signals (Figure 121 and Figure 122) which, in turn,
enable a set of comparators connected to the output channels. If output
responses slip from one test period to the next, the device fails even though
it may be fully functional at the system level (see Figure 123). In order to
minimize this problem, functionality of devices is verified at a relatively low
12-4
Introduction to Testing
Output
Signal at
Max Delay
Fail
Strobe
Test Period N
Properly constructed test patterns should contain input signals and expected
output responses as observed during simulation. For any circuit containing
sequential logic, test patterns consist of two parts:
1) An initialization step to set external and internal nodes, including memory
elements, from an unknown state to a known state by exercising the
device clock, data, reset, or scan pins.
2) The actual test vectors used to stimulate input and output pins.
If a device contains internal 3-state buses, you must arrange the enable logic
so that the buses are always driven (not left in the high-impedance state). A
bus holder cell prevents bus floating by maintaining the last state on the bus
in a way similar to a latch. Furthermore, internal bus contention must be
avoided to ensure the device initialization is not upset by noise resulting from
the contention.
12-5
12.2
12-6
Minimum Delay
Maximum Delay
12-7
Active State
Test Period
to
Rest State
Test Period
to
(HOLD0) (HOLD1)
Delay
Width
(10 ns)
(11.5 ns)
Return-to-Zero
Active State
Test Period
to
Rest State
Test Period
(HOLD1) (HOLD0)
Delay
Width
(10 ns)
(11.5 ns)
Return-to-One
Pattern 010 defines a return-to-zero pulse. Pattern 101 defines a return-toone pulse. HOLD0 is the time the signal is held low and HOLD1 is the time
the signal is held high. Figure 126 depicts the minimum clock width.
12-8
to
Test Period
to
Test Period
Minimum
Clock
Pulse Width
Test Period
to
Test Period
to
Minimum
Clock
Pulse Width
12-9
to
Test Period
Strobe
Window
Max Output Delay
Output
Strobe Offset
Strobe
12-10
From Output
under Test
Test Point
50 W
C = 45 pF for V-Series
= 75 pF for T3320/T3340
Termination
Voltage
At-Speed Testing
The capabilities for each tester are specified in the design manual for the gate
array family.
Pin-to-Pin Testing
Critical timing can be verified by making pin-to-pin propagation delay
measurements.
Keywords can be inserted into the TDL ASIC_TEST statement to define a test
to be included in the test program. Propagation delay measurements have
the following capabilities:
Delay from one package pin to another (input-to-output or output-tooutput). Pass or fail using max values
Delay from a clock edge to an output. Pass or fail using max values
12-11
Guard-banding the limits are automatically done at test to account for tester
accuracy.
12-12
TDL Overview
12.3
TDL Overview
All test patterns must be cycle-based with synchronous clocks.
Synchronous clocks means that all clock periods are multiples of the cycle
time. Example 0-1 shows three common TDL statements.
4.3;
= TsC4000,
= Ardee,
= f123456,
= tdl0,
= FUNC, iddq,
= 1.00,
= 9/27/96;
12-13
TDL Overview
12-14
TDL Overview
t0
Offset = 20 ns
IN[1]
t0
L
Offset = 35 ns
C
CLK
Pulse Width = 25 ns
0
OUT[1]
OUT[1]
STROBE
Strobe Offset = 190 ns
Direction
Input
Drive low
Input
Drive high
Input
Drive pulse
Input
Dont care
Output
Expect low
Output
Expect high
Output
Outout
12-15
TDL Overview
enclosed in single quotes. There are seven inputs (CLOCK, IN1-1N6) and
four outputs (OUT1-OUT4).
C
*)
L
OOOO*)
O IIIIII UUUU*)
C NNNNNN TTTT*)
K 123456 1234*)
P:=TL_YYYYYY_MMMM;
P:=TC_HHHLLL_MMMM;
P:=TC_HLHLHH_1100;
P:=TC_LHLHHL_1Z00;
P:=TC_LHLHHL_1011;
Figure 0-10 shows the relationship between the set of test vectors and the
corresponding logic waveforms.
12-16
TDL Overview
Figure 1210. Relationship Between Test Vectors and Corresponding Logic Waveforms
CLOCK
IN1
IN2
IN3
IN4
IN5
IN6
OUT1
OUT2
OUT3
CLOCK
IN1
IN2
IN3
IN4
IN5
IN6
OUT1
OUT2
OUT3
OUT4
OUT4
12-17
TDL Overview
FROM
TO
MAX
REJECT
Indicates whether to reject a device having a measured value outside the min or max
limits. A YES value causes rejection. A NO value allows the test to be made but does
not reject devices measuring outside the limits.
Optional keywords:
CLKEDGE
Is required if the FROM signal is a clock. The two values for this parameter are
LEADING and TRAILING.
LEADING indicates the positive-going edge of a 010 clock or the negative-going edge
of a 101 clock.
TRAILING indicates the negative-going edge of a 010 clock or the positive-going edge
of a 101 clock.
MIN
Indicates minimum limits. Minimum limit testing is performed only by special request.
Keyword fields can be in any order. If the timing fields require more than one
line, each line must be terminated with a comma (,). The last line must end
with a double quote and semicolon (;).
As shown in Example 124, the ASIC_TEST statement means that you
should measure the propagation delay on the preceding pattern, from pin IN1
to pin OUT1, with a maximum limit of 85 ns.
O *)
(*$
ICU *)
(*$
NLT *)
(*$
1K1 *)
SETR P:TLCO;
12-18
TDL Overview
SETR P:THC1;
ASIC_TEST=PROP FROM=IN1,TO=OUT1,MAX=85NS,
REJECT=YES;
If the input signal is a clock, the edge must be specified. See Example 0-5 for
the specification of a clock-to-output measurement.
This statement defines the scanin and scanout pins for a particular scan path. A scanin
pin must be an input (IN). A scanout pin must be an output (OUT). Bidirectional pins
(INOUT) can be used for either scanin or scanout, but this is not recommended because
it requires extra circuitry.
SET
This statement is used to provide values for all pins prior to a SCAN statement. The
scan pin values in the SCAN statement take precedence over the SET statement
values. The pin values defined in the SET statement are not applied until the SCAN
statement is executed.
SCAN
The SCAN statement indicates that scanning is to be performed using the scan pin
values, described by SCAN_IN and SCAN_OUT. The number of scan cycles is
determined by the loop_count parameter.
Example 126 uses the previously listed TDL statements.
12-19
TDL Overview
SCAN1:= TLHLH;
Example 0-7 shows the scan vectors from Example 0-6 written in functional
TDL format. Notice how the redundant information expands the vectors.
Required keyword:
IDDQ
12-20
TDL Overview
MIN
<value> specifies the minimum allowed IDDQ value. <value> follows the usual conventions
for current specifications.
MAX
<value> specifies the maximum allowed IDDQ value. <value> follows the usual conventions
for current specifications.
If no limits are included, the IDDQ defaults for the given technology type are
used.
The IDDQ ASIC_TEST statement can be inserted in multiple locations in the
TDL.
For more reference material on the test program generation, refer to the
following sources:
Part 2 of this document, the Generic Test Access Port Application Report
Part 5 of this document, the ASIC TDL 91 Reference Guide
Part 6 of this document, the ASIC TDL 91 and Scan Designs
Reference Guide
12-21
TDL Overview
12-22
Chapter 13
The standard test access port works on all IEEE Standard 1149.1 devices.
The GTAP configuration requires additional circuitry for improved dc
parametric test capabilities.
Topic
Page
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Boundary-Scan Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Parametric Measurements Using Boundary-Scan Architecture 1310
Integrating Boundary-Scan Architecture and GTAP . . . . . . . . . 1318
13-1
Introduction
13.1
Introduction
The IEEE Standard 1149.1-1990 defines a standard test access port and
boundary-scan architecture. This circuitry is primarily intended to test system
interconnect. All device I/O pins can be made observable and controllable
respectively through boundary-scan cells. The IEEE Standard 1149.1 can
independently control the device I/O pins to send/receive test signals to and
from other IEEE Standard 1149.1 devices to test the interconnect. This
capability can also be used for dc parametric testing. For example, by
applying test patterns to the input pins and observing these pins with IEEE
Standard 1149, a VIH/VIL test can be made. Also, a VOH/VOL test can be
made by driving test patterns from the output pins with IEEE Standard 1149.1
and capturing the output pin values with IC automated test equipment (ATE).
The IEEE Standard 1149.1 has limited provisions for device internal testing
as well. The boundary-scan cells on the I/O pins can also drive test patterns
into the device and capture the devices response to the test patterns,
respectively. In addition to this capability, new capabilities can be integrated
into the boundary-scan architecture through user-defined test data registers.
Examples of test data registers are internal scan paths.
13-2
Boundary-Scan Architecture
13.2
Boundary-Scan Architecture
The boundary-scan architecture (see Figure 0-1) consists of four dedicated
test pins: Test Data In (TDI), Test Data Out (TDO), Test Mode Select (TMS)
and Test Clock (TCK). An optional Test Reset (TRST) pin is permitted. The
boundary-scan register surrounds the core logic (see Figure 0-2), and all
device I/O signals must pass through a boundary-scan cell (BSC). The
boundary-scan operations are programmed through the instruction register.
MUX
TDO
Bypass Register
Instruction Register
* Note: Optional
Instruction Decode
TMS
TAP Controller
TCK
13-3
Boundary-Scan Architecture
PI
SI
PI
PO
2-State
Output
Pin
PO
SI
SO
SO
SI
PU/PD
Input
Pin
PI
PO
PO
PI
SI
SO
SO
SI
PU/PD
PU/PD
Input
Pin
PI
PO
SI
On-Chip
System
Logic
PO
PI
3-State
Output
Pin
BUF
SO
PU/PD
SI
SO
Input
Pin
PO
PI
PO
PI
SI
SO
SO
SI
PU/PD
PI
PO
PI
PO
SI
SO
SCAN
IN
SCAN
OUT
BUF
Input/
Output
Pin
A 1-bit bypass register is required to put the test circuit in a bypass mode.
Boundary-scan permits optional circuits such as a device ID register, and
user-defined test data registers. All communication with the boundary-scan
registers is serial through the TDI/TDO pins. The test access port (TAP) is a
16-state controller. The TAP is controlled via the TMS/TCK pins. Refer to the
IEEE Standard 1149.1 for a more complete description of this circuit.
13-4
Boundary-Scan Architecture
Boundary-Scan Cell
MUX2
MODE
G1
SIGNAL IN
1
Y
1
SIGNAL
OUT
MUX1
SHIFT/LOAD
SCANOUT
G1
REG1
1
SCANIN
1D
REG2
C1
CLOCK A
1D
C1
CLOCK B
13-5
Boundary-Scan Architecture
rising edges on TCK guarantees that the TAP is in the Test-Logic-Reset state
regardless of the original state.
The TAP controller consists of two major state groups: Data Register (DR)
and Instruction Register (IR). These two groups are functionally identical. The
IR state group handles sampling (Capture-IR), loading/unloading (Shift-IR),
and activating (Update-IR) the instruction register. The DR state group
performs the same functions but for all other registers, i.e., boundary-scan,
device ID, test data register, etc. The instruction register contents select the
specific DR register. Only during the Shift-DR and Shift-IR states are the TDI
and TDO pins used for shifting in/out register data. All shifting is done
synchronous to the TCK clock. During all other states, the TDO pin is in highimpedance mode.
13-6
Boundary-Scan Architecture
Test-Logic-Reset
0
Run-Test/Idle
Select-DR-Scan
Select-IR-Scan
0
1
0
1
Capture-DR
Capture-IR
0
0
Shift-DR
Shift-IR
Exit1-DR
Exit1-IR
0
0
Pause-DR
Pause-IR
1
0
Exit2-DR
Exit2-IR
1
1
Update-DR
1
Update-IR
1
13-7
Boundary-Scan Architecture
13-8
Boundary-Scan Architecture
shift out. The PRELOAD data is loaded into the BSR update flip-flops during
the Update-DR state and the next falling edge of TCK. The binary value for
the SAMPLE/PRELOAD instruction is user-definable.
13-9
13.3
TAP
BSR
VIH/VIL
VOH/VOL
SRAM
Standby
dc Through
Current
Test
Vectors
IDDQ
IIH/IIL
IOZ
Note:
13-10
13-11
3) Serially reapply boundary-scan register data to TDI pin and clock each
bit with the rising edge of TCK. The boundary-scan register data must
force all bidirectional pins to input mode. Serially verify each value on the
TDO pin.
4) Transition TAP through the following states:
Exit-DRUpdate-DR
Step 9: For Schmitt-trigger inputs, repeat VIH test (Step 3 through Step 5).
Step 10: Reset the TAP. Transition TAP through the following states:
Update-DRSelect-DR-ScanSelect-IR-Scan
Test-Logic-Reset
Step 4: Set all 3-state and bidirectional pins to output mode and VOL pattern
(all outputs low).
1) Transition TAP through the following states:
Update-IRSelect-DR-ScanCapture-DRShift-DR
2) Serially apply boundary-scan register data to the TDI pin and clock each
bit with the rising edge of TCK. The boundary-scan register data must
force all 3-state and bidirectional pins to output mode. All output pins
should have VOL values.
3) Transition TAP through the following states:
Exit1-DRUpdate-DR
Step 5: Measure the VOL values at each output pin with the ATE.
Step 6: Reset the TAP. Transition TAP through the following states: UpdateDRSelect-DR-ScanSelect-IR-Scan
Test-Logic-Reset
13-13
13-14
13-15
13-16
The Shift-DR state also enables the TDO output. However, the
Shift-DR state cannot be arrived at following a TMS sequence of
0-1-1-0-0. If TMS fails VIH/VIL, then it would decode 1-1-1-1-1 or
0-0-0-0-0, neither of which could arrive at Shift-DR or Shift-IR
state.
Step 3: The TAP controller stays in Shift-IR state while TMS is held to logic
low. For the n-bit instruction register, apply n TCK clock pulses to
shift out the instruction register. The first two bits shifted out should
be a logic high followed by a logic low. These two output bits
constitute the TDO VOH/VOL test. Simultaneously, the first two bits
shifted in should be a logic high followed by a logic low.
Step 4: Apply two more TCK clocks. The next TDO values should be a logic
high followed by a logic low. These bits are a result of the first two
bits shifted in. This event indirectly confirms TDI VIH/VIL capability.
Step 5: If the optional TRSTZ signal is present, it should be held at a logic
high until now. Set TRSTZ to a logic low. The TAP controller should
be asynchronously reset from Shift-IR to Test-Logic-Reset state.
This would be detectable when TDO returns to high-impedance
state. Therefore, TRSTZ passes VIH/VIL.
13-17
13.4
13-18
TDI
TP000
TP000
TP000
TP000
MUX
TDO
Instruction Register
TEST_REG
Instruction Decode
TMS
TAP Controller
Shift_DR
Run-Test/Idle
TCK
* Note: Optional
13-19
GTT
GTT
GST
GST
TDI
TDIQ
TCK
GZ
C1
GST
C2
SI
G
GTT
SO
GZ
C1
GST
C2
SI
GTT
SO
GZ
C1
GST
C2
SI
G
GTT
SO
GZ
C1
C2
SI
SO
TP000
TP000
TP000
TP000
MSEL1
MSEL2
MSEL3
MSELn
TDO
13-20
TDI
TDIQ
GTT
GST
CK120
AN310
Shift-DR
2-Phase
Clock
Gener.
Shift-DRQ
3-Input AND
Gate
TCK
GTT
GST
IV110
13-21
IEEE Standard 1149.1 Rule 3.5.1b, The TDO driver shall be set to its inactive
drive state except when the scanning of data is in progress. An optional
pullup may be required for the TDO pin to ensure no accidental activations
(see Figure 139 and Figure 1310).
PAD
TDO
To TST_ENBL Circuit
Run-Test/Idle
TST_ENBL
3-Input AND
Gate
TDO
The GTAP test registers selected test features can be activated for dc
parametric testing under the following conditions:
Alternatively, an unused or shared input device pin can be dedicated for this
function. Some devices may not have any unused pins. Also, sharing a pin is
device-specific. By using the TDO pin (which always exists), integration into
the TI flow is simplified. This proposal assumes adoption of test activation
control via the TDO pin.
13-22
VIH/VIL Test
The VIH/VIL test is the same as for the boundary-scan architecture without the
GTAP test register.
VOH/VOL Test
The VOH/VOL test is the same as for the boundary-scan architecture without
the GTAP test register.
IDDQ Test
The IDDQ test comprises the following steps.
Step 1: Set ATE for an IDDQ test. All output and bidirectional pins are
unloaded.
Step 2: Initialize the device for test.
1) Apply power to the device under test.
2) Initialize the TAP controller by setting TMS to a logic high and toggling
TCK with five rising clock edges.
3) Apply sufficient normal vectors to prevent device states that may harm
the device (i.e., prevent bus contention).
Step 3: Initialize the GTAP test register.
1) Load TAP controller with TEST_REG private instruction.
2) Transition TAP through the following states:
Update-IRSelect-DR-ScanCapture-DRShift-DR
3) Serially apply GTAP test register data to the TDI pin and clock each bit
with the rising edge of TCK. The GTAP test register data is programmed
to force SRAMs into standby mode and turn off through-current macros.
4) Transition TAP through the following states:
Exit1-DRUpdate-DRRun-Test/Idle
13-23
5) Upon leaving the Shift-DR TAP state, force the TDO pin high.
Step 4: Apply customer-provided test vectors to device, stopping at vector
of interest.
Step 5: Force SRAMs into standby mode and turn off through-current
devices (pullups and pulldowns) by forcing the TDO pin low.
Step 6: Measure IDDQ at VCC pin.
Step 7: Return SRAMs and through-current devices to their normal states
by forcing the TDO pin high.
Step 8: Repeat Step 4 through Step 6 for all vectors of interest.
Step 9: Reset the TAP. Transition TAP through the following states:
Select-DR-ScanSelect-IR-ScanTest-Logic-Reset
IIH/IIL Test
The IIH/IIL test is the same as for the boundary-scan architecture without the
GTAP test register.
IOZ Test
The IOZ test comprises the following steps.
Step 1: Initialize the device for test.
1) Apply power to the device under test.
2) Initialize the TAP controller by setting TMS to a logic high and toggling
TCK with five rising clock edges.
3) Apply sufficient normal vectors to prevent device states that may harm
the device (that is, prevent bus contention).
Step 2: Initialize the GTAP test register.
1) Load TAP controller with TEST_REG private instruction.
2) Transition TAP through the following states:
Update-IRSelect-DR-ScanCapture-DRShift-DR
3) Serially apply GTAP test register data to TDI pin and clock each bit with
rising edge of TCK. The GTAP test register data is programmed to turn
off through-current macros.
13-24
13-25
13-26
Chapter 14
Military ASIC
Topic
Page
14-1
14.1
Military family data sheets that contain product and macro library
descriptions, an overview of the design flow and tools, and a summary of
the product families.
Design guidelines
Handoff requirements
Military standards compliance
Test application notes
Test strategy considerations
Tester constraints
Military ASIC dc parametric application notes
Prototype and production testing
14-2
14.2
FDS
MADG
Product description
Power estimation
D
D
Floorplanning (CHIPS)
Legend:
D
S
D
D
D
D
D
FDS
MADG
MLS
DM
DSM
DFT
ACE
CHIPS
TSG
MDF
Military ASIC
14-3
14-4
Appendix A
Glossary
A
ACE: ASIC Compiler Environment. The graphical user interface delivery
mechanism for submicron gate-array memory compiler elements.
ASIC: Application Specific Integrated Circuit. A device designed for a user
application, usually by the user.
asynchronous logic: A collection of logic elements with the signal timing
entirely dependent on the propagation delay of all elements in the signal
path. The resulting signal flow timing changes with variations in process
control, temperature, and power-supply voltage.
ASIC TDL 91: An improved TI TDL format that supports both narrow and
wide (SCAN) TDL. Narrow TDL lists the ATE state for all pins in every
cycle. Wide or SCAN TDL allows a description of only nonredundant ATE
states and pins.
ATE: Automated Test Equipment. Machines used to test silicon.
ATPG: Automatic Test Pattern Generation. A process by which the vectors
required to produce a high-fault coverage for a design are generated by
a program. These tools generally require scans in synchronous designs
and assume certain scan rules.
at-speed testing: Refers to test vectors that target the detection of delay
faults. The term usually apllies to test vectors that operate at design
frequency or that validate setup conditions.
AUTOGEN: A TI software tool that compiles an automated test equipment
program (ATE) program from TDL.
Automatic Test Pattern Generation: A methodology, using software tools,
to generate test patterns. Test patterns attempt to control and observe
each circuit node using a stuck-at model.
B
back annotation: The process of updating the design database with actual
interconnect delays (as opposed to estimations by design CAD software). The actual delays are calculated after placement and routing,
when exact interconnect lengths are known.
BIST: Built-In Self-Test. The capability of a product to carry out a functional
test of itself. Some support from external equipment may be required.
BIST usually involves special hardware in the product to generate input
stimuli and to analyze test responses.
block: A group of interconnected cells. May contain instances of other
blocks.
BNF: Backus Naur Form. A description of ASIC TDL 91.
BTL: Backplane Transceiver Logic. A form of transmission line driver and
receiver circuitry specified by IEEE Std 1149.1.
bus: A data distribution path that typically has multiple data receivers and
can have multiple data sources. Bus structures must be driven by threestate drivers. The drivers must be capable of disconnecting from the bus,
and only one such source can be active at one time.
bus contention: If more than one bus driver is active with conflicting output
levels at the same time, neither driver may be able to assert a true logic
level on the bus line. The result could be excessive drive current, undefined logic levels, and possible device failure.
bus holder: A logic device that prevents a bus from floating if all bus drivers
are placed into the high-impedance state. It maintains the last logic state.
C
cell: An individual component of a library (typically a logic gate; for example,
a NA210 2-input NAND gate). See macro.
CHIPS: Comprehensive Hierarchical Physical Synthesis. TIs submicron
gate-array floorplanning tool designed to improve design cycle time by
decreasing layout iterations. Includes PRELUDE delay estimation capabilities plus full graphic floorplanning.
circuit initialization: A sequence of stimuli that sets internal nodes of a
circuit to a predictable known state.
clock skew: The difference in clock edge timing across the chip. Loading
and interconnect capacitance cause the active clock edge to be delayed,
possibly disrupting critical circuit timing.
clocked scan: An edge-triggered scan methodology. The clocked scan flipflop has separate clock and data inputs for scan- and system-mode operation.
CMOS: Complementary Metal Oxide Semiconductor. A form of digital logic
that has the characteristics of low power consumption, wide power supply
range, and high noise immunity.
combinational fault: A functional fault whose effect on the behavior of the
circuit is not affected by the sequence of the input stimuli.
controllability: The ability of a node to be established at specific logic states
by applying stimuli to the circuits externally accessible nodes.
core logic: All logic functions except I/O buffers are core logic.
critical path:
CTL: CMOS Transceiver Logic. A form of transmission-line driver and receiver circuitry. These circuits allow CMOS devices to communicate in
a low-noise, terminated-transmission-line environment.
D
delay fault: A fault in a circuit that causes failure to meet ac specifications
but might not cause functional failure.
design-for-testability feature: Lets you specify a list of placement rules
describing the connectivity of any logic path you want to group.
design requirements document: A document to guide the product development that states the goals of the design. This type of document usually
includes functional description, performance goals, cost goals, testability
goals, and quality goals.
detectable fault: A functional fault for which a test pattern can be created
that always causes the effects of the fault to be observable at an externally accessible node.
detected fault: A functional fault that causes effects that are observed at
an externally accessible node when the circuit is exercised by the existing
test pattern.
Glossary
DFT: Design for Testability. A design goal requiring that each node be both
observable and controllable. Failure to achieve this design goal can
compromise quality assurance.
E
ECL: Emitter-Coupled Logic. A nonsaturating form of digital logic that eliminates transistor storage time as a speed-limiting characteristic, permitting very-high-speed operation.
F
fault: A defect that can cause a failure in the circuit operation/timing.
fault detectability ratio: The ratio of detectable faults to the sum of detectable and undetectable faults.
fault grade: A measurement of the efficiency of test vectors to detect manufacturing defects in silicon. The fault-grade value is usually presented
as a percentage of the stuck-at faults that can be identified using those
test vectors.
fault grading: The process of determining the test pattern fault coverage of
a circuit.
fault-tolerant design: A design approach to enhance the ability of a circuit
to remain operational after the occurrence of a fault. Fault-tolerance design techniques can impact fault detection.
floating bus: Any bus line not driven by an active device is free to assume
any voltage level. Circuits with inputs connected to this bus may draw
excessive current or otherwise malfunction.
floating input: The input of a macro can assume an undefined voltage level
if it is not driven to a defined logic level. Circuits with floating inputs can
draw excessive current or otherwise malfunction.
functional fault: A fault that causes improper logical operation of a circuit.
G
GTAP: Generic Test Access Port. The TI ASIC test controller. The GTAP can
be instructed to enable or disable any combination of DFT features.
I
I/O: Input/Output. An input/output or bidirectional buffer cell used to connect
design interface signals directly to package pins.
ICCQ:
IDDQ:
J
JTAG: Joint Test Action Group. 1) Committee that established the test access port (TAP) and boundary-scan architecture defined in IEEE Standard 1149.1-1990. 2) Common name for IEEE Std1149.1-1990.
L
LSSD: Level-Sensitive Scan Design. A scan methodology. It is a technique
where all logic storage elements in a device are chained together in a
dual mode. The first mode is the normal operation of the device where
clocks allow the storage of data in normal system operation. In the second mode, master and slave clocks are used to shift data in and out of
the device for testing purposes.
M
MegaModule:
ter files.
multiplexed flip-flop scan: Multiplexed flip-flop scan design is a scan methodology. It is a technique where all logic storage elements in a device
are chained together in a dual mode. A 2:1 multiplexer is placed at the
input of the logic storage elements. The first mode is the normal operation
of the device where the multiplexer allows the storage of data in normal
system operation. In the second mode, the multiplexer allows the shifting
of data in for test purposes.
netlist: A description of a logic circuit that names the macros used and
describes their interconnection.
Glossary
O
observability: The ability to determine the logic states of an internal circuit
node at the circuits externally accessible nodes.
open circuit fault: A fault in a circuit that alters the number of nodes by
breaking a node into two or more nodes.
P
parametric fault: A fault in a circuit that causes failure to meet ac or dc
specifications but might not cause functional failure.
parametric test: These are electrical tests that evaluate parameters such
as dc and ac electrical characteristics ( VIH, IDDQ, VOH, tpd, etc. ).
PECL: Pseudo ECL. Logic that is implemented to operate with standard 5V VCC and GND power supplies.
PMT: Parallel Module Test. A system of additional logic built into MegaModules for the purpose of enhancing the testability of the circuitry. Package
input and output pins are multiplexed with internal test circuitry to minimize the need for package pins dedicated to testing.
prelayout simulation: Accomplished as part of verification that the design
meets design specifications. To be effective, simulation must include
circuit evaluation using both minimum and maximum propagation delays.
The only unknown is actual interconnect capacitance. Interconnect capacitance is estimated by the design CAD software to give an assumed
value.
R
redundant circuit: Deliberate duplication of logical functions to create backup functions that enhance performance or reliability of operation.
RTL: Register Transfer Level. A subset of behavioral modeling constructs
that can be used to model a circuit at the level of data flowing between
a set of registers. This level of abstraction typically contains little timing
information, except references to a set of clock edges and features.
S
scan path: A shift register made up of the logic storage elements (standalone bit-storage devices). In test mode, the storage elements are connected in a shift register. During normal operation they carry out their
normal system functions. The scan path is used to shift test data into the
logic storage elements for controllability and to shift out test response
data for observability.
sequential fault: A functional fault whose effect on the behavior of the circuit
is affected by the sequence of the input stimuli.
short circuit fault: A fault in a circuit that alters the number of nodes by
connecting two or more nodes together.
simulation: The process of using workstation software to exercise a logic
design. When properly done, simulation verifies both circuit timing and
logic functionality.
state machine: A logic block that can assume any of several output logic
states in response to input stimuli. Each logic state is uniquely determined from the previous state and the previous input.
stuck-at-0 fault: A fault in a digital circuit characterized by a node remaining
at a logic low (0) state regardless of changes in input stimuli.
stuck-at-1 fault: A fault in a digital circuit characterized by a node remaining
at a logic high (1) state regardless of changes in input stimuli.
synchronous logic: Any group of logic storage elements through which the
signal flow timing is controlled by the system clock. Clock signals cause
data signals to advance from one logic storage element to the next, one
element at a time. The resulting signal flow is thus made predictable.
T
testable: An electronic circuit is testable if test patterns can be generated,
evaluated, and applied in such a way as to satisfy predefined levels of
performance defined in terms of fault-detection, fault-location, and testapplication criteria, within a predefined cost-budget and timescale.
TDL:
Glossary
U
undetectable fault: A functional fault for which no set of functional test vectors can be created that can guarantee that the effects of the fault are
observable at an externally accessible node.
undetected fault: A functional fault that causes effects that are not observed
at an externally accessible node when the circuit is exercised by the
existing test pattern.
V
VCC:
VDD:
Positive supply voltage or the voltage required across supply and VSS
terminals of a CMOS integrated circuit
VSS:
Index
$ 1-2
( ) 1-2
)
keyword fields end with 12-18
, 1-2
. 1-2
_ 1-2
1-2
0
TDL character 12-15
1
TDL character 12-15
A
ac critical paths
pattern sets 3-9
scan path loading on 6-11
ac margin 3-2
ACE
defined 1
activating, IR, updateIR group does 13-6
ad hoc tests 5-1
asynchronous circuits 5-7
bidirectional buffers 5-4
counters 5-10
dividers 5-10
gated clocks 5-8
internal clocks 5-9
internal node observability 5-3
Johnson counter test signal generator 5-18
known states 5-5
logic blocks 5-17
Index
asynchronous circuits
avoiding 5-7
gating clocks create 5-8
asynchronous clocks
not in scan path flipflops 6-10
asynchronous logic
defined 1
asynchronous timing
as ATPG constraint 11-9
ATE
block diagram 12-4
defined 1
loads 12-10
simulation example 12-11
logic simulator vs 12-2
pattern memory, DUT vectors stored in 12-3
test patterns operate on 12-1
ATPG 11-1
clock skew and 6-7
constraints 11-9
cycletime reduction from -3
debugging considerations 11-8
defined 1
design flow
typical 11-4
highfaultgrade test patterns and 3-10
introduction 11-2
path sensitization 11-5
scan designs 11-7
full 11-6
summary 11-10
testing considerations 11-8
tool -8
atspeed testing 4-4, 4-5, 12-5, 12-11
AUTOGEN
defined 1
PMT TDL sets converted by 4-5
automated test equipment 1-2
automatic test pattern generation 1-2
defined 1
automation, design
structured approach favors 6-2
B
back annotation
defined 2
backplane transceiver logic 1-2
Backus Naur Form 1-2
BiCMOS, TP0B0 macro 8-3
bidirectional buffers
test contention and 12-10
bidirectional buses
normal NAND tree patterns cause bus conflicts
10-6
bidirectional pins 1-2
internal access with 5-4
BIST
defined 2
TDL pattern sets for 4-3
BIST TDL 4-3
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
BIST TEST ENABLE, ASIC test 8-6
BIST_AC TDL
described 4-4
setup and hold testing and 12-11
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
bit definitions
for test register 8-5
block
defined 2
block diagrams
ATE 12-4
GTAP 8-2
GTAPcontrolled PMT 9-3
IEEE Standard 1149.1 hardware 13-3
BNF
defined 2
boundary-scan architecture 13-10
boundaryscan architecture 3-2, 7-2, 7-4, 10-12,
13-3, 13-5, 13-7, 13-8, 13-9, 13-10, 1312, 13-13, 13-14, 13-15, 13-16, 13-18,
13-19, 13-20, 13-21, 13-22, 13-23
boundaryscan cell 1-2, 13-5
boundaryscan instructions 13-8, 13-9, 13-14
boundaryscan macros 7-5, 7-6, 7-7
Index
Index
C
C
TDL character 12-15
captureIR group
sampling done by 13-6
cautions
information about vi
cells 1-2
defined 2
characters
simulator mapping 1-2
CHIPS
defined 2
circuit
testable
described 5-2
circuit design
typical flow
ATPG 11-4
circuit initialization 5-5
defined 2
clear mechanism
controllability added with 5-6
CLKEDGE keywords 12-18
CLOCK 6-5
shift register and 5-19
clock edge
to output
pintopin testing of 12-12
clock inputs
circuit initialization to known state and 5-5
clocked scan flipflops 6-3
clock signals
GTAP test registers and 13-20
TDL 12-7
width, minimum
illustrated 12-9
clock skew
defined 3
edgetriggered flipflop scan and 6-7
CLOCK statements
TDL 12-7
Clocked LSSD scan flip-flop
circuit interconnect
illustrated 6-9
illustrated 6-8
clocked NAND tree
input threshold voltage levels tested with 10-4
illustrated 10-5
shared control pins
Index
Index
illustrated 10-8
TGC1000 configurations
illustrated 10-7
TGC2000 configurations
illustrated 10-7
clocked scan 3-7
defined 3
clocked scan flipflop scan designs 6-3
macros, TI offers 6-3
clocked scan flipflop scan designs
multiple scan chains
illustrated 6-16
clocks 1-2
adding
to asynchronous latch 5-7
constraints
ATPG 11-9
flipflop scan design and 6-10
clocktooutput measurements 12-19
CMOS
defined 3
CMOS transceiver logic 1-2
combinational fault
defined 3
commas (,)
keyword fields separated by 12-18
compatibility
planning for 3-13
compiled cells
structured approach not suited for 6-20
complementary metal oxide semiconductor 1-2
Comprehensive Hierarchical Physical Synthesis
defined 2
constraints
ATPG 11-9
contact ix
contentions 1-2
tester vs TTL/CMOS bidirectional buffers 1210
control pins
dedicated
clocked NAND tree circuit
illustrated 10-5
voltage level test patterns 10-6
shared
D
DATA 6-3, 6-5
data corruption
bus contention causes 6-12
data inputs
clocked scan flipflops 6-3
data register
TAP group 13-6
dc leakage current
Index
Index
measuring 10-13
dc leakage test 1-2, 3-10
dc parametric measurements 10-1
input current 10-12
input threshold voltage levels
using clocked NAND tree 10-4
leakage current 10-13
output voltage levels 10-10
overview 10-2
threestate highimpedance 10-11
using boundary-scan architecture
resources 13-10
using boundaryscan architecture
GTAP and
test activation control pin
Index
Index
timetomarket -3
scan designs 6-1
strategy development 3-1
committing to 3-3
compatibility
planning for 3-13
diagnostic pattern set, creating 3-9
faultgrade requirements establishing 3-4
flowchart 3-14
gate density as base for 3-6
highfaultgrade test patterns, generating 3-10
IEEE Std 1149.1 as system requirement 3-5
structured tools
choosing 3-7
technology, selecting 3-2
test patterns
converting
to TDL 3-12
simulations 3-11
timing patterns, simulating 3-11
structured approaches 6-2
DIAGNOST TDL
described 4-4
if BIST TDL fails 4-3
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
diagnostics
pattern set establishment for debugging 3-9
differential amplifier
PMT I/O hookup 9-18, 9-19
digitaltoanalog converter
PMT I/O hookup 9-15, 9-16
direct access
to logic
multiplexing provides 5-12
directconnect PMT 1-2
dividers
bypassing 5-10
documentation
militaryspecific ASIC 14-3
double quotes ()
keyword fields end with 12-18
DR
TAP group 13-6
duration
Index
Index
minimum
of test periods 12-4
DUT
vectors applied to
stored in ATE pattern memory 12-3
E
ECL
defined 4
economics 1-2
tradeoffs -2, -4
edgetriggered clocks 5-8
edgetriggered flipflop scan designs 6-7
efficiency
scan designs not noted for 6-20
embedded memories
PMT tests 3-6
emittercoupled logic 1-2
EXPANSION
ASIC test 8-6
external chip circuitry
EXTEST instruction designed to test 13-9
EXTEST instructions 13-9
input threshold voltage levels checked using
clocked NAND tree 10-4
output voltage levels 10-10
threestate highimpedance measurements and
10-11
F
falltime measurements 1-2
fault
defined 4
fault coverage
described 1-2
determining target 11-2
device defect level vs -5
Motorola Delco study results -6
tradeoffs -4
fault detectability ratio
defined 4
fault grade 1-2
defined 4
development time vs
illustrated -3
requirements
establishing as part of DFT strategy development 3-4
fault grader -8
fault grading
defined 4
fault simulation 1-1
multiple scan chain designs and 6-14
faulttolerant design 4
feedback loops
combinatorial
as ATPG constraints 11-9
feedback paths
breaking
in nested sequential circuits 5-14
scan flipflops and 6-10
field maintenance costs
fault coverage and -5
flipflop outputs 5-13
flipflop scan designs 5-5, 6-3, 6-5, 6-7, 6-10
floating bus
defined 4
floating I/O inputs
avoid 10-13
floating input
defined 4
floating internal nodes
avoid 10-13
frequency dividers 5-5
FROM keywords 12-18
full scan designs 11-6
FUNC TDL
described 4-3
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
FUNC_AC TDL
described 4-4
setup and hold testing and 12-11
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
Index
Index
functional fault
defined 4
G
gate density
DFT strategy development based on 3-6
gatecount margin 3-2
gated clocks
avoiding 5-8
GBUSENZ signals 13-20
generating
test patterns 12-1
ATE block diagram 12-4
creating 12-6
input delay groups 12-6
illustrated 12-7
TDL
example 12-15
propagation delay measurements
specifying, in TDL 12-17
quiescent current measurements 12-20
scan 12-19
TDL clocks 12-7
test precautions
special 12-10
width, minimum
example 12-9
introduction 12-2
H
H
TDL character 12-15
hardware
design testability affects on 1-1
overhead
for multiplexed flipflop scan designs 6-6
help with designs ix
HI Z
ASIC test selection codes 8-6
Index
Index
I
I/O
defined 5
I/O buffers
multiplexed PMT and 9-7
I/O ports
BSC connects 13-5
ICC TDL
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
ICCQ
defined 5
keywords 12-20
IDDQ
defined 5
test location and pattern set identification 1014
IDDQ TDL
described 4-3
IDDQ test 1-2, 13-10, 13-13
location and pattern set identification 10-14
using boundaryscan architecture and GTAP
test register 13-23
IDR
described 7-5
IEEE Standard 1149.1 1-2, 7-1
boundaryscan architecture 7-3, 7-4
circuit not adhering to
Index
Index
J
Johnson counter
test signal generator 5-18
Joint Test Action Group 1-2
JTAG 3-2
defined 5
L
L
TDL character 12-15
latches
set, reset capabilities needed for circuit initialization 5-5
layout errors
failures and 11-8
leakage current 10-13
levelsensitive scan design 1-2
Index
10
Index
defined 5
multiple clocked scan chains
illustrated 6-18
LSSD scan flip-flop design 6-8
M
M
TDL character 12-15
macro functions
structured approach not suited for 6-20
macros 1-2
clocked scan flipflop 6-3
multiplexed flipflop scan design 6-5
MagaModules
test collar 9-4
mask fabrication defects
failures and 11-8
MAX keywords 12-18, 12-21
MCLK
GTAP controller pin 8-7
measurements
parametric 10-1
input current 10-12
input threshold voltage levels
using clocked NAND tree 10-4
leakage current 10-13
output voltage levels 10-10
overview 10-2
threestate highimpedance 10-11
MegaModule
PMT I/O hookup 9-5, 9-7, 9-9, 9-12, 9-15, 916, 9-18, 9-19
MegaModules
defined 5
described 9-2
logic functions
tested by PMT TDL 4-4
multiplexed PMT
insystem use 9-21
rules 9-8
PMT I/O hookup 9-5, 9-7
PMT test for 9-2
N
nesting
sequential circuits
feedback paths in
breaking 5-14
netlist
defined 5
node
defined 6
nondigital circuitry
structured approach not suited for 6-20
notational conventions v
Index
11
Index
observability
debugging time and -4
defined 6
of I/O ports, via BSC 13-5
of internal nodes
improving via unused pins 5-3
of logic
multiplexing improves 5-12
scan designs and 6-2
shift register used to obtain 5-20
test vector generation and 5-2
onchip oscillator circuitry 5-9
open circuit fault
defined 6
oscillators
PWRDN pin 10-13
oscilloscopes
ineffective in debugging ASIC systems -4
output signals
test vectors define 12-6
TO keyword indicates 12-18
output strobe groups
test pattern generation and 12-9
placement
example 12-10
precautions
special 12-10
output voltage levels
testing 10-10
overhead
for clocked scan flipflop designs 6-4
for multiplexed flipflop scan designs 6-6
overview
ATPG 11-2
GTAP 8-2
IEEE Standard 1149.1 7-2
parametric measurements 10-2
PMT 9-1
TDL 12-13
test pattern generation 12-2
ownership
costs -5
illustrated -9
package pins
pintopin testing of 12-11
parallel module test 1-2
parallel scan chains 3-8
parallel scan designs 6-14
parallel testing 6-14
time determined by longest chain 6-15
parametric fault
defined 6
parametric measurements 10-1
input current 10-12
input threshold voltage levels
using clocked NAND tree 10-4
leakage current 10-13
output voltage levels 10-10
overview 10-2
threestate highimpedance 10-11
parametric test
defined 6
partial scan 3-8
partial scans
designs 11-7
partitioning
circuits
in multiple scan chains 6-14
path sensitization
ATPG and 11-5
PATH statements
description 12-19
pattern sets
diagnostic
establishing 3-9
parallel module tests 4-4
scan 4-3
pattern statements
IDDQ 10-14
PCB
boundaryscannable 7-7
costofownership orderofmagnitude relationship for -8
defect rates for -7
ASIC PPM vs
illustrated -8
Index
12
Index
described 4-4
power supply
quiescent current measurements
ASIC_TEST statements define 12-20
predictability
of designs 5-2
prelayout simulation
defined 6
preload
multiplexed PMT appropriate for 9-21
PRELOAD instructions 13-8
printed circuit boards 1-2
private instructions
TEST_REG 13-19
process yields
in Williams model -5
PROP keywords 12-18
propagation delay tests 1-2
edgetriggered clock and 5-8
measurements
example 12-18
one needed per design 4-3
pintopin testing verifies 12-11
PROP keyword indicates 12-18
responsibilities for 4-2
specifying measurements in TDL 12-17
TGC1000 TDL pattern set requirements 4-5
TGC2000 TDL pattern set requirements 4-5
pseudo ECL 1-2
PU/PD CURRENT
ASIC test 8-6
public instructions 13-8
pulldown macros
PWRDN pin 10-13
pullup macros
PWRDN pin 10-13
pulsegenerating circuitry 5-9
PWRDN
ASIC test selection codes 8-6
TP000 bit assignments 8-5
PWRDN pin 10-13
PWRDN STATE
ASIC test 8-6
Index
13
Index
Q
quiescent power supply current measurements
ASIC_TEST statement defines 12-20
R
random access memory
structured approaches not suited for 6-20
random vector generation
ATPG 11-5
read only memory
structured design approach not suited for 6-20
reconverging signals
watching for 5-16
redundant logic
defined 6
testing 5-15
register files
structured approach not suited for 6-20
register transfer level
defined 6
registers 1-2
as overhead for multiplexed flipflop scan designs 6-6
REJECT keywords 12-18
reset capabilities
initializing circuit to known state requires, for
latches, flipflops 5-5
RESETZ
shift register and 5-19
RESTORE1
test condition 8-8
RESTORE2
test condition 8-8
review process
design
DFT strategy development and 3-4
risetime measurement 1-2
RTL
defined 6
rule checking
structured approach favors 6-2
S
safe circuit initialization pattern 10-4, 10-10, 1011
SAMPLE/PRELOAD instructions 13-8
input threshold voltage levels checked using
clocked NAND tree 10-4
output voltage levels 10-10
threestate highimpedance measurements and
10-11
sampling
IR
captureIR group does 13-6
SCAN
GTAP controller pin 8-7
scan 3-7
DFT strategy development and 3-2
sequential logic tested best with 3-7
scan chains
parallel 3-8
SCAN CLOCK 6-3, 6-4
clock skew and 6-7
scan designs 1-2, 6-1
bus contention
scan testing and 6-12
clocked scan flipflop 6-3
edgetriggered flipflop 6-7
flipflop guidelines 6-10
inefficiencies in certain structures 6-20
multiplexed flipflop 6-5
parallel 6-14
partial
ATPG and 11-7
scan path loading
on critical ac path 6-11
structured approaches 6-2
testisolation modules 6-14
SCAN ENABLE 6-5, 6-6
Index
14
Index
scan macros
partitioning logic reduces number of 6-15
scan paths
defined 7
flipflops 6-7
flipflops in 6-10
integrity
GTAPCHK TDL checks 4-4
SCANCHK TDL checks 4-3
inversions 6-11
isolating loading
with inverter
illustrated 6-11
loading
on critical ac paths 6-11
multiple
as testisolatable modules 6-14
clocked scan flipflop scan designs 6-16
LSSD
illustrated 6-18
multiplexed flipflop scan designs 6-17
patterns 6-18
test patterns, multiple 6-18
scan rings 6-20
SCAN statements
description 12-19
SCAN TDL
described 4-3
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
scan testing
bus contention and 6-12
SCAN_AC TDL
described 4-4
setup and hold testing and 12-11
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
SCANCHK TDL
described 4-3
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
SCANIN DATA 6-3, 6-5
SCANOUT 6-3
SCLK
GTAP controller pin 8-7
select inputs
circuit initialization to known state and 5-5
semicolon ( 12-18
sequential circuits
bypassing 5-10
nests
breaking feedback paths in 5-14
sequential fault
defined 7
sequential logic
scan approach best for testing 3-7
serial shift register
test register is 8-3
set capabilities
initializing circuit to known state requires, for
latches, flipflops 5-5
SET statements
description 12-19
setup and hold testing 12-11
shift registers
observability obtained by using 5-20
scan chain
circuit initialization to known state and 5-5
serial
test register is 8-3
test signal generator 5-19
shiftIR group
loading done by 13-6
short circuit fault
defined 7
signal generators
test
Johnson counter 5-18
shift register 5-19
signals
paths
long scan chains
separating from 6-11
reconverging 5-16
separating
unused pins control 5-17
types
TDL toggle states
required for various 10-3
silicon
Index
15
Index
overhead
for clocked scan flipflop designs 6-4
for multiplexed flipflop scan designs 6-6
simulations
ATE loads and 12-10
example 12-11
defined 7
test pattern 3-11
skew, scan 1-2
slave clock
interface circuit
TCKtoMaster 13-21
splitting long counter chains 5-11
SR 1-2
SRAM
MegaModules 9-2
SRAM OFF
ASIC test selection codes 8-6
SRAM standby
dc parametric test resources 13-10
SRAM_OFF
TP000 bit assignments 8-5
SRL 1-2
state machine
controllability
using clear to add
illustrated 5-6
defined 7
state machines
uncontrollable
illustrated 5-5
state transition diagram
GTAP controller 8-9
states
initializing circuit to known 5-5
static testing
ICC TDL facilitates 4-3
status check
multiplexed PMT appropriate for 9-21
strategies
for testability, developing 3-1
commitment to design practices 3-3
compatibility planning 3-13
diagnostic pattern set for debugging 3-9
T
TAP 1-2
boundaryscan architecture 13-5
controller 7-4
dc parametric test resources 13-10
described 13-4
DFT strategy development and 3-2
IEEE Standard 1149.1 and 7-2
state diagram 13-7
Index
16
Index
TCK
boundaryscan architecture test pin 13-3
to Master
slave clock interface circuit 13-21
TDI
boundaryscan architecture test pin 13-3
TDL 1-2
BIST_AC pattern types 12-11
clocks 12-7
definition
example 12-8
width
minimum
illustrated 12-9
defined 7
example 12-15
FUNC_AC pattern types 12-11
IDDQ location 10-14
propagation delay measurements
specifying 12-17
quiescent power supply current measurements
defined in 12-20
scan 12-19
example 12-19
vectors 12-20
SCAN_AC pattern types 12-11
simulation timing and 3-11
test pattern created by 12-6
ATE loads 12-10
simulation example 12-11
clocks 12-7
input delay group 12-6
output strobe groups 12-9
placement
example 12-10
BIST 4-3
pattern sets
Index
17
Index
creates 12-6
example 12-15
input delay groups 12-6
output strobe groups 12-9
performance test procedures 12-11
propagation delay measurements, specifying 12-17
quiescent power supply current measurements defined in 12-20
scan 12-19
example 12-19
vectors 12-20
TDLs create
ATE loads 12-10
clocks 12-7
output strobe groups
placement
example 12-10
precautions
special 12-10
tester period slip 12-5
handing off
to TI
in TDL format 4-2
highfault grade 11-1
highfaultgrade 3-10
requirements 4-1
responsibilities for providing 4-2
scan path
multiple 6-18
simulations 3-11
TDL type descriptions 4-3
test costs and -2
timing 3-11
test periods
duration of
minimum 12-4
input delay group relationship to
illustrated 12-7
test pins
boundaryscan architecture 13-3
test procedures
performance
TDL 12-11
atspeed testing 12-11
pintopin testing 12-11
setup and hold testing 12-11
test program
defined 8
test register 8-3
architecture
typical
illustrated 8-4
bit definitions 8-5
building block
illustrated 8-3
described 8-3
test selection codes 8-6
Test Reset
boundaryscan architecture test pin 13-3
test selection codes
for test register 8-6
test signal generators
Johnson counter 5-18
Index
18
Index
shift register
observability obtained from 5-20
shift registers
test signal generator 5-19
area impact and -2
introduction 1-1
of logic
multiplexing improves 5-13
overlooked, in design process -2
performance impact and -2
principles, applying early in process 1-1
scan designs and 6-2
schemes 1-2
structured 6-1
approaches to 6-2
bus contention
scan testing and 6-12
clocked scan flipflop 6-3
edgetriggered flipflop 6-7
flipflop scan design 6-10
LSSD 6-8
multiplexed flipflop 6-5
scan path loading
on critical ac path 6-11
scan paths 6-20
testisolatable modules 6-14
testisolation modules
multiple scan paths
patterns 6-18
testisolation modules 6-14
structured tools
choosing 3-7
clocked scan 3-7
LSSD 3-8
multiplexed flipflop scan 3-7
parallel scan chains 3-8
partial scan 3-8
testable
defined 7
TESTDATA
shift register and 5-19
testers
commercial -2
constraints 3-11
described 3-11
Index
19
Index
U
undetectable fault
defined 8
undetected fault
defined 8
unloading
IR
shiftIR group does 13-6
updateIR group
activating IR done by 13-6
user test data register 7-5
Index
20
Index
UTDR
described 7-5
V
vendors
design process and -2
VIH/VIL and VOH/VIL test (TAP pins) 13-10
VIH/VIL and VOH/VOL test (TAP pins) 13-16
using boundaryscan architecture and GTAP
test register 13-26
VIH/VIL test 13-10
ASIC test selection codes 8-6
using boundaryscan architecture and GTAP
test register 13-23
VIH/VIL_CLK_A
ASIC test 8-6
VIH/VIL_CLK_B
ASIC test 8-6
VIH_VIL
TP000 bit assignments 8-5
VIH_VIL CLK SELECT
ASIC test selection codes 8-6
TP000 bit assignments 8-5
VIH_VIL TDL
described 4-4
input threshold voltage levels 10-4
parametric testing and 10-2
TGC1000 pattern set requirements 4-5
TGC2000 pattern set requirements 4-5
VOH/VOL test 13-10, 13-12
using boundaryscan architecture and GTAP
test register 13-23
VOL/VOH
ASIC test 8-6
voltage level measurements 10-1
input current 10-12
input threshold
using clocked NAND tree 10-4
leakage current 10-13
output 10-10
overview 10-2
threestate highimpedance 10-11
W
wafer fabrication defects
failures and 11-8
warnings
information about vi
waveform analyzers
ineffective in debugging ASIC systems -4
Williams fault coverage model -5
Motorola, Delco study supports -6
WRITE
test condition 8-8
Y
Y
TDL character 12-15
Z
Z
TDL character 12-15
Index
21
Index
Index
22
Index
Index
23
Index
Index
24
Index
Index
25
Index
Index
26
Index
Index
27
Index
Index
28
Index
Index
29
Index
Index
30
Index
Index
31
Index
Index
32
Index
Index
33
Index
Index
34
Index
Index
35
Index
Index
36
Appendix A
Glossary
A
ACE: ASIC Compiler Environment. The graphical user interface delivery
mechanism for submicron gate-array memory compiler elements.
ASIC: Application Specific Integrated Circuit. A device designed for a user
application, usually by the user.
asynchronous logic: A collection of logic elements with the signal timing
entirely dependent on the propagation delay of all elements in the signal
path. The resulting signal flow timing changes with variations in process
control, temperature, and power-supply voltage.
ASIC TDL 91: An improved TI TDL format that supports both narrow and
wide (SCAN) TDL. Narrow TDL lists the ATE state for all pins in every
cycle. Wide or SCAN TDL allows a description of only nonredundant ATE
states and pins.
ATE: Automated Test Equipment. Machines used to test silicon.
ATPG: Automatic Test Pattern Generation. A process by which the vectors
required to produce a high-fault coverage for a design are generated by
a program. These tools generally require scans in synchronous designs
and assume certain scan rules.
at-speed testing: Refers to test vectors that target the detection of delay
faults. The term usually apllies to test vectors that operate at design
frequency or that validate setup conditions.
AUTOGEN: A TI software tool that compiles an automated test equipment
program (ATE) program from TDL.
Automatic Test Pattern Generation: A methodology, using software tools,
to generate test patterns. Test patterns attempt to control and observe
each circuit node using a stuck-at model.
B
back annotation: The process of updating the design database with actual
interconnect delays (as opposed to estimations by design CAD software). The actual delays are calculated after placement and routing,
when exact interconnect lengths are known.
BIST: Built-In Self-Test. The capability of a product to carry out a functional
test of itself. Some support from external equipment may be required.
BIST usually involves special hardware in the product to generate input
stimuli and to analyze test responses.
block: A group of interconnected cells. May contain instances of other
blocks.
BNF: Backus Naur Form. A description of ASIC TDL 91.
BTL: Backplane Transceiver Logic. A form of transmission line driver and
receiver circuitry specified by IEEE Std 1149.1.
bus: A data distribution path that typically has multiple data receivers and
can have multiple data sources. Bus structures must be driven by threestate drivers. The drivers must be capable of disconnecting from the bus,
and only one such source can be active at one time.
bus contention: If more than one bus driver is active with conflicting output
levels at the same time, neither driver may be able to assert a true logic
level on the bus line. The result could be excessive drive current, undefined logic levels, and possible device failure.
bus holder: A logic device that prevents a bus from floating if all bus drivers
are placed into the high-impedance state. It maintains the last logic state.
C
cell: An individual component of a library (typically a logic gate; for example,
a NA210 2-input NAND gate). See macro.
CHIPS: Comprehensive Hierarchical Physical Synthesis. TIs submicron
gate-array floorplanning tool designed to improve design cycle time by
decreasing layout iterations. Includes PRELUDE delay estimation capabilities plus full graphic floorplanning.
circuit initialization: A sequence of stimuli that sets internal nodes of a
circuit to a predictable known state.
clock skew: The difference in clock edge timing across the chip. Loading
and interconnect capacitance cause the active clock edge to be delayed,
possibly disrupting critical circuit timing.
clocked scan: An edge-triggered scan methodology. The clocked scan flipflop has separate clock and data inputs for scan- and system-mode operation.
CMOS: Complementary Metal Oxide Semiconductor. A form of digital logic
that has the characteristics of low power consumption, wide power supply
range, and high noise immunity.
combinational fault: A functional fault whose effect on the behavior of the
circuit is not affected by the sequence of the input stimuli.
controllability: The ability of a node to be established at specific logic states
by applying stimuli to the circuits externally accessible nodes.
core logic: All logic functions except I/O buffers are core logic.
critical path:
CTL: CMOS Transceiver Logic. A form of transmission-line driver and receiver circuitry. These circuits allow CMOS devices to communicate in
a low-noise, terminated-transmission-line environment.
D
delay fault: A fault in a circuit that causes failure to meet ac specifications
but might not cause functional failure.
design-for-testability feature: Lets you specify a list of placement rules
describing the connectivity of any logic path you want to group.
design requirements document: A document to guide the product development that states the goals of the design. This type of document usually
includes functional description, performance goals, cost goals, testability
goals, and quality goals.
detectable fault: A functional fault for which a test pattern can be created
that always causes the effects of the fault to be observable at an externally accessible node.
detected fault: A functional fault that causes effects that are observed at
an externally accessible node when the circuit is exercised by the existing
test pattern.
Glossary
DFT: Design for Testability. A design goal requiring that each node be both
observable and controllable. Failure to achieve this design goal can
compromise quality assurance.
E
ECL: Emitter-Coupled Logic. A nonsaturating form of digital logic that eliminates transistor storage time as a speed-limiting characteristic, permitting very-high-speed operation.
F
fault: A defect that can cause a failure in the circuit operation/timing.
fault detectability ratio: The ratio of detectable faults to the sum of detectable and undetectable faults.
fault grade: A measurement of the efficiency of test vectors to detect manufacturing defects in silicon. The fault-grade value is usually presented
as a percentage of the stuck-at faults that can be identified using those
test vectors.
fault grading: The process of determining the test pattern fault coverage of
a circuit.
fault-tolerant design: A design approach to enhance the ability of a circuit
to remain operational after the occurrence of a fault. Fault-tolerance design techniques can impact fault detection.
floating bus: Any bus line not driven by an active device is free to assume
any voltage level. Circuits with inputs connected to this bus may draw
excessive current or otherwise malfunction.
floating input: The input of a macro can assume an undefined voltage level
if it is not driven to a defined logic level. Circuits with floating inputs can
draw excessive current or otherwise malfunction.
functional fault: A fault that causes improper logical operation of a circuit.
G
GTAP: Generic Test Access Port. The TI ASIC test controller. The GTAP can
be instructed to enable or disable any combination of DFT features.
I
I/O: Input/Output. An input/output or bidirectional buffer cell used to connect
design interface signals directly to package pins.
ICCQ:
IDDQ:
J
JTAG: Joint Test Action Group. 1) Committee that established the test access port (TAP) and boundary-scan architecture defined in IEEE Standard 1149.1-1990. 2) Common name for IEEE Std1149.1-1990.
L
LSSD: Level-Sensitive Scan Design. A scan methodology. It is a technique
where all logic storage elements in a device are chained together in a
dual mode. The first mode is the normal operation of the device where
clocks allow the storage of data in normal system operation. In the second mode, master and slave clocks are used to shift data in and out of
the device for testing purposes.
M
MegaModule:
ter files.
multiplexed flip-flop scan: Multiplexed flip-flop scan design is a scan methodology. It is a technique where all logic storage elements in a device
are chained together in a dual mode. A 2:1 multiplexer is placed at the
input of the logic storage elements. The first mode is the normal operation
of the device where the multiplexer allows the storage of data in normal
system operation. In the second mode, the multiplexer allows the shifting
of data in for test purposes.
netlist: A description of a logic circuit that names the macros used and
describes their interconnection.
Glossary
O
observability: The ability to determine the logic states of an internal circuit
node at the circuits externally accessible nodes.
open circuit fault: A fault in a circuit that alters the number of nodes by
breaking a node into two or more nodes.
P
parametric fault: A fault in a circuit that causes failure to meet ac or dc
specifications but might not cause functional failure.
parametric test: These are electrical tests that evaluate parameters such
as dc and ac electrical characteristics ( VIH, IDDQ, VOH, tpd, etc. ).
PECL: Pseudo ECL. Logic that is implemented to operate with standard 5V VCC and GND power supplies.
PMT: Parallel Module Test. A system of additional logic built into MegaModules for the purpose of enhancing the testability of the circuitry. Package
input and output pins are multiplexed with internal test circuitry to minimize the need for package pins dedicated to testing.
prelayout simulation: Accomplished as part of verification that the design
meets design specifications. To be effective, simulation must include
circuit evaluation using both minimum and maximum propagation delays.
The only unknown is actual interconnect capacitance. Interconnect capacitance is estimated by the design CAD software to give an assumed
value.
R
redundant circuit: Deliberate duplication of logical functions to create backup functions that enhance performance or reliability of operation.
RTL: Register Transfer Level. A subset of behavioral modeling constructs
that can be used to model a circuit at the level of data flowing between
a set of registers. This level of abstraction typically contains little timing
information, except references to a set of clock edges and features.
S
scan path: A shift register made up of the logic storage elements (standalone bit-storage devices). In test mode, the storage elements are connected in a shift register. During normal operation they carry out their
normal system functions. The scan path is used to shift test data into the
logic storage elements for controllability and to shift out test response
data for observability.
sequential fault: A functional fault whose effect on the behavior of the circuit
is affected by the sequence of the input stimuli.
short circuit fault: A fault in a circuit that alters the number of nodes by
connecting two or more nodes together.
simulation: The process of using workstation software to exercise a logic
design. When properly done, simulation verifies both circuit timing and
logic functionality.
state machine: A logic block that can assume any of several output logic
states in response to input stimuli. Each logic state is uniquely determined from the previous state and the previous input.
stuck-at-0 fault: A fault in a digital circuit characterized by a node remaining
at a logic low (0) state regardless of changes in input stimuli.
stuck-at-1 fault: A fault in a digital circuit characterized by a node remaining
at a logic high (1) state regardless of changes in input stimuli.
synchronous logic: Any group of logic storage elements through which the
signal flow timing is controlled by the system clock. Clock signals cause
data signals to advance from one logic storage element to the next, one
element at a time. The resulting signal flow is thus made predictable.
T
testable: An electronic circuit is testable if test patterns can be generated,
evaluated, and applied in such a way as to satisfy predefined levels of
performance defined in terms of fault-detection, fault-location, and testapplication criteria, within a predefined cost-budget and timescale.
TDL:
Glossary
U
undetectable fault: A functional fault for which no set of functional test vectors can be created that can guarantee that the effects of the fault are
observable at an externally accessible node.
undetected fault: A functional fault that causes effects that are not observed
at an externally accessible node when the circuit is exercised by the
existing test pattern.
V
VCC:
VDD:
Positive supply voltage or the voltage required across supply and VSS
terminals of a CMOS integrated circuit
VSS: