Professional Documents
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1. How to find word which is occuring number of times with linux in just one command?
Ans:
With Grep Command:
grep -o 'needle' file | wc -l
With AWK command:
awk -F'^needle | needle | needle$' '{c+=NF-1}END{print c}'
2. What is grep -v?
Ans:
Too find pattern matching word, use grep command & it switch -v is added then the found word
will be neglected including that raw.
3. How to find pattern in TCL?
Ans:
string match f* foo
4. what is diff between blocking & nonblocking? explain with example.
Ans:-Blocking assignments evaluate the RHS and update the LHS without interruption from any
other verilog statement
-A nonblocking assignment evaluates the RHS at the beginning of the time step and updates the
LHS at the end of the time step.
module block_nonblock();
reg a, b, c, d , e, f ;
// Blocking assignments
initial begin
a = #10 1'b1;// The simulator assigns 1 to a at time 10
b = #20 1'b0;// The simulator assigns 0 to b at time 30
c = #40 1'b1;// The simulator assigns 1 to c at time 70
end
// Nonblocking assignments
initial begin
d <= #10 1'b1;// The simulator assigns 1 to d at time 10
e <= #20 1'b0;// The simulator assigns 0 to e at time 20
f <= #40 1'b1;// The simulator assigns 1 to f at time 40
end
endmodule
5. What is diff between $finish & $stop?
Ans:$finish;
Finishes a simulation and exits the simulation process.
$stop;
Halts a simulation and enters an interactive debug mode.
You can easily see that the CMOS circuit functions as an inverter by noting that when VIN is five
volts, VOUT is zero, and vice versa. Thus when you input a high you get a low and when you input
a low you get a high.
9. What is Latchup?
ANS :
CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to
the base of the other transistor in a positive feedback structure.
A phenomenon called latchup can occur when:
(1) both BJT's conduct, creating a low resistance path between Vdd and GND and
(2) the product of the gains of the two transistors in the feedback loop, b1 x b2, is greater than one.
The result of latchup is at the minimum a circuit malfunction, and in the worst case, the destruction
of the device.
Latchup may begin when Vout drops below GND due to a noise spike or an improper circuit
hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn on
Q2 (I Rsub > 0.7 V ), this will draw current through Rwell. If the voltage drop across Rwell is high
enough, Q1 will also turn on, and a self-sustaining low resistance path between the power rails is
formed.
If the gains are such that b1 x b2 > 1, latchup may occur.
Once latchup has begun, the only way to stop it is to reduce the current below a critical level,
usually by removing power from the circuit.
Preventing latchup:
1). Reduce the gain product b1 x b1
move n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces
gain beta2 > also reduces circuit density
buried n+ layer in well reduces gain of Q1
2). Reduce the well and substrate resistances, producing lower voltage drops
higher substrate doping level reduces Rsub
reduce Rwell by making low resistance contact to GND
guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic
resistances.
The free command is the most simple and easy to use command to check memory usage on
linux. Here is a quick example
2. /proc/meminfo
The next way to check memory usage is to read the /proc/meminfo file. Know that the /proc
file system does not contain real files. They are rather virtual files that contain dynamic
information about the kernel and the system.
3. vmstat
The vmstat command with the s option, lays out the memory usage statistics much like the
proc command.
4. top command
The top command is generally used to check memory and cpu usage per process. However it
also reports total memory usage and can be used to monitor the total RAM usage. The
header on output has the required information. Here is a sample output
21 What is synthesis?
Ans. Synthesis is a process if conversion of RTL file (that is technology independent) to get level
NETLIST file (that is technology dependent).
22 What is synthesis process?
Ans. There are 3 steps in Synthesis Process:
Translation: RTL code is translated to technology independent representation. The converted logic
is available in boolean equation form.
Optimization: Boolean equation is optimized using SoP or PoS optimization methods.
Technology mapping: Technology independent boolean logic equations are mapped to technology
dependant library logic gates based on design constraints, library of available technology gates.
This produces optimized gate level representation which is generally represented in verilog.
23 Input and Output of synthesis.
Ans.
INPUT:RTL- Register Transfer Level
RTL is the functional description of the design to logic synthesis which is represented by
HDIs.
Register: Storage element like F-F, latches
Transfer: Transfer data between input, output and register using combinational logic.
Level: Level of Abstraction modeled using HDL.
Target Library:
use of print$2 in above command to extract word after the pattern : matching as shown in above
fig.
And use of print$1 in above command to extract word before the pattern : matching as shown in
above fig.
25. In cmos inverter if we change nmos instead of pmos so what effect occurred.
Ans. If we change the position of nmos and pmos so it work as a week buffer.
initial begin
a = #10 1'b1;// The simulator assigns 1 to a at time 10
b = #20 1'b0;// The simulator assigns 0 to b at time 30
c = #40 1'b1;// The simulator assigns 1 to c at time 70
end
// Nonblocking assignments
initial begin
d <= #10 1'b1;// The simulator assigns 1 to d at time 10
e <= #20 1'b0;// The simulator assigns 0 to e at time 20
f <= #40 1'b1;// The simulator assigns 1 to f at time 40
end
endmodule
33. What is the difference between $monitor & $finish?
Ans.
$monitor displays every time one of its parameters changes.
$finish exits the simulator back to the operating system.
34. What is FSM?
Ans.
In general, a state machine is any device that stores the status of something at a given time and can
operate on input to change the status and/or cause an action or output to take place for any given
change.
35. Write a code for D_FF?
Ans.
module dff (q,data,clk,reset);
output q;
reg q;
input data,clk,reset;
always @(reset or posedge clk)
if (~reset)
begin
q <= 1'b0;
end
else
begin
q <= data;
end
endmodule
36. What is lappend?
Ans.
Lappend is similar to append except that the values are appended as list elements rather than raw
text. This command provides a relatively efficient way to build up large lists.
BIST sends out test patterns generated by a pseudorandom pattern generator (PRPG) along scan
chains and then collects the responses in a multiple-input signature register (MISR). The final
content of the MISR is a signature that determines the pass/fail result. The signature is typically sent
out via the TAP and then compared to a pre-calculated, or expected, signature.
54. Syntax for pattern matching.
Ans.
grep "string_to_match" input_file_name
or
command | grep "string"
55. what is awk ? Describe about in brief.
Ans.
Awk is kind of a text processing programming language, and can be used to manipulate text in
many ways. It can also be used for data processing from text files.
A simple 'awk' command can be run from the command line. More complex tasks should be
written as 'awk' program to a file, kind of a script file.
Awk Variables:
'awk' variables do not need to be declared before and also are independent of any data type.
Variable name should be started with a letter and can be continued with letters, digits,
underscores. Also variable name is case sensitive. Here are commonly used built-in variables:
~>NR: The current line's sequential number
~>NF: The number of fields in the current line
~>FS: The input field separator; which is set default to white space and can be reset by -F
command line parameter.
56. What is DFT? What is the requirement and What happens after DFT to the ckt?
- To add circuitary that allows designer to perform controlability and observability on every cell is
called
DFT. To determine the presence of faults in a given circuit.
The circuit becomes bulky as we include testing circuitry and get observable and controllable after
the manufacture.
57. What is Synthesis? Inputs and Outputs of synthesis. Libraries used in synthesis.
- Synthesis is the process to convert RTL in to GATE level netlist.
In other sense, Synthesis is the step of mapping RTL files to the targeted library cells and convert it
to the actual hardware.
Inputs RTL file, Constraints, Technology Library
Outputs Gate level Netlist
Libraries in synthesis are Synthetic lib, Symbol lib, link lib and Target library.
58. What happens if I replace the PMOS & NMOS in inverter? Yes it acts as a buffer but why
dont we use that buffer in circuit?
- Because if we put NMOS with Vcc, it will need more threshold, while the PMOS will be needing
less threshold. And hence we say, NMOS is good to pass logic 0 and PMOS is good to pass logic 1.
59. Extracting data using awk
- We can simply write awk '{print $1}' abc.txt (file name)
Where $1 will replace or $2 will represent the column of the file.
60. What is the reason we are shifting from MOSFET to FINFET?
- Because as the technology is shrinking, it is difficult to avoid short channel effects.
Like for e.g., below 24nm tech, the short channel effects goes uncontrollable, so we moved to
FINFET.
61. Difference between target library & link library
- Target library is basically used for mapping...while for link library we can say it is used for
resolving functional references.
62. What are the short channel effects?
- When in MOSFET, the channel length keeps on shrinking, few loses occurs between drain and
source terminals due to parasitic drain and source terminals. Hence we had to move for FINFET.
63. Difference between CMOS and FINFET
Ans. Structure wise difference:
CMOS structure:
FINFET 3D structure:
The traditional transistor takes significantly higher amount of power so the entire chipset will
consume a greater amount of power because a chipset contains billions of transistors. Due to this
high power consumption, the sustainability of the processor will decrease along with heat increase,
which is not desired. Talking about FinFET transistors, these will use standard drain and contacts so
it takes less power and expose less heat so the processor performance wont fall like the traditional
chip. This is the main reason; all the chip makers are interested in FinFET technology. There is
another important reason that is, FinFET transistors will take a lot less power at the stand-by time.
Advantages over planer MOSFET:
1.Higher transconductance (current out per voltage in)
2.Lower apparent input capacitance for the same gain
3.Less wafer area per transistor to get high gain, as the fin height can be increased in order to get
high gain
4.Fully depleted structure, enabling better on/off contrast
5.I-V curves get flatter, meaning lower dynamic power consumption.
6.Reducing short-channel effects by more effectively physically separating the source and drain
rather than letting them couple as a PNP or NPN structure beneath the channel
64. Perl Script (Email Assignmnet)
Ans.
In email assignment the task was that, there is one .xlxs perl doubt sheet that was on google drive
using perl script access that file and find the unanswered queries and then that unanswered queries
are sent by email to TA or student.
Following cpan modules are used:
Email::Send;
Email::Send::Gmail;
Email::Simple::Creator;
Email::Send::SMTP::Gmail;
Spreadsheet::Read;
then we installed google drive package to my pc and get access to google drive. After that we
downloaded that doubt sheet and read that file. To find unanswered queries we checked the column
of queries if there is no data in particular cell then that questions are unanswered. So we compared
with white-space and find out list of unanswered queries, then save to text file and that text had
been mailed to TA or Student.
Fanout : It defines the maximum number of gates which can be driven by driving gate.if output load
capacitance increases number of fanout increases so driving strength will increase.
67. lib files for DC tool and its contents
Ans.
Three types of lib files are there. 1) max lib 2) min lib and 3) Typical lib file.
These library file contain wire load model, default specifications, operating condition.
Max lib is for worst case scenario, min lib is for best case scenario and typical is for normal
scenario.
68. From lib file, which cell is taken by synthesis tool from the list of cells like AND2X1,
AND2X2, etc...
69. how to match two different pattern using grep command. Use only single grep command
Ans.
grep -e can match multiple pattern.
grep -e pattern1 -e pattern2 file_name
Synthesis is the step of mapping RTL files to the targeted library cells and convert it to the
actual hardware.
73. AWK to print a given particular column from the report generated in synthesis.
Ans. Report.txt
SIMULATION TIME : 2MS
VOLTAGE
: 3V
TEMPERATURE
: 25
Given the design complexity, manual generation of test vectors is time-consuming. Almost
IMPOSSIBLE.
So, we have tools to do it FastScan, TK, TetraMax etc..
are:
set_operating_conditions,
set_wire_load_model
and
What are scan chains: Scan chains are the elements in scan-based designs that are used to
shift-in and shift-out test data. A scan chain is formed by a number of flops connected back to
back in a chain with the output of one flop connected to another. The input of first flop is
connected to the input pin of the chip (called scan-in) from where scan data is fed. The output
of the last flop is connected to the output pin of the chip (called scan-out) which is used to take
the shifted data out. The figure below shows a scan chain.
A scan chain
Purpose of scan chains: As said above, scan chains are inserted into designs to shift the test data into
the chip and out of the chip. This is done in order to make every point in the chip controllable and
observable as discussed below.
How normal flop is transformed into a scan flop: The flops in the design have to be modified in order
to be put in the scan chains. To do so, the normal input (D) of the flip-flop has to be multiplexed with
the scan input. A signal called scan-enable is used to control which input will propagate to the output.
If scan-enable = 0, data at D pin of the flop will propagate to clock at the next active edge
If scan-enable= 1, data present at scan-in input will propagate to Q at the next active edge
Scan terminology: Before we talk further, it will be useful to know some signals used in scan chains
which are as follows:
Scan_in ->Input to the flop/scan-chain that is used to provide scan data into
Scan_out ->Output from flop/scan-chain that provides the scanned data to the next flop/output
Scan_enable ->Input to the flop that controls whether scan_in data or functional data will propagate to
output
Purpose of testing using scan: Scan testing is carried out for various reasons, two most prominent of them
are:
To test stuck-at faults in manufactured devices
To test the paths in the manufactured devices for delay; i.e. to test whether each path is working at
functional frequency or not
How a scan chain functions: The fundamental goal of scan chains is to make each node in the circuit
controllable and observable through limited number of patterns by providing a bypass path to each flipflop. Basically, it follows these steps:
1.Assert scan_enable (make it high) so as to enable (SI -> Q) path for each flop
2.Keep shifting in the scan data until the intended values at intended nodes are reached
3.De-assert scan_enable (for one pulse of clock in case of stuck-at testing and two or more
cycles in case of transition testing) to enable D->Q path so that the combinational cloud output
can be captured at the next clock edge.
4.Again assert scan_enable and shift out the data through scan_out
The PDF (How does scan work) provides a very good explanation to how scan chains function.
How Chain length is decided: By chain length, we mean the number of flip-flops in a single scan
chain. Larger the chain length, more the number of cycles required to shift the data in and out. However,
considering the number of flops remains same, smaller chain length means more number of input/output
ports is needed as scan_in and scan_out ports. As
Number of ports required = 2 X Number of scan chains
Since for each scan chain, scan_in and scan_out port is needed. Also,
Number of cycles required to run a pattern = Length of largest scan chain in design
Suppose, there are 10000 flops in the design and there are 6 ports available as input/output. This means
we can make (6/2=) 3 chains. If we make scan chains of 9000, 100 and 900 flops, it will be inefficient as
9000 cycles will be required to shift the data in and out. We need to distribute flops in scan chains
almost equally. If we make chain lengths as 3300, 3400 and 3300, the number of cycles required is
3400.
Keeping almost equal number of flops in each scan chain is referred to as chain balancing.
Fig.1 clocked scan replacement In normal operation, the system clock (sys_clk) clocks
system data (data) into the circuit and through to the output (Q). In scan mode, the scan clock
(sc_clk) clocks scan input data (sc_in) into the circuit and through to the output (sc_out).
81.What is Stuck-at Fault Models?
Ans:
The stuck-at-0 fault means a signal that is permanently low regardless of the other signals that
normally control the node, as shown in Figure 1. The stuck-at-1 fault represents a signal that is
permanently high regardless of the other signals that normally control the node. For example,
assume that you have a two-input AND gate that has stuck-at-0 fault on the output pin.
82. jagathi.txt and abc.txt which contains word jagathi .If we write egrep -r jagathi.txt then
what it returns?
A. then it searches the word jagathi in the text files and print them with the number of counts of
jagathi is found.
83. what if I consider $a= @a then print $a?
A. then it prints all the elements present in the @a.
84. I have a word like *- xxx jag xxx 123 in between of 10 lines then I need a command to find
and print this jag and 123?
A. then I need to print it with perl like /((\d+) (\w+) (\d+))/; so that it will identify the digits and
alphabets.
85. what is the command to find out the word in grep ?
A. grep -w word *
polysilicon, i.e., silicon formed from many small crystals. The middle layer is a very thin insulating film of SiO2 called the gate oxide. The bottom layer is the doped silicon body. The figure
shows a p-type body in which the carriers are holes. The body is grounded and a voltage is applied
to the gate. The gate oxide is a good insulator so almost zero current flows from the gate to the
body.
92. Explain cMOs iverter
ANS :
You can easily see that the CMOS circuit functions as an inverter by noting that when VIN is five
volts, VOUT is zero, and vice versa. Thus when you input a high you get a low and when you input
a low you get a high.
93. What is Latchup ?
ANS :
CMOS structure is a pair of parasitic bipolar transistors. The collector of each BJT is connected to
the base of the other transistor in a positive feedback structure.
A phenomenon called latchup can occur when:
(1) both BJT's conduct, creating a low resistance path between Vdd and GND and
(2) the product of the gains of the two transistors in the feedback loop, b1 x b2, is greater than one.
The result of latchup is at the minimum a circuit malfunction, and in the worst case, the destruction
of the device.
Latchup may begin when Vout drops below GND due to a noise spike or an improper circuit
hookup (Vout is the base of the lateral NPN Q2). If sufficient current flows through Rsub to turn on
Q2 (I Rsub > 0.7 V ), this will draw current through Rwell. If the voltage drop across Rwell is high
enough, Q1 will also turn on, and a self-sustaining low resistance path between the power rails is
formed.
If the gains are such that b1 x b2 > 1, latchup may occur.
Once latchup has begun, the only way to stop it is to reduce the current below a critical level,
usually by removing power from the circuit.
Preventing latchup:
1). Reduce the gain product b1 x b1
move n-well and n+ source/drain farther apart increases width of the base of Q2 and reduces
gain beta2 > also reduces circuit density
buried n+ layer in well reduces gain of Q1
2). Reduce the well and substrate resistances, producing lower voltage drops
higher substrate doping level reduces Rsub
reduce Rwell by making low resistance contact to GND
guard rings around p- and/or n-well, with frequent contacts to the rings, reduces the parasitic
resistances.
94. FSM sequence for 1011
Ans:
Hold Time:
The time required for the data to remain stable after the triggering clock edge.
So, hold check ensures that the path is not too fast so that data is not passed through.
How to remove
Setup & Hold
violations:
To solve setup violation
1. By optimizing and restructuring the combinational logic between the flops of design. In
big designs, we dont do this by ourselves, generally tool does this for us. And what are the
ways that tool follows for the same? We'll discuss that in next post.
2. By using Tweak flops to offer less setup delay. Since, Tweak launch-flop have better
slew at the clock pin and this makes CK->Q of launch flop faster, so that it helps in fixing
setup violations.
3. By using Useful- skews.
To solve Hold Violations
1. By adding delay/buffer cell. Since the simple buffer offers less delay, so we use special
Delay cells whose functionality remains same, i.e. Y=A, but with more delay.
2. By providing delay to the launch flop clock.
3. Where the hold time requirement is huge, we can use Lock-up Latches also.
96. Asynchronous D-FF veilog code
Ans : module dff_async_reset (data , clk ,reset,q);
input data, clk, reset ;
output q;
reg q;
always @ ( posedge clk or negedge reset)
if (~reset) begin
q <= 1'b0;
end else begin
q <= data;
end
endmodule
97. Synthesis steps in detail.
Ans : Synthesis is the process to convert RTL in to GATE level netlist.
(1)Translation
(2)Mapping
(3)Optimization
98. How many times DFT comes into the picture and when?
Ans : DFT will be done after synthesis and after manufacturing.
98. I/p of logic synthesis.
Ans: -----Requires inputs:
(1) RTL files.
(2) Synopsys Constraints file ,Design constraints file.
(3) Technology specific libraries.
-----Its Output :
Gate level netlist which is technology dependent.
103. Scan Chain Reordering:scan chain reordering is a process which is done in the physical
design to optimise the congestion while doing placement. When we do scan Stitching , we do not
have, resistor which are placed far from each other but getting stitched in same scan chain. Also
they may not be having any valid paths between them,functionally.hence physical design tool ,has
to route between these two far away FlipFlop just for scan purpose.But with scan reordering, the
physical design toolreordering the resistors in the chain bsed on the placement of them to reduce the
wire length.
104.From how many ways we can Extract perticular string from file?
Using linux command line
awk
sed
Using perl scripting
Split your report from : and put it into array
now apply regular expression for string which you want to find
print that element
TCL scripting
As I said split your file with repeatation character and make list
Apply regx and find string
print
105. What happen if we swap nmos amd pmos in circuit?
first if we swap nmos and pmos than we will not get exact 5v at output side.
second it will work as an inverter
From this we also know about why pmos pass strong 1 and nmos pass strong 0.
The FinFET technology is a technological breakthrough in recent years. It redefined the entire
chipset industry with newly implemented 3D transistors. Ok..here again, what is 3D transistor? The
traditional planar transistors contain Source and Drain parts, which separated by High K-Dielectric
surface. The entire power flow goes through Dielectric surface gate only. The 3D transistor drain
part raised like Fin structure in FinFET transistors, so these transistors are called FinFETs. Usually,
this kind of protruding parts will allow power to pass through all three parts at the same time. Also,
it will allow multiple transistors to share a common gate and common contacts so the ultimate
power supply consumption will significantly be reduced. Ok , so I will try to put it in simple words.
FinFET technology will allow chipset makers to build ultra-powerful processors, which only take a
little power when compared to traditional planar transistors.
111. huzaifa_ab.*/-_kapasi--Detect a pattern like this.
Ans. [w\]+\_ab\.\*\/\-\_[w\]+.
112.huzaifa.txt and abc.txt which contains word huzaifa.If we write egrep -r huzaifa.txt then
what it returns?
Ans. abc.txt:huzaifa
113.To print multiples of 5 till 10 using shell scripting
Ans. N=5
i=1
while [$i -lt 11]
do
echo " $n x $i = `expr $n \* $i`"
i=`expr $i + 1`
done
114. Display hashes according to key values
Ans.
foreach my $name (sort keys %planets) {
printf "%-8s %s\n", $name, $planets{$name};
}
115. Different methods to find the length of array
Ans.
@length = $#array1.
print scalar(@array1)
$length = @array
116. What is sensitivity list?what if we specify & for all the parameters inside it?
Ans.
117. Why we need to store the output values as reg?what if the output is not driving any load?
Ans.
Because in the always block it is not continuous assignment thus until the block is triggered
again we need to store the output values thus reg is required to be defined for every output
port.
If output is not driving any load then it will be floating,thus in that case also we need to store
it as reg.
Ans.
Initially a =3,b=5,c=8;
a=b;
b<= c;
c = a;
the output will be a=5, c= 5, b= 8;
Ans.10 Because TB is the top level module which is driving the DUT thus the ports that are input
for DUT are outputs of TB actually and the same goes for input ports.Thus we write ports as
opposite of each other in TB and DUT.
121.Cmos structure and characteristics of output voltage
Ans.
CMOS structure
Id vs Vd characteristics
122. What is threshold voltage?
Ans. It is the minimum voltage required to be applied to the device to turn it ON.
123.What is the impact of change in gate voltage on the device?
Ans. If the gate voltage decreases then the no. of electrons in case of nmos are less attracted as a
result weak channel is formed,thus current from drain to source will be less.
Ans. It is the process of converting RTL design to Gate level netlist so that it can be further done
for physical design of the required design.
125. What are the contents of .sdc files?
Ans. It describes the default values for input delay,output delay,clock latency,max transition,setting
input and output ports,multicycle path,etc.
126. Process of synthesis?
Ans. First the design file is read and then before compile it maps acc. To Gtech lib. And design
ware lib. And then constraints are given and then afte compilation it is mapped acc. To tech.
Lib. And then various reports are generated and checked whether DRC are violated or not.If
violated then constraints are changed and then reports are again generated until all DRC are
fixed.
127.What is dft why we need it and how it is done?
guest(virus) will not have any access to the system thus it is virus free while in windows to
install anything we need to run as administrator which does not require any password thus it
is not virus free.
Ans:
N=5
i=1
while [$i -lt 11]
do
echo " $n x $i = `expr $n \* $i`"
i=`expr $i + 1`
done
132. ls lrt
Ans:
ls for list command
l -list
r- reverse
t- time
133. Faviourite command of linux.
Ans:
cd ls pwd etc.
134. Command to check in which directory we are in vi editor
Ans:
pwd
135. How to go in previous directory using command
Ans:
cd 136. Find the word from zip file
Ans:
using zgrep command
137. Syntex grep command.
Ans:
grep 'word' inputfile name
138. Difference in hash and array.
Ans:
Arrays are ordered, integer-indexed collections of any object. Array indexing starts at 0, as in C or
Java. A negative index is assumed to be relative to the end of the arraythat is, an index of -1
indicates the last element of the array, -2 is the next to last element in the array, and so on.
A Hash is a collection of key-value pairs. It is similar to an Array, except that indexing is done via
arbitrary keys of any object type, not an integer index. Hashes enumerate their values in the order
that the corresponding keys were inserted.
Hashes have a default value that is returned when accessing keys that do not exist in the hash. By
default, that value is nil
139. If I print 5 times hash and five times array what will be the difference in the output
Ans:
thre will be no change in output.
140. Sorting of a hash in alphabetic orde
Ans:
foreach my $name (sort keys %planets) {
printf "%-8s %s\n", $name, $planets{$name};
}
this syntax will give sorted values.
141. Difference in a and $a
Ans:
a is used to define the variable and $a will be used to fetch the value which is stored in that variable.
142. 3 ways to print how many values are there in any array.
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my @arr = (2);
print scalar @arr;
my $arrSize = @arr;
print $arrSize;
my @planets = qw(mercury venus earth mars jupiter);
my $size = $#planets + 1;
print "$size\n";
143. Difference of mealy and moore.
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chomp removes the last new line character.
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Synchronous Reset
A synchronous reset signal will only affect or reset the state of the flip-flop on the active edge of the
clock. The reset signal is applied as is any other input to the state machine.
Asynchronous Reset
An asynchronous reset will affect or reset the state of the flip-flop asynchronously i.e. no matter
what the clock signal is. This is considered as high priority signal and system reset happens as soon
as the reset assertion is detected.
146. How cmos characteristics and when pinch off occure Id equation at pinchoff.
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Pinch of will take place when vds and more then vdsat. And very small amount of current will pass.
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For simplicity , it is assumed that the source and the bulk of the transistor are tied together , but in
reality it is not.
It is one of the Second-Order effects in analysis of a mosfet.
The voltage difference between the source and bulk(substrate) (Vsb) affects Vth of transistor.
And in order to see the body effect in transistor you have to add a current source in the drain of the
small signal model of a mosfet.it is parallel with ro resistor and gm*Vin current source. and its
value is gmb*Vbs.
148. Application of Shebang line in shell scripting
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The #! syntax used in scripts to indicate an interpreter for execution under UNIX / Linux operating
systems.
149. Explain nand2 or nor2 cmos.
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Architectural optimization
arithmetic
resource sharing
design ware implementation
gate level optimization
area optimization
time optimization
logic optimization
structuring
flattening
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Design rule constraints
max tansition
max/min capacitance
fanout
Optimization constraints
max area
max timing
152. Types of leakage current in CMOS explain all currents.
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Subthreshold conduction when the transistors are off
Tunnelling current through gate oxide
Leakage current through reverse-biased diodes
153. Initial block is synthesizable or not?
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It is not synthesizable.