SRI VIVEKA INSTITUTE OF TECHNOLOGY

MADALAVARIGUDAM, KRISHNA Dt.

Department of Electronics and communication Engineering
FIRST SEMESTER 2010-11
Course Handout
Date: 14.06.2010
Course Title Digital IC Applications

1. Course description: In this course, the fundamental concepts involved in Hardware description Language for
Digital ICs will be discussed. The course coverage includes a wide range of topics such as functions of Digital ICs,
Hardware description language of ICs, VHDL coding of all ICs, component model, different models of VHDL,
behavioral modeling, structural modeling of VHDL, Design of FPGA implementations, CPLD modeling including
RAM and ROM modeling.

2.Scope and Objective of the course: The need of the hour in the world nowadays is optimized electronic gadgets.
The main objective of this subject is to design electronic circuits in a single chip. This is the fundamental concept to be
used in VLSI design which is most widely used technology in electronic IC fabrication.

2. Textbooks:
T1. 1. Digital Design Principles & Practices – John F. Wakerly, PHI/ Pearson Education Asia, 3rd Ed., 2005.
T2. 2. VHDL Primer – J. Bhasker, Pearson Education/ PHI,3rd Edition.

4. Reference books:
R1. Digital System Design Using VHDL – Charles H. Roth Jr., PWS Publications,1998.
R2. Introduction to Logic Design – Alan B. Marcovitz,TMH,2nd Edition,2005.
R3. Fundamentals of Digital Logic with Verilog Design – Stephen Brown, Zvonko Vransesic, TMH, 2003.
R4. Cypress Semiconductors Data Book(Download from website).
R5. Fundamentals of Digital Logic with VHDL Design – Stephen Borwn and Zvonko Vramesic, McGraw
Hill,2nd Edition.,2005.
R6. Linear Integrated Circuit Applications by K. Lal kishore, Pearson Educations 2005

5.Course Plan:
Lec. Learning Objectives Topics to be covered References
No.
1-5 CMOS LOGIC : logic Introduction to logic families, CMOS logic, CMOS steady Ch.1 of T1 &
families, CMOS logic, state electrical behavior, CMOS T2; Ch. 5 of
dynamic electrical behavior dynamic electrical behavior, CMOS logic families. T1; Ch. 6 of
T1; Ch. 8 of T2
6-11 BIPOLAR LOGIC AND Bipolar logic, Transistor logic, TTL families, CMOS/TTL Ch. 7 of T1;
INTERFACING interfacing, Ch.9 & 10 of
low voltage CMOS logic and interfacing, Emitter coupled T2
logic, Comparison of logic families, Familiarity with
standard 74XX and CMOS 40XX series-ICs –
Specifications.
11-18 THE VHDL HARDWARE Design flow, program structure, types and constants, Ch 8-11 of T1
DESCRIPTION functions and procedures, libraries and packages.
LANGUAGE
19-25 THE VHDL DESIGN Structural design elements, data flow design elements, Ch. 11-15 of T2
ELEMENTS behavioral design
elements, time dimension and simulation synthesis.
23-30 COMBINATIONAL Decoders, encoders, three state devices, multiplexers and Ch. 16 of T2
LOGIC DESIGN demultiplexers, Code Converters, EX-OR gates and parity
 circuits, comparators, adders & subtractors, ALUs,
Combinational multipliers. VHDL modes for the above
ICs.
30-36 UNIT VI Design examples (using VHDL) - Barrel shifter, Ch-18 of T2;
DESIGN EXAMPLES comparators, floatingpoint Ch. 11 of T1
(USING VHDL) encoder, dual parity encoder.
36-40 SEQUENTIAL LOGIC Latches and flip-flops, PLDs, counters, shift register, and Ch. 6 of T2;
DESIGN their VHDL models, Ch. 16 of T1
synchronous design methodology, impediments to
synchronous design.
40-45 MEMORIES : ROMs Internal structure, 2D-decoding commercial types, timing Ch. 6 of T2;
Dynamic RAM and applications. Static RAM: Ch. 16 of T1
Cypress CY6116,CY7C1006, Specifications.

6. Assignments: Comprises of Reading and/or Home assignments. Details will be announced in the class from time to
time and also will be uploaded in college website.

7.Evaluation scheme
EC Evaluation Duration Marks Date Time Venue
No Component minutes
MID-I Descriptive-1 90 10 Will be Announced later
Internal Quiz-1 30 2
Open Book Tests 30 2 (each) Continuous ---
(at the end of each =
unit) 4x2=8M
Online Quiz-1 20 20 Will be Announced later

MID-II Descriptive-2 90 10 Will be Announced later

Internal Quiz-2 30 2
Open Book Tests 30 2 (each) Continuous
(at the end of each =
unit) 4x2=8M
Online Quiz -2 20 20 Will be Announced later

08. Notices: Concerning the course will be displayed on Department Notice Board.

INSTRUCTOR-IN-CHARGE