Digital Image

Processing
System Analysis
 Digital Image Processing Data Flow
Source File Input transport
- RGB - MPEG,
JPEG, etc. - External: USB 2.0, IEEE-1394, Home Networking options, etc.
- Internal: IDE, LVDS, AGP, PCI, FLASH, SDRAM, etc.

Decoding DCT/IDCT, color space conversion, decryption, etc.

(Decompress/decrypt)
Raw
RGB
Image Scaling, gamma/color correction, dithering,
Processing brightness, contrast, sharpness, etc.
(Image adjustment)

Adjusted RGB

Encoding DCT/IDCT, color space conversion, encryption, etc.

(Compress/encrypt)
Output transport
- External: USB 2.0, IEEE-1394, Home Networking options, etc.
- Internal: IDE, LVDS, AGP, PCI, etc.
 Generic Digital Image
Processing System

Optional
Frame Buffer
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 Digital Data Input
Digital Input
- MPEG
- JPEG
- TIFF
Optional - RGB
Frame Buffer - Etc.
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

Digital Transport Options
Digital Transport
- IEEE-1394
- USB 2.0
- Ethernet
Optional - LVDS/BLVDS
Frame Buffer - Etc.
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 Digital Decoding
Digital Decoder
- MPEG
- TIFF
- Etc.
Optional Content Protection
Frame Buffer
RAM
- Decryption

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

Supervision and Control
Supervisory Control
- User interface
- Graphic menus
- LEDs
- Buttons
Optional
- Etc.
Frame Buffer
RAM - System control

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 Image Processing
Image Processing
- Scaling
- Color correction
- Image enhancement
Optional
Frame Buffer - Etc.
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

Memory and Sub-System
Interfaces
Memory and Sub-
system Interfaces
- ROM
- SRAM
Optional - SDRAM
Frame Buffer - etc
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

Optional Digital Encoding
Optional Digital Encoder
- MPEG
- TIFF
- Etc.
Optional Content Protection
Frame Buffer
RAM
- Encryption

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

Output Transport Options
Digital Transport
- IEEE-1394
- USB 2.0
- Ethernet
Optional - LVDS/BLVDS
Frame Buffer - Etc.
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 Digital Data Output
Digital Output
- MPEG
- JPEG
- TIFF
Optional - RGB
Frame Buffer - Etc.
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 Image Processing
System Design Challenges
• Component interconnectivity
– How do you integrate the best components to address your application?
• Image processing
– How do you meet the performance challenge? How do you maintain
compatibility with geographically divergent and continuously evolving
formats and standards?
• Encoding/Decoding
– How can you deal with the myriad of evolving formats and standards?
• Content protection
– How can you make and keep your product compatible with the wide
diversity of protection schemes emerging among the content providers?
• System control
– How do you control the system?
 Programmable Logic Utility
Where FPGAs Can Add Value
Optional
Frame Buffer
RAM

Digital Digital RGB Image Digital RGB Digital

PHY
PHY PHY
Input Processing Output

Optional
Optional Optional
Optional
Digital
Digital Digital
Digital
Decode
Decode uC Encode
Decode
Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 System Connectivity
Where FPGAs Can Add Value
External Transport MACs
- USB 2.0, 1394, Ethernet
System Level Interfaces
- LVDS/BLVDS
Optional - PCI
Frame Buffer
RAM
- Etc.

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Decode
Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

Component Interconnectivity
Where FPGAs Can Add Value
Connectivity
- System I/O with support for
19 signaling standards
Optional
Block & distributed RAM
Frame Buffer - For buffers and FIFOs
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Optional
Digital Digital
Digital
Decode uC Decode
Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

Digital Format Encoding/Decoding
Where FPGAs Can Add Value
Digital En/decode IP
- JPEG
- DCT/IDCT (MPEG)
- Error correction
Optional En/decryption IP
Frame Buffer
RAM
- DES, TDES, AES, etc.

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Decode
Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 System Control
Where FPGAs Can Add Value
System Control IP
- 32-bit uP
- 8-bit uC
Optional
Frame Buffer
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Decode
Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 High Performance Image
Processing Where FPGAs Can Add
Value Image Processing IP
and
- Color space converters
- Dozens of DSP building
Optional blocks (FFT, FIR, etc.)
Frame Buffer
RAM - MATLAB TM development

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Decode
Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

Memory Subsystem Control
Where FPGAs Can Add Value
Memory Controller IP
- ROM
- FLASH
- SRAM
Optional - SDRAM/DDR SDRAM
Frame Buffer - Etc.
RAM

Digital Digital RGB Image Digital RGB Digital

PHY PHY
Input Processing Output

Optional Optional
Digital Digital
Decode uC Decode
Encode

Digital Memory Mixed Signal uP or uC Programmable IP Block

 Image Processing
System Design Challenge
Digital
Output
FPGA Image Processing Clock
System Utility Mgmt
PHY
Image Processing
SDRAM

User Designed I/O

Sub-System Controllers
Optional

Sub-System I/O
Digital SRAM
Decode

System FLASH
Buffers / Memories
PHY Control
Hard
Encoding/Decoding Disk
Encryption/Decryption
Digital
input

Digital Memory Mixed Signal uP or uC Programmable IP Block

 FPGA Standard Features and IP
Accelerating Time-to-Market
Digital
Output
FPGA Image Processing Clock
DLL DLL

System Utility Mgmt

DLL DLL
PHY
Image Processing 2D FFT

Controller
SDRAM
2D FIR Filter
SDRAM

I/O I/O

Controllers
YCrCb2RGB

Designed
Optional RGB2YCrCb

System I/O I/O

Controller
Digital

SRAM
RGB2YUV SRAM
System
En/decode

Sub-System
YUV2RGB

Sub-System
User

Controller
FLASH
System
uC Block RAM FLASH
BuffersDistributed
/ Memories
PHY Control RAM

Controller
Hard
DCT Encoding/Decoding
DES AES

EIDE
Disk
JPEG
IDCT Encryption/Decryption
3DES
Digital
input

Digital Memory Mixed Signal uP or uC Programmable IP Block

 Standard System I/O
Features
• LVDS, BLVDS (Spartan- • HSTL I, III, & IV
IIE) • SSTL3 I & II
• LVTTL • SSTL2 I & II
• LVCMOS2 • CTT
• LVCMOS18 • AGP-2X
• PCI 33/66 • LVPECL (Spartan-IIE)
• GTL, GTL+
 Memory Controller IP
• Content Addressable • Registered ROM
Memory (CAM) • Dual-port Block Memory
• DDR-SDRAM Controller • 200MHz ZBT SRAM
• Quad-Data-Rate SRAM Interface
Interface • SDRAM Controller
• Single-Port Block
Memory
• Registered single port
RAM
 MicroBlaze
• 32-bit fully synthesized RISC processor
• Fast
– Twice the performance at half the logic area vs. competition
• Supported by an integrated IP library
— Timer/Counter Block — IIC*
— Watchdog Timer/Timebase — SPI*
— Interrupt Controller — Ethernet 10/100 MAC*
— 16550/16450/Lite UART — More to come
— ZBT Memory Controller
— SRAM Controller
— Flash Memory Controller

* Licensed for a fee

 Xtreme DSP
• Industry first System Generator for Simulink® bridges gap between
FPGA and conventional DSP design flows
• Unique constraint-driven Filter Generator allows optimization
between performance and cost
• Power estimator tool (Xpower™) for power-sensitive DSP
implementations
• Eleven optimized DSP algorithms (cores) that cut development
time by weeks
• DSP features added to ChipScope ILA tool dramatically accelerate
hardware debugging time

* Licensed for a fee

Content Protection Solutions
• Xilinx encryption solutions are NIST approved
• The programmable nature of these solutions allows easy
customization based on end application requirement
Spartan-IIE Implementation Examples

Note: Solution includes encry ption, decryption and key generation

* 128-bit key im plementation
** Key Generation offloaded to embeddedµC/ µP
 Video/Image Processing IP
• Inverse Discrete Cosine • logiCVC - Compact Video
Transform (IDCT) Controller
• 1-D Discrete Cosine • RGB2YCrCb Color Space
Transform Converter
• 2-D DCT/IDCT Forward & • YCrCb2RGB Color Space
Inverse Discrete Cosine Converter
Transform • RGB2YUV Color Space
• JPEG CODEC Converter
• FastJPEG Color Decoder • YUV2RGB Color Space
• Fast JPEG B/W Decoder Converter