11AK46 Full TV+DVD SCH+SM 66p

CONTENTS
SAFETY PRECAUTIONS:................................................................................................................................................................ 2
• TV set switched off........................................................................................................................ 2
• Measurements ............................................................................................................................... 2
PERI-TV SOCKET.............................................................................................................................................................................. 2
• SCART 1 ......................................................................................................................................... 2
1. INTRODUCTION ........................................................................................................................................................................... 3
2. SMALL SIGNAL PART WITH STV2248 .................................................................................... 3
• 2.1 Vision IF amplifier...................................................................................................................................................................3
• 2.2 QSS Sound circuit (QSS versions).......................................................................................................................................3
• 2.3 AM demodulator ...................................................................................................................................................................3
• 2.4 FM demodulator ....................................................................................................................................................................3
• 2.5 Video switch............................................................................................................................................................................4
• 2.6 Synchronisation circuit..........................................................................................................................................................4
• 2.7 Chroma and luminance processing......................................................................................................................................4
• 2.8 RGB output circuit ..................................................................................................................................................................5
• 2.9 µ-Controller................................................................................................................................. 6
3. TUNER.............................................................................................................................................................................................. 6
5. SOUND OUTPUT STAGE TDA7496.......................................................................................................................................... 7
6. VERTICAL OUTPUT STAGE WITH TDA8174A.................................................................................................................... 7
7. VIDEO OUTPUT AMPLIFIER STV5114................................................................................................................................... 7
8. POWER SUPPLY (SMPS)............................................................................................................................................................ 7
10. SERIAL ACCESS CMOS 8K EEPROM 24C08..................................................................................................................... 7
12. SAW FILTERS ............................................................................................................................................................................. 7
13. IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM................................................................................................ 8
• ST92195.........................................................................................................................................................................................8
• STV224X .....................................................................................................................................................................................10
• UV1316, UV1336.........................................................................................................................................................................11
• TDA7496.....................................................................................................................................................................................12
• TDA8174.....................................................................................................................................................................................13
• STV5114 ......................................................................................................................................................................................13
• MC44608 .....................................................................................................................................................................................14
• 24CO8 ..........................................................................................................................................................................................15
• SAW FILTERS...........................................................................................................................................................................16
GENERAL BLOCK DIAGRAM of 11AK46.................................................................................................................................17
Service menu ....................................................................................................................................................................................18
Options................................................................................................................................................................................................19
Languages ..........................................................................................................................................................................................22
“1 1
DO NOT CHANGE ANY MODULE UNLESS THE SET IS SWITCHED OFF
The mains supply part of the switch mode power supply’s transformer is live.
Use an isolating transformer.
The receiver complies with the safety requirements.
SAFETY PRECAUTIONS:
The service of this TV set must be carried out by qualified persons only. Components marked
with the warning symbol on the circuit diagram are critical for safety and must only be replaced with an
identical component.
- Power resistor and fused resistors must be mounted in an identical manner to the original component.
- When servicing this TV, check that the EHT does not exceed 26kV.
TV set switched off:
Make short-circuit between HV-CRT clip and CRT ground layer.
Short C809 before changing IC800 or other components in primary side of the SMPS part.
Measurements:
Voltage readings and oscilloscope traces are measured under the following conditions:
Antenna signal’s level is 60dB at the color bar pattern from the TV pattern generator. (100% white, 75%
color saturation)
Brightness, contrast, and color are adjusted for normal picture performance.
Mains supply, 220VAC, 50Hz.
PERI-TV SOCKET
- The figure of PERI-TV socket-
SCART 1 PINING
1 Audio right output 0.5Vrms / 1K

2 Audio right input 0.5Vrms / 10K
3 Audio left output 0.5Vrms / 1K
4 Ground AF
5 Ground Blue
6 Audio left input 0.5Vrms / 10K
7 Blue input 0.7Vpp / 75ohm
8 AV switching input 0-12VDC /10K
9 Ground Green
10 -
11 Green input 0.7Vpp / 75ohm
12 -
13 Ground Red
14 Ground Blanking
15 Red input 0.7Vpp / 75ohm
16 Blanking input 0-0.4VDC, 1-3VDC / 75 Ohm
17 Ground CVBS output
18 Ground CVBS input
“1 2
19 CVBS output 1Vpp / 75ohm
20 CVBS input 1Vpp / 75ohm
21 Ground
1. INTRODUCTION
11AK46 is a 90° chassis capable of driving 14” tubes at the appropriate currents. The chassis is capable
of operating in PAL, SECAM and NTSC standards. The sound system is capable of giving 3,5 watt
RMS output into a load of 8 ohms. One page, 7 page SIMPLETEXT, TOPTEXT, FASTTEXT and US
Closed Caption is also provided. The chassis is equipped with a 42 pin Scart connector.
2. SMALL SIGNAL PART WITH STV2248:
STV2248 video processor is essential for realizing all small signal functions for a color TV receiver.
2.1 Vision IF amplifier3

The vision IF amplifier can demodulate signals with positive and negative modulation. The PLL
demodulator is completely alignment-free. Although the VCO (Toko-coil) of the PLL circuit is external,
yet the frequency is fixed to the required value by the original manufacturer thus the Toko-coil does not
need to be adjusted manually. The setting of the various frequencies (38.9 or 45.75 MHz) can be made
via changing the coil itself.
2.2 QSS Sound circuit (QSS versions)

The sound IF amplifier is similar to the vision IF amplifier and has an external AGC de-coupling capacitor.
The single reference QSS mixer is realised by a multiplier. In this multiplier the SIF signal is converted to
the inter-carrier frequency by mixing it with the regenerated picture carrier from the VCO. The mixer
output signal is supplied to the output via a high-pass filter for attenuation of the residual video signals.
With this system a high performance hi-fi stereo sound processing can be achieved. The AM sound
demodulator is realised by a multiplier. The modulated sound IF signal is multiplied in phase with the
limited SIF signal. The demodulator output signal is supplied to the output via a low-pass filter for
attenuation of the carrier harmonics. The AM signal is supplied to the output via the volume control.
2.3 AM DEMODULATOR
The AM demodulated signal results from multiplying the input signal by itself, it is available on
AM/FM output.
2.4 FM demodulator and audio amplifier :

The FM demodulator is realized as narrow-band PLL with external loop filter, which provides the
necessary selectivity without using an external band-pass filter. To obtain a good selectivity a linear phase
detector and constant input signal amplitude are required. For this reason the inter-carrier signal is
internally supplied to the demodulator via a gain controlled amplifier and AGC circuit. The nominal
frequency of the demodulator is tuned to the required frequency (4.5/5.5/6.0/6.5 MHz) by means of a
calibration circuit that uses the clock frequency of the µ-controller/Teletext decoder as a reference. The
setting to the wanted frequency is realized by means of the software. It can be read whether the PLL
frequency is inside or outside the window and whether the PLL is in lock or not. With this information it is
possible to make an automatic search system for the incoming sound frequency. This is realized by means
“1 3
of a software loop that alternate the demodulator to various frequencies, then select the frequency on
which a lock condition has been found. De-emphasis output signal amplitude is independent of the TV
standard and has the same value for a frequency deviation of ±25 kHz at the 4.5 MHz standard and for a
deviation of ±50 kHz for the other standards. When the IF circuit is switched to positive modulation the
internal signal on de-emphasis pin is automatically muted. The audio control circuit contains an audio
switch and volume control. In the mono inter-carrier sound versions the Automatic Volume Leveling
(AVL) function can be activated. The pin to which the external capacitor has to be connected depends on
the IC version. For the 90° types the capacitor is connected to the EW output pin (pin 20). When the
AVL is active it automatically stabilizes the audio output signal to a certain level.
2.5 Video switching

The video processor (STV2248C) has three CVBS inputs and two RGB inputs. The first CVBS input is
used for external CVBS from SCART 1, the second is used for either CVBS or Y/C from BAV/FAV,
and the third one is used for internal video. The selection between both external video inputs signals is
realized by means of software and hardware switches.
2.6 Synchronization circuit

The video processor (STV224X) performs the horizontal and vertical processing. The external horizontal
deflection circuit is controlled via the Horizontal output pulse (HOUT). The vertical scanning is performed
through an external ramp generator and a vertical power amplifier IC controlled by the Vertical output
pulse (VOUT).
The main components of the deflection circuit are:
• PLL1: the first phase locked loop that locks the internal line frequency reference on the
CVBS input signal. It is composed of an integrated VCO (12 MHz) that requires the chroma
Reference frequency (4.43MHz or 3.58MHz crystal oscillator reference signal), a divider by
768, a line decoder, and a phase comparator.
• PLL2: The second phase locked loop that controls the phase of the horizontal output
(Compensation of horizontal deflection transistor storage time variation). Also the horizontal position
adjustment is also performed in PLL2.
• A vertical pulse extractor.
• A vertical countdown system to generate all vertical windows (vertical synchronization window, frame
blanking pulses, 50/60Hz identification window...).
• Automatic identification of 50/60Hz scanning.
• PLL1 time constant control.
• Noise detector, video identification circuits, and horizontal coincidence detector.
• Vertical output stage including de-interlace function, vertical position control.
• Vertical amplitude control voltage output (combined with chroma reference output and
Xtal 1 indication).
2.7 Chroma and luminance processing:

The chroma decoder is able to demodulate PAL, NTSC and SECAM signals.
The decoder dedicated to PAL and NTSC sub-carrier is based on a synchronous demodulator, and an
Xtal PLL locked on the phase reference signal (burst).
The SECAM demodulation is based on a PLL with automatic calibration loop.
The color standard identification is based on the burst recognition.
Automatic and forced modes can be selected through the I2C bus.
“1 4
NTSC tint, and auto flesh are controlled through I2C bus.
Xtal PLL can handle up to 3 crystals to work in PAL M, PAL N and NTSC M for South America.
ACC an ACC overload control the chroma sub-carrier amplitude within 26dB range. Both
ACC s are based on digital systems and do not need external capacitor.
All chroma filters are fully integrated and tuned via a PLL locked on Xtal VCO signal.
A second PLL is used for accurate fine-tuning of the SECAM bell filter. This tuning is achieved during the
frame blanking. An external capacitor memorizes the bell filter tuning voltage.
A base-band chroma delay-line rebuilds the missing color line in SECAM and removes transmission
phase errors in PAL.
The base-band chroma delay line is clocked with 6MHz signal provided by the horizontal scanning VCO.
The luminance processor is composed of a chroma trap filter, a luminance delay line, a peaking function
with noise coring feature, a black stretch circuit.
Trap filter and luminance delay lines are achieved with the use of bi-quad integrated filters, auto-aligned
via a master filter phase locked loop.
2.8 RGB output circuit:

The video processor performs the R, G, B processing.
There are three sources:
1. Y,U,V inputs (coming from luma part (Y output), and chroma decoder outputs (R-Y, B-Y outputs).
2. External R,G,B inputs from SCART (converted internally in Y,U,V), with also the possibility to input
YUV signals from a DVD player, (YUV specification is Y=0.7 V PP , U= 0.7 V PP , V = 0.7V PP for
100% color bar).
3. Internal R,G,B inputs (for OSD and Teletext display)
The main functions of the video part are:

- Y,U,V inputs with integrated clamp loop, allowing a DC link with YUV outputs,
- External RGB inputs (RGB to YUV conversion), or direct YUV inputs,
- Y,U,V switches,
- Contrast, saturation, brightness controls,
- YUV to RGB matrix,
- OSD RGB input stages (with contrast control),
- RGB switches,
- APR function,
- DC adjustment of red and green channels,
- Drive adjustments (R, G, B gain),
- Digital automatic cut-off loop control,
- Manual cut-off capability with I2C adjustments,
- Half tone, oversize blanking, external insertion detection, blue screen,
- Blanking control and RGB output stages.
“1 5
2.9 µ-Controller
The ST92195 is the micro-controller, which is required for a color TV receiver. ST92195D1 is the
version with one page Teletext and ST92195D7 is the one with 7 page Teletext. The IC has the supply
voltages of 5 V and they are mounted in PSDIP package with 56 pins.
µ-Controller has the following features
• Display of the program number, channel number, TV Standard, analogue values, sleep timer, parental
control and mute is done by OSD
• Single LED for standby and on mode indication
• System configuration with service mode
• 3 level logic output for SECAM and Tuner band switching
3. TUNER
PLL tuner is used as a tuner.
Channel coverage of UV1316:
OFF-AIR CHANNELS CABLE CHANNELS

BAND CHANNELS FREQUENCY CHANNELS FREQUENCY
RANGE (MHz) RANGE (MHz)
Low Band E2 to C 48.25 to 82.25 (1) S01 to S08 69.25 to 154.25
Mid Band E5 to E12 175.25 to 224.25 S09 to S38 161.25 to 439.25
High Band E21 to E69 471.25 to 855.25 (2) S39 to S41 447.25 to 463.25
(1). Enough margin is available to tune down to 45.25 MHz.

(2). Enough margin is available to tune up to 863.25 MHz.
Noise Typical Max. Gain Min. Typical Max.

Low band : 5dB 9dB All channels : 38dB 44dB 52dB
Mid band : 5dB 9dB Gain Taper (of-air channels): 8dB
High band : 6dB 9dB
“1 6
Channel Coverage UV1336:
BAND CHANNELS FREQUENCY

RANGE (MHz)
Low Band 2 to D 55.25 to 139.25
Mid Band E to PP 145.25 to 391.25
High Band QQ to 69 397.25 to 801.25
Noise is typically 6dB for all channels. Gain is minimum 38dB and maximum 50dB for all channels.
5. SOUND OUTPUT STAGE TDA7496

TDA7496 is used as the AF output stereo amplifier . It is supplied by +20 VDC coming from a separate
winding in the SMPS transformer. An output power of 3.5W (THD=0.5%) can be delivered into an
8ohm load.
6. VERTICAL OUTPUT STAGE WITH TDA8174A

The TDA8174A is a power amplifier circuit for use in 90° and 110° colour deflection systems for 25 to
200 Hz field frequencies, and for 4: 3 and 16: 9 picture tubes.
7. VIDEO OUTPUT DISCRETE AMPLIFIERS

There are three monolithic video output amplifiers. Each amplifier consist of two transistors which are
TR_2SC2482 and BF421.
8. POWER SUPPLY (SMPS)

The DC voltages required at various parts of the chassis are provided by an SMPS transformer
controlled by the IC MC44608 which is designed for driving, controlling and protecting switching
transistor of SMPS. The transformer produces 115V for FBT input, ±14V for audio output IC, S+3.3,
S+5V and 8V for ST92195.
10. SERIAL ACCESS CMOS 8K EEPROM 24C08

The 24C08 is a 8Kbit electrically erasable programmable memory (EEPROM), organized as 4 blocks of
256*08 bits. The memory is compatible with the I²C standard, two wire serial interface which uses a bi-
directional data bus and serial clock.
12. SAW FILTERS
Saw filter type: Model:

-66M: PAL SECAM B/G/D/K/I MONO
J1981 : PAL-I MONO
K2958M: PAL-SECAM B/G-D/K (38) MONO
L9653M: SECAM L/L’ AM MONO (AUDIO IF)
G3967M: PAL-SECAM B/G STEREO (VIDEO IF)
G9353M: PAL-SECAM B/G STEREO (AUDIO IF)
K3958M: PAL-SECAM B/G/D/K/I/L/L’ STEREO (VIDEO IF)
K9356M: PAL-SECAM B/G/D/K/I STEREO (AUDIO IF)
“1 7
K9656M: PAL-SECAM B/G/D/K/I/L/L’ STEREO (AUDIO IF)
K3958M: PAL I NICAM (VIDEO IF)
K9356M: PAL I NICAM (AUDIO IF)
M1962M: PAL M/N NTSC M MONO
M3953M: PAL M/N NTSC M STEREO (VIDEO IF)
M9370M: PAL M/N NTSC M STEREO (AUDIO IF)
IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM
• ST92195
• STV224X
• TUNER (UV1316, UV1336)
• TDA7496L
• TDA8174A
• STV5114
• MC44608
• 24C08
• SAW FILTERS
G1975M, K2966M, K2962M, L9653M, G3962M, G9353M, K3958M, K9356M, K9656M,
K6263K, K9652M,
M1962M, M3953M, M9370M
ST92195
The ST92195 is a member of the ST9+ family of micro-controllers, completely developed and produced
by SGS-THOMSON Microelectronics using a proprietary n-well HCMOS process. The nucleus of the
ST92195 is the advanced Core, which includes the Central Processing Unit (CPU), the ALU, the
Register File and the interrupt controller. The Core has independent memory and register buses to add to
the efficiency of the code. A set of on-chip peripherals form a complete sys-tem for TV set and VCR
applications:
– Voltage Synthesis
– VPS/WSS Slicer
– Teletext Slicer
– Teletext Display RAM
– OSD
Additional peripherals include a watchdog timer , a serial peripheral interface (SPI), a 16-bit timer and
an A/D converter.
“1 8
“1 9
STV224X Video processor:
The STV2246/2247/2248 are fully bus controlled ICs for TV including PIF, SIF, luma, Chroma and
deflection processing. Used with a vertical frame booster (TDA1771 or TDA8174 for 90° chassis,
STV9306 for 110° chassis), they allow the design of multi-standard (BGDKIMNLL, PAL/
SECAM/NTSC) sets with very few external components and no manual adjustments.
“1 10
UV1316, UV1336
General description of UV1316:

The UV1316 tuner belongs to the UV 1300 family of tuners, which are designed to meet a wide range of
applications. It is a combined VHF, UHF tuner suitable for CCIR systems B/G, H, L, L’, I and I’.
Features of UV1316:
• Member of the UV1300 family small sized UHF/VHF tuners
• Systems CCIR: B/G, H, L, L’, I and I’; OIRT: D/K
• Digitally controlled (PLL) tuning via I²C-bus
• Off-air channels, S-cable channels and Hyper-band
• World standardized mechanical dimensions and world standard pinning
• Complies to “CENELEC EN55020” and “EN55013”
PINNING PIN VALUE
1. Gain control voltage (AGC) :4.0V, Max:4.5V

2. Tuning voltage
3. I²C-bus address select :Max:5.5V
4. I²C-bus serial clock :Min:-0.3V, Max:5.5V
5. I²C-bus serial data :Min:-0.3V, Max:5.5V
6. Not connected
7. PLL supply voltage :5.0V, Min:4.75V, Max:5.5V
8. ADC input
9. Tuner supply voltage :33V, Min:30V, Max:35V
10. Symmetrical IF output 1
11. Symmetrical IF output 2
General description of UV1336:

UV1336 series is developed for reception of channels broadcast in accordance with the M, N standard.
Features of UV1336:
• Global standard pinning
• Integrated Mixer-Oscillator & PLL function
• Conforms to CISPR 13, FCC and DOC (Canada) regulations
• Low power consumption
• Both Phono connector and ‘F’ connector are available
“1 11
PINNING PIN VALUE
1. Gain control voltage :4.0V, Max:4.5V

2. Tuning voltage
3. Address select Max:5.5V
4. Serial clock :Min:-0.3V, Max:5.5V
5. Serial data :Min:-0.3V, Max:5.5V
6. Not connected
7. Supply voltage :5.0V, Min:4.75V, Max:5.5V
8. ADC input (optional)
9. Tuning supply voltage :33V, Min:30V, Max:35V
10. Ground
11. IF output
TDA7496
DESCRIPTION
The TDA7496 is a stereo 5+5W class AB power amplifier assembled in the @ Multiwatt 15 pack-age,
specially designed for high quality sound, TV applications. Features of the TDA7496 include linear
volume control, Stand-by and mute functions.
-5+5W OUTPUT POWER

-RL =? W@THD= 10% VCC = 22V
-ST-BY AND MUTE FUNCTIONS
-LOW TURN-ON TURN-OFF POP NOISE
-LINEAR VOLUME CONTROL DC COUPLED
-WITH POWEROP. AMP.
-NO BOUCHEROT CELL
-NO ST-BY RC INPUT NETWORK
-SINGLE SUPPLY RANGING UP TO 35V
-SHORT CIRCUIT PROTECTION
-THERMAL OVERLOAD PROTECTION
-INTERNALLY FIXED GAIN
-SOFT CLIPPING
-VARIABLE OUTPUT AFTER VOLUME CON-TROL
-CIRCUIT
-MULTIWATT 15 PACKAGE
PINNING
1 INR.
2 VAROUT_R
3 VOLUME
4 VAROUT_L
5 INL
6 NC
“1 12
7 SWR
8 S_GNR
9 STBY
10 MUTE
11 PW_GND
12 OUTL
13 VS
14 OUTR
15 PW1_GND
TDA8174AW
Independent vertical amplitude adjustement. buffer stage. Power amplifier flyback generator thermal
protection . Internal reference voltage decou-pling
General Description:
TDA8174A and TDA8174AWare a monolithic integrated circuits. It is a full performance and very
efficient vertical deflection circuit intended for direct drive of a TV picture tube in Color and B & W
television as well as in Monitor and Data displays.
PINNING
1. POWER OUTPUT
2. OUTPUT STAGE Vs
3. TRIGGER INPUT
4. HEIGHT ADJUSTMENT
5. VOLTAGE REF DECOUPLING
6. GROUND
7. RAMP GENERATOR
8. BUFFER OUTPUT
9. INVERTING INPUT
10. Vs
11. FLYBACK GENERATOR
STV5114
25MHz BANDWIDTH
CROSSTALK : 55dB
SHORT CIRCUIT TO GROUND OR VCC PRO-TECTED
ANTI SATURATION GAIN CHANGING
VIDEO SWITCHING
“1 13
DESCRIPTION
This integrated circuit provides RGB switching al-lowing connections between peri TV plug, internal RGB
generator and video processor in a TV set. The input signal black level is tied to the same reference
voltageon each input in order to have no differential voltage when switching two RGB generators.
An AC output signal higher than 2 Vpp makes gain going slowly down to 0dBto protect the TV set video
amplifier from saturation. Fast blanking output is a logicial OR between FB1
(Pin 8) and FB2 (Pin 10).
PINNING PIN VALUE

1. R1IN
2. GND
3. R2IN
4. G1IN
5. G2IN
6. B1IN
7. B2IN
8. FB1IN
9. FBOUT
10. FB2+FBBIN
11. BOUT
12. FBGIN
13. GOUT
14. VCC
15. FBRIN
16. ROUT
MC44608
General description:
The MC44608 is a high performance voltage-mode controller designed for off–line converters. This high
voltage circuit that integrates the start–up current source and the oscillator capacitor, requires few external
components while offering a high flexibility and reliability.
The device also features a very high efficiency stand–by management consisting of an effective Pulsed
Mode operation. This technique enables the reduction of the stand–by power consumption to
approximately 1W while delivering 300mW in a 150W SMPS.
• Integrated start–up current source

• Loss less off–line start–up
• Direct off–line operation
• Fast start–up
General Features
• Flexibility
• Duty cycle control
“1 14
• On chip oscillator switching frequency 40, or 75kHz
• Secondary control with few external components
Protections
• Maximum duty cycle limitation
• Cycle by cycle current limitation
• Demagnetization (Zero current detection) protection
• “Over V CC protection” against open loop
• Programmable low inertia over voltage protection against open loop
• Internal thermal protection
GreenLine Controller
• Pulsed mode techniques for a very high efficiency low power mode
• Lossless startup
• Low dV/dT for low EMI radiations
PINNING PIN VALUE

1. Demagnetization Zero cross detection voltage: 50 mV typ.
2. I Sense Over current protection voltage 1V typ.
3. Control Input Min: 7.5V Max.: 18V
4. Ground Iout 2A p-p during scan 1.2A p-p during flyback
5. Driver Output resistor 8.5 Ohm sink 15 Ohm source typ.
6. Supply voltage Max:16V (Operating range 6.6V-13V)
7. No connection
8. Line Voltage Min:50V Max:500V
24CO8
General description:
The 24C16 is a 8Kbit electrically erasable programmable memory (EEPROM), organized as 4 blocks of
256 * 08 bits. The memory operates with a power supply value as low as 2.5V.
Features:
• Minimum 1 million ERASE/WRITE cycles with over 10 years data retention
• Single supply voltage:4.5 to 5.5V
• Two wire serial interface, fully I²C-bus compatible
• Byte and Multi-byte write (up to 8 bytes)
• Page write (up to 16 bytes)
• Byte, random and sequential read modes
• Self timed programming cycle
PINNING PIN VALUE
1. Write protect enable :0V

2. Not connected :0V
3. Chip enable input :0V
4. Ground :0V
5. Serial data address input/output :Input LOW voltage: Min:-0.3V, Max:0.3*Vcc
:Input HIGH voltage: Min:0.7*Vcc, Max:Vcc+1
6. Serial clock :Input LOW voltage: Min:-0.3V, Max:0.3*Vcc
:Input HIGH voltage: Min:0.7*Vcc, Max:Vcc+1
“1 15
7. Multibyte/Page write mode :Input LOW voltage: Min:-0.3V, Max:0.5V
:Input HIGH voltage: Min:Vcc-0.5, Max:Vcc+1
8. Supply voltage :Min:2.5V, Max:5.5V
Saw filter’s list:
VIDEO AUDIO
PAL BG G1975M
PSBG DK K2966M
MONO
PAL II' J1981

PSBGDKK' II' K2966M
PSBGDKK' LL' K2962M L9653
VIDEO AUDIO
PAL BG G3967M G9353M
PAL II' K3958M K9356
STR
PSBGDKK' II' K3958M K9356

PSBGDKK' LL' K3958M K9656
PINNING
1. Input
2. Input-ground
3. Chip carrier-ground
4. Output
5. Output
K9656M, L9653M
PINNING
1. Input
2. Switching Input
3. Chip carrier-ground
4. Output
5. Output
“1 16
“1 17
GENERAL BLOCK DIAGRAM of 11AK46
SCART F-AV
DVD MODULE
TDA7496
R
AUDIO SWITCHING L AU.
CIRCUITS AMP
PLL TUNER
UV1316 R
2
I C
SERVICE
CONNECTOR RGB
MONO
AMP
NVM IF
ST92195
KEYPAD MICRO STV2248C
CONTROLLER VIDEO VER
PROCESSOR AMP
IR SENSOR
TDA8174AW
115V
SMPS VIDEO
+12V AUD. SWITCHING CIRCUITS
MC +8V
HORIZONTAL
44608 +5V FBT
DRIVE
+5V St-by BU808DF
“1 19
DVD SCART1 FAV/BAV SVHS
DVD POWER
SUPPLY
“1 20
SIRA REGISTER PARAMETER
NO
1 OSD OSD Horizontal Position
2 IF1 IF Coarse Adjust

3 IF2 IF Fine Adjust
4 IF3 IF Coarse Adjust for L-Prime
5 IF4 IF Fine Adjust for L-Prime
6 AGC Automatic Gain Control
7 VLIN Vertical Linearity
8 VS1A Vertical Size for 50 Hz / 4:3
9 VS1B Vertical Size for 50 Hz / 16:9
10 VP1 Vertical Position for 50 Hz
11 HP1 Horizontal Position for 50 Hz
12 VS2A Vertical Size for 60 Hz / 4:3
13 VS2B Vertical Size for 60 Hz / 16:9
14 VP2 Vertical Position for 60 Hz
15 HP2 Horizontal Position for 60 Hz
16 RGBH RGB Horizontal Shift Offset
17 WR White Point Adjust for RED
18 WG White Point Adjust for GREEN
19 WB White Point Adjust for BLUE
20 BR Bias for RED
21 BG Bias for GREEN
22 APR APR Threshold
23 FMP1 FM Prescaler when AVL is OFF
24 NIP1 NICAM Prescaler when AVL is OFF
25 SCP1 SCART Prescaler when AVL is OFF
26 FMP2 FM Prescaler when AVL is ON
27 NIP2 NICAM Prescaler when AVL is ON
28 SCP2 SCART Prescaler when AVL is ON
29 F1H High Byte of crossover frequency for VHF1-VHF3
30 F1L Low Byte of crossover frequency for VHF1-VHF3
31 F2H High Byte of crossover frequency for VHF3-UHF
32 F2L Low Byte of crossover frequency for VHF3-UHF
33 BS1 Band Switch Byte for VHF1 Meaningful for only
34 BS2 Band Switch Byte for VHF3 Meaningful for only
35 BS3 Band Switch Byte for UHF Meaningful for only
36 CB Control Byte Meaningful for only PLL Tuner
37 OP1 Option 1 (see the Option List)
42 TX1 Teletext Option 1 (see the Option List)
“1 21
OP1 – Peripheral Options
BIT-7 NOT USED
BIT-6 1, Display “AV-3” as “F-AV”

0, Display “AV-3” as “B-AV”
BIT-5 1, Turn back TV mode after the last AV (with AV key)
0, Turn back first AV mode after the last AV
BIT-4 1, SVHS is available in AV key stream
0, SVHS is NOT available in AV key stream
BIT-3 1, RGB is available in AV key stream
0, RGB is NOT available in AV key stream
BIT-2 1, AV-3 is available in AV key stream
0, AV-3 is NOT available in AV key stream
BIT-1 1, DVD is available in AV key stream
0, DVD is NOT available in AV key stream
BIT-0 1, AV-1 is available in AV key stream
0, AV-1 is NOT available in AV key stream
OP2 – Reception Standard Options
BIT-7 1, 3-button keyboard (V-, P+, V+)

0, 4/5 button keyboard (V-, V+, P-, P+, Menu)
BIT-6 1, L/L’ is available
0, L/L’ is not available
BIT-5 1, I is available
0, I is not available
BIT-4 1, DK is available
0, DK is not available
BIT-3 1, BG is available
0, BG is not available
BIT-2 RESERVED (Keep as "0")
BIT-1 RESERVED (Keep as "0")
BIT-0 1, WFI available

0, WFI NOT available
OP3 – Video Options
BIT-7 Xtal Configuration

BIT-6 00, 1 Xtal PAL 4.43
01, 2 Xtal PAL/NTSC 4.43/3.58
10, 1 Xtal PAL/SEC/NTSC 4.43
11, 2 Xtal PAL/SEC/NTSC 4.43/3.58
BIT-5 1, Enable Blue back when no signal in AV modes
0, No Blue back in AV modes
BIT-4 1, White Insertion is ON
0, White Insertion is OFF
BIT-3 1, Blue Background when no signal
0, Disable Blue Background
BIT-2 1, Semi-transparent background for menu
0, Solid Menu background for menu
“1 22
BIT-1 1, Black Stretch is ON
0, Black Stretch is OFF
BIT-0 1, APR is ON
0, APR is OFF
OP4 – TV Features
BIT-7 1, Headphone is available (for STEREO models)

0, Headphone is not available
BIT-6 1, Arabic/Persian ON
0, Arabic/Persian OFF
BIT-5 1, Hebrew ON
0, Hebrew OFF
BIT-4 1, Hotel Mode can be activated
0, Hotel Mode can not be activated
BIT-3 1, No Signal Timer is enabled
0, No Signal Timer is disabled
BIT-2 For PLL Tuner
1, Frequency based search
0, Channel table based search
For VST Tuner
1, VST Band drive is negative logic (with transistors on the chassis)
0, VST Band drive is positive logic (without transistors on the chassis)
BIT-1 1, 3-band tuning (VHF1, VHF3, UHF)

0, 1-band tuning (only UHF)
BIT-0 1, Extra 200 msec blanking for VST
0, no-extra blanking
OP5 – Channel Tables
BIT-7 1, Extra 150 msec blanking more for VST

0, no-extra blanking
BIT-6 1, “Programme” item in AUTOSTORE menu is visible
0, “Programme” item in AUTOSTORE menu is invisible
BIT-5 NOT USED
BIT-4 1, French OS Channel Table is available

0, French OS Channel Table is not available
BIT-3 1, French Channel Table is available
0, French Channel Table is not available
BIT-2 1, England Channel Table is available
0, England Channel Table is not available
BIT-1 1, East Europe Channel Table is available
0, East Europe Channel Table is not available
BIT-0 1, West Europe Channel Table is available
0, West Europe Channel Table is not available
TX1 – Teletext Options
BIT-7 NOT USED
BIT-6 RESERVED (must be 0)
“1 23
BIT-5 5 4 3 Teletext Language Groups
BIT-4 000, Group 1 – West
BIT-3 (English, French, Swedish, Czech, German, Portuguese, Italien, Rumanian)

001, Group 2 – West/East
(Polish, French, Swedish, Czech, German, Serbian, Italien, Rumanian)
010, Group 3 – West/Turkish
(English, French, Swedish, Turkish, German, Portuguese, Italien, Rumanian)
011, Group 4 – East/Cyrillic
(English, Cyrillic, Swedish, Czech, German, Serbian, Lettish, Rumanian)
100, Group 5 – Arabic
(English, French, Swedish, Turkish, German, Hebrew, Italien, Arabic)
BIT-2 2 1 0 Device type selection

BIT-1 000, EPROM M6 A
BIT-0 001, ROM H5 P
010, ROMLESS H5 P
011, EPROM M6 R
100, ROM M6 R
101, OSDEPROM M6 R
110, ROM M6 P
111, Read Auto Gain Table for the device from EEPROM
AK46/TITANIUM – Languages Groups

GROUP 1 - WEST
• ENGLISH
• FRENCH
• SWEDISH
• CZECH
• GERMAN
• PORTUGUESE
• ITALIAN
• RUMANIAN
GROUP 2 – WEST / EAST
• POLISH
• FRENCH
• SWEDISH
• CZECH
• GERMAN
• SERBIAN
• ITALIAN
• RUMANIAN
• GROUP 3 – WEST / TURKEY
• ENGLISH
• FRENCH
• SWEDISH
• TURKISH
• GERMAN
• PORTUGUESE
• ITALIAN
• RUMANIAN
GROUP 4 – EAST / CYRILLIC
• ENGLISH
• CYRILLIC
• SWEDISH
“1 24
• CZECH
• GERMAN
• SERBIAN
• LETTISH
• RUMANIAN
GROUP 5 - ARABIC
• ENGLISH
• FRENCH
• SWEDISH
• TURKISH
• GERMAN
• HEBREW
• ITALIAN
• ARABIC
Using Coloured Buttons
RED : No function.
GREEN : Is used to switch the aspect ratio between 4:3 and 16:9.
YELLOW : Is used to prepare the system for screen-adjustments.
BLUE : No function.
“1 25
CONTENTS
1. CHANGE HISTORY .................................................................................................................... 4

2. GENERAL DESCRIPTION .......................................................................................................... 4
2.1 STI5508 ...................................................................................................................................... 4
2.2 M2 .............................................................................................................................................. 5
2.3 DRIVE INTERFACES .................................................................................................................. 5
2.4 FRONT PANEL ........................................................................................................................... 5
2.5 REAR PANEL ............................................................................................................................. 6
3. GPIO, IRQ, AND CHIP SELECT ASSIGNMENTS ........................................................................ 6
4. JUMPER CONFIGURATION ........................................................................................................ 7
5. AUDIO OUTPUT .......................................................................................................................... 8
5.1 AUDIO DACS .............................................................................................................................. 8
5.2 AUDIO MUTE .............................................................................................................................. 8
6 VIDEO INTERFACE .................................................................................................................... 8
6.1 SCART INTERFACE ................................................................................................................... 9
6.2 DIGITAL VIDEO INTERFACE ....................................................................................................... 9
7. MPEG DECODER SDRAM MEMORY ........................................................................................ 9
8. PROCESSOR SDRAM MEMORY .............................................................................................. 9
9. FLASH MEMORY ....................................................................................................................... 10
10. SERIAL EEPROM MEMORY ..................................................................................................... 10
11. TMM DRIVE INTERFACE ............................................................................................................ 10
11.1 CONNECTION INFORMATION .................................................................................................... 10
11.2 TMM DRIVE TRAY MOTOR CONTROL AND PUSH AND STALL SENSE CIRCUITRY................. 11
12. ATAPI DRIVE INTERFACE AND EPLD ........................................................................................ 11
13. AUDIO SAMPLING RATE AND EXTERNAL PLL COMPONENT CONFIGURATION ..................... 11
14. UART SERIAL PORT .................................................................................................................. 11
15. FRONT PANEL ........................................................................................................................... 12
15.1 FRONT PANEL MICRO ............................................................................................................... 12
15.2 VFD CONTROLLER .................................................................................................................... 12
15.3 MICROPHONE INPUTS .............................................................................................................. 12
15.4 HEADPHONE OUTPUTS ............................................................................................................ 12
16. MISCELLANEOUS FUNCTIONS ................................................................................................. 12
16.1 POWER DOWN .......................................................................................................................... 12
16.2 RESET CIRCUITRY .................................................................................................................... 13
16.3 VOLTAGE REGULATORS ........................................................................................................... 13
17. CONNECTORS ........................................................................................................................... 13
17.1 ATAPI DRIVE STANDARD CONNECTOR .................................................................................... 13
17.2 TMM DRIVE CONNECTORS ....................................................................................................... 14
17.3 STI5508 JTAG INTERFACE ......................................................................................................... 15
17.4 RS232 SERIAL PORT ................................................................................................................. 16
17.5 DIGITAL YUV OUTPUT HEADER ................................................................................................ 16
17.6 ANALOG VIDEO INPUT HEADER .............................................................................................. 16
17.7 SCART CONNECTORS .............................................................................................................. 16
17.8 POWER CONNECTOR ............................................................................................................... 17
18. SCHEMATICS ............................................................................................................................. 17
19. BILL OF MATERIALS .................................................................................................................. 17
20. BOARD LAYOUT ........................................................................................................................ 17
20.1 TOP SIDE ASSEMBLY DRAWING ............................................................................................. 17
20.2 BOTTOM SIDE ASSEMBLY DRAWING ...................................................................................... 17
1 CHANGE HISTORY
2
2.3 DRIVE INTERFACES
The system supports either a standard ATAPI drive interface or the SGS Thomson TVM502 drive (simply called TMM).
The TMM drive is supplied with either a three connector interface or a single FFC cable connection. The design supports
either connection method. The TMM three connector interface utilizes separate connectors for power, data, and drive tray
motor control. Circuitry to control the TMM drive tray is located on the decoder board when this TMM drive version is
used. The interface to the ATAPI drive is included within the STi5508. The ATAPI data bus is buffered so that the ATAPI
cable does not interfere with signal quality. An ATAPI drive is connected via the standard 34 pin dual row PC style IDE
header. An IDE power connector is also supported for convenience.
2.4 FRONT PANEL

The front panel is included in the reference design and is based around an inexpensive Futaba VFD and a common NEC
front panel controller chip, (uPD16311). The STi5508 controls the uPD16311 using several control signals, (clock, data,
chip select). The infra-red remote control signal is passed directly to the STi5508 for decoding.
A more advanced front panel is possible with the addition of a front panel microcontroller. A Microchip PIC can be used to
control the 16311, receive the infra-red remote control decoding, and system power down. Communication between the
STi5508 and the front panel PIC is accomplished over an I²C interface.
The front panel connector also supports two microphone inputs and a stereo headphone output.
2.5 REAR PANEL

A typical rear panel is included in the reference design. This rear panel supports:
- Six channel and two channel simultaneous audio outputs
- Optical and coax S/PDIF outputs are supported
- Composite, S-Video, and RBG/YUV outputs
- Dual SCART provides SCART passthrough when DVD output is not supplied
- External video DENC Connections
The six video signals used to provide CVBS, S-Video, and RGB/YUV are generated by the STi5508s internal video DAC.
The video signals are be buffered by external circuitry. The STi5508 can generate either RGB or YUV outputs on three of
the pins by configuring internal STi5508 registers.
Six channel audio output by the STi5508 in the form of three I²S (or similar) data streams. An addition, an I²S stream is
generated by the STi5508 to support simultaneous two-channel output. The S/PDIF serial stream is also generated by
the STi5508 output by the rear panel. A six-channel audio DAC, a stereo DAC, or both can be installed.
3 GPIO, IRQ, AND CHIP SELECT ASSIGNMENTS
PIO Port Bit Pin # STi5508 Alternate Function CineMaster CE Function

Port 0 Bit 0 186 SC0_DATA #SOFT_RESET
Port 0 Bit 1 187 #ATAPI_RD #ATAPI_RD
Port 0 Bit 2 188 #ATAPI_WR #ATAPI_WR
Port 0 Bit 3 189 SC0_CLK DAC_CCLK (Audio DAC control)
Port 0 Bit 4 190 SC0_RST DAC_CCLK (Audio DAC control)
Port 0 Bit 5 191 SC0_CMD_VCC #DAC_CS0 (Audio DAC control)
Port 0 Bit 6 192 SC0_DATA_DIR #DAC_CS1 (Audio DAC control)
Port 0 Bit 7 193 SC0_DETECT Unused (Test Point 39)
Port 1 Bit 0 194 SSC0_DATA SDA (I2C)
Port 1 Bit 1 195 SSC0_CLK SCL (I2C)
Port 1 Bit 2 196 PARA_DVALID/SC_EXT_CLK Unused (Test Point 35)
Port 1 Bit 3 197 TXD2 TXD (Serial Port)
Port 1 Bit 4 200 RXD2 RXD (Serial Port)
Port 1 Bit 5 201 PARA_SYNC/TXD1 SR0 (for PLL1700)
Port 1 Bit 6 202 TRIGIN TRIGIN (JTAG)
Port 1 Bit 7 203 TRIGOUT TRIGOUT (JTAG)
Port 2 Bit 0 204 SC1_DATA FPCLK (Front Panel)
Port 2 Bit 1 205 PARA_REQ/RXD1 FS0 (for PLL1700)
Port 2 Bit 2 206 PARA_STR FS1 (for PLL1700)
Port 2 Bit 3 207 SC1_CLK RTS (Serial Port)
Port 2 Bit 4 208 SC1_RST CTS (Serial Port)
Port 2 Bit 5 1 SC1_CMD_VCC FPDATA (Front Panel)
Port 2 Bit 6 2 DAC_DATA/SC1_DATA_DIR DAC_DATA (Stereo Audýo)
Port 2 Bit 7 3 SC1_DETECT FPSTRB (Front Panel)
4
1. CHANGE HISTORY
Revision Date Author Comments

Rev 1.0 7/23/2000 Jim Loughin Initial Release
Rev 1.1 8/23/2000 Jim Loughin Updated to match final design
2. GENERAL DESCRIPTION
Major functional blocks are discussed briefly in this section. A more detailed description is contained later in the document.
2.1 STI5508
The STi5508 provides a highly integrated back-end solution for DVD applications. A host CPU handles both the general
application (the user interface, and the DVD, CD-DA, VCD, SVCD navigation) and the drivers of the different embedded
peripheral (audio/video, karaoke, sub-picture decoders, OSD, PAL/NTSC encoder...). Because of its memory savings,
increased number of internal peripherals, improved development platform and reference design, theSTi5508 offers a cost-
effective solution to DVD applications, with rapid time-to-market. These functions include:
Integrated 32-bit host CPU @ 60MHz

- 2 Kbytes of instruction cache, 2 Kbytes of data cache, and 4Kbytes of SRAM configurable as data cache.
Audio decoder
- 5.1 channel Dolby Digital® /MPEG-2 multi-channel decoding, 3 X 2-channel PCM outputs
- IEC60958 IEC61937 digital output
- DTS® digital out 5.1 channel
- SRS®/TruSurround®
- MP3 decoding
Karaoke processor
- Echo, pitch shift, microphone inputs, voice cancellation and multiple other effects
Video decoder
- Supports MPEG-2 MP@ML
- Fully programmable zoom-in and zoom-out
- PAL to NTSC and NTSC to PAL conversion
DVD and SVCD subpicture decoder
High performance on-screen display
- to 8 bits per pixel OSD options
- Anti-flicker, anti-flutter and anti-aliasing filters
PAL/NTSC/SECAM encoder
- RGB, CVBS, Y/C and YUV outputs with 10-bit DACs
- Macrovision® 7.01/6.1 compatible
Shared SDRAM memory interface
- Supports one or two 16Mbit, or one 64Mbit 125 MHZ SDRAMs
Programmable CPU memory interface for SDRAM, ROM, peripherals...
Front-end interface
- DVD, VCD, SVCD and CD-DA compatible
- Serial, parallel and ATAPI interfaces
- Hardware sector filtering
- Integrated CSS decryption and track buffer
Integrated peripherals
- UARTS, 2 SmartCards, I2C controller, 3 PWM outputs, 3 capture timers
- Modem support
- 38 bits of programmable I/O
Please refer to the STi5508 Data Sheets: STi5508 DVD HOST PROCESSOR WITH ENHANCED
AUDIO FEATURES and STi5508 REGISTER MANUAL for more detailed information.
2.2 MEMORY
The STi5508 includes all of the interface signals to connect to industry standard SDRAM, DRAM, ROM, and I2C memory
devices. The system includes one or two SDRAM components. The MPEG decoder unit interfaces to a single 4M x 16bit
SDRAM over the SMI bus. The general purpose processor can share the decoder SDRAM or can access an optional
SDRAM installed on the EMI bus. This EMI SDRAM can be either a 1Mx16 or 4Mx16 chip. The optional EMI SDRAM can
be installed if the system requires higher performance of requires more RAM than is standard system (due to complex trick
modes, advanced GUI, etc). The standard production Ravisent CineMasterCE software will execute without EMI SDRAM
installed, however EMI SDRAM is required to perform debugging and prototyping. A single 1Mx16 FLASH ROM device is
support on the EMI bus. There is also a small I²C serial EEPROM (from 1Kbit to 256Kbit) for storage of user player settings,
software configuration information, title specific information, or other purposes.
3
Port 3 Bit 0 6 PARA_DATA0 OPEN (TMM Tray Control)
Port 3 Bit 1 7 PARA_DATA1 CLOSE (TMM Tray Control)
Port 3 Bit 2 8 PARA_DATA2 Unused (Test Point 36)
Port 3 Bit 3 9 PARA_DATA3 Front Panel IR
Port 3 Bit 6 12 PARA_DATA6/COMP1 #SENSE (TMM Tray Control)
Port 3 Bit 7 13 PARA_DATA7/COMP2 #PUSH (TMM Tray Control)
Port 4 Bit 0 39 YUV0 YUV0 (External Video DENC)
Port 4 Bit 1 40 YUV1 YUV1
* Front Panel uses the 16311 controller. In the CineMaster design, FPDIN and FPDOUT are connected
together as FPDATA.
Pin Name Pin # STi5508 Pin Function CineMaster CE Function

#CE1 134 Programmable Chip Enable 1 ATAPI Buffer Chip Enable
#CE2 133 Programmable Chip Enable 2 Unused
#CE3 132 Programmable Chip Enable 3 FLASH Memory Chip Select
#IRQ0 127 Interrupt 1 Front Panel Interrupt
#IRQ1 126 Interrupt 2 Front End Interrupt (ATAPI/TMM)
#IRQ2 125 Interrupt 3 Unused
Table 1 GPIO, IRQ, and Chip Select Assignments
4. JUMPER CONFIGURATION
Jumper Function Installed Not Installed

JP1 Power +3.3V, +5V and +12V are Uninstalled all
Down disconnected from the components are powered
STi5508 and associated
circuitry using a FET switch
JP3 Boot From forces STi5508 to boot from Not Installed STi5508 will
Link JTAG interface only attempt to boot from
FLASH, but will also boot
from JTAG interface
* Note: There is no JP2
Table 2 Jumper Configuration
5. AUDIO OUTPUT
The STi5508 supports both a six channel analog output and a stereo output configuration. Both of these output configura-
tions are available simultaneously (eight analog outputs total). In a system configuration with six analog outputs, the front
left and right channels can be configured to provide the stereo outputs, Dolby Surround, and SRS TruSurround, or the left
and right front channels for a 5.1 channel surround system.
The STi5508 also provides a stereo output channel that can be used in combination with the 5.1 outputs. An example of
this configuration is a DVD player with these stereo outputs connected to the TV and the six channel outputs connected
to the surround sound amplifier unit. In this setup, the consumer can use the TV speakers or the surround speaker
without changing any wires. The stereo output can be configured separately from the six-channel left and right outputs,
so, for example, the stereo output can be configured for Dolby ProLogic.
The Sti5508 also provides digital output in S/PDIF format. The evaluation board supports both optical and coaxial
S/PDIF outputs.
5.1 AUDIO DACs

The STi5508 supports several variations of an I²S type bus, varying the order of the data bits (leading or no leading zero
bit, left or right alignment within frame, and MSB or LSB first) is possible using the Sti5508 internal configuration registers.
The I²S format uses four stereo data lines and three clock lines. The I²S data and clock lines can be connected directly to
one or more audio DAC to generate analog audio output.
5
The evaluation board uses a six-channel DAC and also a two-channel DAC. The six-channel DAC is connected to the
three STI5508 data signals for six-channel output and the two-channel DAC is connected to the STi5508 optional stereo
output. The board can be configured with either the six- or two-channel DAC, or both. When the two-channel DAC is not
used, the left and right front audio can be connected to the stereo audio output connectors by installing zero ohm resis-
tors R364 and R365.
The six-channel DAC is an AKM AK4356. The two-channel DAC is an AK4394 also made by AKM. Both of these DACs
support up to 192Khz sampling rate. A less expensive 96kHz two-channel DAC with the same pin-out can be placed
instead of the AK4394. Four STi5508 PIO pins are used to configure the audio DACs. The outputs of the DACs are
differential, not single ended so a slightly more expensive buffering circuit is required. The buffer circuits use NJR
NJM5532 opamps to perform the low-pass filtering and the buffering.
5.2 AUDIO MUTE

The audio DACs contain an internal mute circuit and can be enabled by the STi5508 PIO pins. The evaluation board may
output a small pop when the system is powered on and off, but no audible pops should be heard during operation or
when entering or leaving standby mode.
6. VIDEO INTERFACE
The STi5508 integrates a PAL/NTSC encoder. It converts the digital MPEG/Sub Picture/OSD stream into a standard
analog baseband PAL/NTSC signals. Six analog video outputs provide CVBS, S-Video (Y/C), and RGB/YUV formats. The
three RGB signals can be configured via an internal STi5508 register setting to output either RGB or YUV video signals.
The encoder handles interlaced and non-interlaced mode. It can perform Closed Captions, CGMS or Teletext encoding
and allows Macrovision 7.01/6.1 copy protection. The encoder supports both master and slave modes for synchronization.
The six video signals are routed to the back panel where they are low-pass filtered and buffered. The six active video
buffer circuits on the decoder board are identical and use a video speed MAX4018 opamp made by Maxim.
The buffered CVBS video is available on a RCA (cinch) style jack, S-Video on a mini-DIN, RGB/YUV on a triple RCA
jack, and all six signals (and stereo audio) are available on a SCART connector.
Note:The STi5508 is not capable of placing the video synch information in the green signal as required by some RGB
monitors. The synch information must be obtained from the CVBS output and connected to the external sync input of an
RGB monitor.
Note:When the STi5508 is configured to output YUV signals, the RGB pins of the SCART connector will also output YUV.
6.1 SCART INTERFACE

The Ravisent evaluation board contains a SCART controller chip from ST Microelectronics, the STv6412. This controller
chip allows SCART daisy-chaining the SCART output from another device can be connected to the DVD player SCART
input and passed through when the DVD player is in standby.
All SCART functions are controlled by the 6412 chip, which is in turn controlled by the STi5508 over the I²C bus. Please
see the STv6412 AUDIO/VIDEO SWITCH MATRIX data sheet for more detailed information.
6.2 DIGITAL VIDEO INTERFACE

An external video DENC can be connected to the STi5508. The digital output and analog input headers are provided on the
board, J20 and J19 respectively. The video encoder is controlled via I2C through the header. Also supplied on the header
are +3.3V, +5V, ground, and +5V and 5V analog supplies. The output of the external DENC is then fed into the video
filter-buffers on board. The values of the discrete components in the filter-buffers should be changed to match the charac-
teristics of the external DENC.
7. MPEG DECODER SDRAM MEMORY

The STi5508 includes glueless interfaces to SDRAM memory for the MPEG decoder. The STi5508 supports one or two
1Mx16bit chips or a 4Mx16bit SDRAM chip. However, the Ravisent evaluation board supports only a 64Mbit chip. The
device used is a 4M x 16 bit, 125MHz, 3.3V, 54 pin TSOP II, Micron Technology MCT48LC4M16A2TG-7 or equivalent.
8. PROCESSOR SDRAM MEMORY

The STi5508 supports DRAM or SDRAM on its processor bus without any glue logic required. The Ravisent evaluation
board supports only SDRAM - either a 1Mx16bit or a 4Mx16bit SDRAM. The STi5508 processor can be configured to
share the decoder memory. This will reduce performance slightly, but will reduce the cost of the system, as processor
SDRAM is no longer required. It is expected that a typical DVD player will not need any processor SDRAM and this chips
will only be installed for test and debug purposes.
Dual PCB footprints were used to accommodate the differences in packaging between 16M and 64M SDRAMS. U5/1 is
the 16Mbit footprint and U5/2 is the 64Mbit footprint. The same 64Mbit SDRAM used for decoder memory can be used for
processor SDRAM.
6
9. FLASH MEMORY
The decoder board supports a single 1Mx16bit FLASH memory device. The device is a 1M x 16, 90ns, bottom boot block,
3.3V, 48 pin TSOP II, SGS Thomson M29F160BB-90N1 or equivalent. Both 3.3V and 5V FLASH devices can be installed.
Our current FLASH loading software supports several FLASH chips from different manufacturers. To support new chips, the
programming algorithm will have to be adapted, but this is a rather simple adaptation.
Note: Intel and Micron FLASH require that pins 13 and 14 are tied to the positive power supply to allow programming in
circuit. To support these device families, install zero ohm (0R0) resistors in locations R79 and R80.
Note: Install a zero ohm resistor in location R350 to support +5V FLASH. Install zero ohms in R352 to support +3.3V
FLASH. Never install both R350 and R352 at the same time as this will short the 3.3 and 5V supplies together. The default
is +3.3V.
Note: Some FLASH devices use pin 15 for address pin A19, while most others use pin 9. To support a chip that uses pin
15, install R81.
10. SERIAL EEPROM MEMORY

An I²C serial EEPROM is used to store user configuration (i.e. language preferences, speaker setup, etc.) and software
configuration information (i.e. remote control type). Industry standard EEPROM range in size from 1kbit to 256kbit and
share the same IC footprint and pinout. The default device is 2kbit, 256k x 8, SOIC8 SGS Thomson ST24C02M1 or
equivalent. See the section on Reset Circuitry for a less costly EEPROM solution.
11. TMM DRIVE INTERFACE

The STi5508 will directly supports a Thomson TVM502 drive (or a similar drive built around the ST chip drive set) without
any external glue logic. The newer TVM drives include the disc tray motor control circuitry, but the older drives do not.
Tray motor control circuitry is included on the evaluation board to support these older drives.
11.1 CONNECTION INFORMATION

The newer TMM drive uses a 19 pin FFC connector while the older drives use two PicoFlex ribbon connectors and a
two pin tray motor connector. Both connector systems are supported on the evaluation board. The drive interface, with
the exception of the tray motor circuitry, is contained entirely in the STi5508.
The older TMM drive connects to the evaluation board in three places:
J5 Drive tray motor terminals
J6 Power cable connector
J7 Data cable connector
The newer TMM drive connects to the evaluation board with a single connector:
J8 FFC19 connector
The connectors selected by Thomson for the data and power cables are in the PicoFlex product line manufactured by Molex
and Lumberg. The FFC connector is available from many suppliers including Molex. See Bill of Material for part numbers.
11.2 TMM DRIVE TRAY MOTOR CONTROL AND PUSH AND STALL SENSE CIRCUITRY
There is circuitry on the decoder board to power the TMM drive tray and to monitor its activity. When the tray is being
opened or closed and the tray has reached the end of its travel or is being jammed, the motor will stall and draw a high
current. Circuitry monitors the level of current used by the motor and will toggle a PIO pin of the STi5508 when the motor
has stalled, (schematic net name: #SENSE). The STi5508 will then remove power to the motor. Also, if the tray is open and
the user pushes the tray to close it, the motor will generate voltage. Circuitry will sense this voltage and toggle another PIO
pin, (schematic net name: #PUSH). The STi5508 will then close the tray.
The sensitivity of the push sense can be adjusted by changing the value of R114 in relation to R117. When the tray is
motionless, the voltage across the motor is zero. When the tray is pushed the voltages at either side of the motor begin to
diverge. These two voltages are fed into a comparator to create the trigger signal. This is an improved circuit from the
Ravisent STi5505 evaluation boards and this new circuit is not sensitive to temperature or component tolerances.
Note: To disable the push sense circuit, remove R109 and R112. R106 and R107 should already be installed.
12. ATAPI DRIVE INTERFACE AND EPLD

The STi5508 includes a glueless ATAPI interface on-chip. While this interface limits performance of the system, it is a lower
cost solution than providing external logic to interface the drive to the STi5508 front-end interface.
Standard ATAPI DVD drives are supported through the ATAPI EPLD interface. The drive connects to the decoder board
through a standard 40 pin header, The header is a 2 row by x 20 pins, 0.1 pin spacing, and has 0.025 square pins.
Note: The decoder board supports the standard ATAPI electrical connections, but the software protocol within the drive is
not always supported according to ATAPI specifications. Custom software may need to be developed and tested to support
ATAPI drives from different manufacturers.
7
13 AUDIO SAMPLING RATE AND EXTERNAL PLL COMPONENT CONFIGURATION
The decoder board has optional PLLs, which can be installed to provide the audio clock for the system. The initial version
of the STi5505 was not able to provide an audio clock for 96kHz support and an external PLL was used to support this.
This was fixed in the STi5505 later chip revisions and therefore no problems are expected in the STi5508. However, in
case a problem arises, the PLL circuit can be installed to provide a high quality clock particularly important in S/PDIF
applications. In the default configuration, a small buffer chip is installed to buffer the audio clock between the STi5508
and the audio DACs.
14 UART SERIAL PORT

The evaluation board provides an RS232 connection to the STi5508. A standard DB9 connector ribbon cable can be
connected to the 10 pin header provided, (J9). The RS232 buffer can also be bypassed and the 3.3V signals can be
accessed on the header. ASC2 is the serial port used to this connection.
15. FRONT PANEL

15.1 FRONT PANEL MICRO
A Microchip PIC can be installed in the system to control the front panel VFD, perform IR remote control decoding and
power down functions, and read the position on two POTs with its internal ADC. When the front panel micro is installed,
the entire decoder board circuit can be powered down in standby mode because the PIC will decode the IR signals.
15.2 VFD CONTROLLER

The VFD controller is a NEC uPD16311. This controller is not a processor, but does include a simple state machine
which scans the VFD and reads the front panel button matrix. The 16311 also includes RAM so it can store the current
state of all the VFD icons and segments. Therefore, the 16311 need only be accessed when the VFD status changes
and when the button status is read. The STI5508 can control this chip directly using PIO pins or can allow the front panel
PIC to control the VFD.
15.3 MICROPHONE INPUTS

The board has two ¼ phono-jacks for microphone input. The microphone circuits consist of microphone pre-amps, a
signal buffers, and a stereo ADC. The microphone pre-amp, SSM2165, conditions the signal for better performance. The
stereo ADC is a Crystal CS5331 and connects directly to the STi5508 digital audio input via I²S.
Adjusting the value POT1 and POT2 can vary the compression characteristics of the microphone signal. See the
SSM2165 data sheet for a graph of the compression characteristics and POT settings. When the correct POT setting is
found, the pots can be replaced with fixed resistors, R382 and R383.
15.4 HEADPHONE OUTPUTS

The left and right audio is amplified and output through a stereo ¼ phono-jack. The audio is from the two-channel output,
not the let and right channel of the six-channel, (the left and right six-channel audio can be connected to the left and right
two-channel output when the stereo DAC is not installed). A dual logarithmic POT is used to adjust the volume of the
audio before amplification, POT5. The connections for left and right channels at the headphone jack can be swapped by
changing the resistor stuffing options, R376-379
.
16 MISCELLANEOUS FUNCTIONS
16.1 POWER DOWN
Two dual FET ICs can be installed on the decoder board to enable a power down feature. Power down is activated by
connecting a switch across JP1, shorting the two pins together pulling pin 2 to +5V. The front panel microcontroller can
also control the power down status by driving FPPWD high. When in power down state, power can be removed from all of
the circuitry except the front panel micro, which must remain power to decode remote control signaling and scanning the
front panel buttons. If the front panel micro is not used, then the STi5508 cannot be powered down.
The board can be configured in several ways to accomplish a power down goal. The net VCC_PIC is always powered.
VCC can either be switched (by installing R3) or always powered (by installing R1). VCC3 can either be switched (by
installing R5)or always powered (by installing R2). VCC-S, VCC3-S, +12V-S, and +8V-S are switched. There are four
LEDs used to indicate power state and they can be connected on either side of the FET switch. The dual FET is a
Fairchild NDS8934 and is located at Q1 and Q2.
Note: If the power down feature is enabled FPPWD must be driven by the front panel micro or some other source.
16.2 RESET CIRCUITRY

Three different chips are supported to provide the power-on-reset and pushbutton reset function: Analog Device ADM707
(or equivalent), Telcom Semiconductor TC1270, or Xicor X1242. The TC1270 is a lower cost alternative to the ADM707.
The Xicor device also includes 2kbits of Serial EEPROM storage and can be used to replace both the reset and
SEEPROM devices to reduce cost. All three devices support and pushbutton reset switch.
8
16.3 VOLTAGE REGULATORS
There are two +5V linear regulators to generate +5V for the analog circuitry from +12V. A smaller DPAK surface mount
device can be used in most circumstances, but in applications were more than 150mA are required, a TO-220 through-
hole package can be used.
The STi5508 requires 2.5V to operate. This voltage is generated from +5V.
Negative 5V is required by the audio buffer circuitry and this is generated in one of three ways. If 12V is supplied by the
power supply, it is regulated to 5V with a linear regulator. If no 12V is supplied, a DC-DC can be installed in U51 to
generate either 12V or 5V. The use of a switching regulator to generate the negative voltage may introduce noise into
that voltage, so better audio performance may be produced by generating 12V with the DC-DC converter and then
regulating this to 5V with a linear regulator.
17 CONNECTORS
17.1 ATAPI DRIVE STANDARD CONNECTOR
ATAPI Drive Interface J23

Pin Description Pin Description
1 #RESET 2 GND
3 DATA7 4 DATA8
5 DATA6 6 DATA9
7 DATA5 8 DATA10
9 DATA4 10 DATA11
11 DATA3 12 DATA12
13 DATA2 14 DATA13
15 DATA1 16 DATA14
17 DATA0 18 DATA15
19 GND 20 -
21 DMARQ 22 GND
23 #IOW 24 GND
25 #IOR 26 GND
27 IOCHRDY 28 GND
29 #DMACK 30 GND
31 INTRQ 32 HIO16
33 ADDR1 34 #PDIAG
35 ADDR0 36 ADDR2
37 #CS0 38 #CS1
39 - 40 GND
Table 3 ATAPI Drive Interface J23
TMM Tray Connector J5

Pin Description
1 +12V
2 GND
3 GND
4 +5V
Table 4 ATAPI Power Connector J4
17.2 TMM DRIVE CONNECTORS
TMM Tray Connector J5

Pin Description
1 OPEN
2 CLOSE
Table 5 TMM Tray Connector J5
TMM Power Connector J6

Pin Description
1 +5V (filtered)
2 +5V
3 GND
4 GND (filtered)
5 GND
6 +8V
7 GND
8 +12V
9 GND
10 +3.3V
Table 6 TMM Power Connector J6
9
TMM Data Connector J7
Pin Description
2 GND
3 SYNC
4 FLAG
5 DATA
6 BCLK
7 GND
8 #FE RESET
9 FE I NT
10 SCL
11 SDA
12 GND
Table 7 TMM Data Connector J7
TMM FFC19 Connector J8

1 - 11 SDA
2 GND 12 GND
3 SYNC 13 GND
4 FLAG 14 +3.3V
5 DATA 15 +5V
6 BCLK 16 GND
7 GND 17 GND (filtered)
8 #FRESET 18 +12V
9 FEINT 19 +8V or +12V
10 SCL
Table 8 TMM FFC19 Connector J8
17.3 STI5508 JTAG INTERFACE
JTAG Programming Interface J2

1 - 2 GND
3 PIO3_7 4 GND
5 PIO3_6 6 GND
7 - 8 GND
9 TMS 10 GND
11 TCK 12 GND
13 TDI 14 GND
15 TDO 16 GND
17 #JTAG_RESET 18 GND
19 #TRST 20 GND
Table 9 JTAG Programming Interface J2
17.4 RS232 SERIAL PORT
RS232 Serial Port Header J9

1 - 2 -
3 TXD 4 CTS
5 RXD 6 RTS
7 - 8 -
9 GND 10 -
Table 10 RS232 Serial Port Header J9
10
17.5 DIGITAL YUV OUTPUT HEADER
Digital YUV Output Header J20

1 YUV0 2 GND
3 YUV1 4 GND
5 YUV2 6 GND
7 YUV3 8 VSYNC
9 YUV4 10 -
11 YUV5 12 HSYNC
13 YUV6 14 -
15 YUV7 16 GND
17 PIXCLK 18 GND
19 - 20 GND
21 SCL 22 +5V or +3.3V
23 SDA 24 +5V (analog)
25 GND 26 -5V (analog)
Table 11 Digital YUV Output Header J20
17.6 ANALOG VIDEO INPUT HEADER
Analog Video Input Header J19

1 RED 2 GND
3 GREEN 4 GND
5 BLUE 6 GND
7 CHROMA 8 GND
9 LUMA 10 GND
11 CVBS 12 GND
Table 12 Analog Video Input Header J19
17.7 SCART CONNECTORS
SCART Connectors J10

1 RIGHT AUDIO OUT 2 RIGHT AUDIO IN
3 LEFT AUDIO OUT 4 GND
5 GND 6 LEFT AUDIO IN
7 BLUE 8 SWITCH
9 GND 10 -
11 GREEN 12 -
13 GND 14 GND
15 RED (CHROMA) 16 BLANK
17 GND 18 GND
19 CVBS OUT (LUMA) 20 CVBS IN
21 GND (shield)
Table 13 SCART Connectors J10
17.8 POWER CONNECTOR
Power Connector J1
Pin Description
1 +5 V
2 +3.3 V
3 +3.3 V
4 GND
5 GND
6 +12 V
71 GND
81 -12 V
Table 14 Power Connector J1
1
Connection to these two terminals is not required unless the board uses 12V. In a system without 12V,
a six pin header can be installed into pins one (1) through six (6) leaving pins seven (7) and eight (8) unpopulated.
18 SCHEMATICS
19 BILL OF MATERIALS
20 BOARD LAYOUT
20.1 TOP SIDE ASSEMBLY DRAWING
20.2 BOTTOM SIDE ASSEMBLY DRAWING
11
A B C REV
DDESCRIPTION E
APPROVAL DATE
1.0 INITIAL RELEASE
Production - STi5508/80
4 DECMEM STi5508 SYSMEM 4
MA[0..13] MA[0..13] MA[0..13] ADR[0..20] ADR[0..20] ADR[0..20]
MD[0..15] MD[0..15] MD[0..15] DATA[0..15] DATA[0..15] DATA[0..15]
SMICLK SMICLK RAMCLK RAMCLK
#SMICS0 #SMICS0 #SDCS0 #SDCS0
#SMIRAS #SMIRAS #SDRAS #SDRAS

#SMICAS #SMICAS #SDCAS #SDCAS
#SMIWE #SMIWE #SDWE #SDWE
SMIDQML SMIDQML DQML DQML
SMIDQMU SMIDQMU DQMH DQMH
05-DECMEM 04-SYSMEM
FRONT PANEL FLASHROM
ADR[0..20]
FPCLK FPCLK DATA[0..15]
FPDATA FPDATA
FPSTB FPSTB
FPIR FPIR #CE3 #CE3
#OE #OE
3 SCL
#WE #WE 3
SDA #RESET #RESET
03-FLASHROM
14-FRONT PANEL RS232
AUDIO OUT
RTS RTS
#BPRESET #BPRESET CTS CTS
TXD TXD
SPDIF_OUT SPDIF_OUT RXD RXD
DAC_PCMCLK 10-RS232
DAC_SCLK DAC_SCLK
DAC_LRCLK DAC_LRCLK FRONTEND
DAC_DATA0 DAC_DATA0
DAC_DATA1 DAC_DATA1 ADR[0..20]
DAC_DATA2 DAC_DATA2
DAC_DATA DAC_DATA DATA[0..15]
SCL #FERESET #FERESET
SDA
BPPIO0 BPPIO0 #CE1 #CE1
BPPIO1 BPPIO1 R/#W R/#W
BPPIO2 BPPIO2
BPPIO3 BPPIO3 #ATAPI_WR #ATAPI_WR
11-AUDIO OUT #ATAPI_RD #ATAPI_RD
2 VIDEO OUT FEINT FEINT 2
RED RED OPEN OPEN
GREEN GREEN CLOSE CLOSE
BLUE BLUE #SENSE #SENSE
STANDBY #PUSH #PUSH
CHROMA CHROMA DATA DATA
LUMA LUMA BCLK BCLK
CVBS CVBS FLAG FLAG
12-VIDEO OUT SYNC SYNC
SEEPROM RST SCL SCL
SDA SDA
SCL 06-FRONTEND
SDA
POWER
POWERON POWERON
20-SEEPROM RST
EXTPLL
#BPRESET 22-POWER
ML ML THESE SCHEMATICS ARE PROPRIETARY AND CONFIDENTIAL
MD MD
MC MC INFORMATION OF RAVISENT Technologies Inc.
PCMCLK
1 (c) RAVISENT Technologies Inc. 1
PIXCLK PIXCLK
AUDCLK AUDCLK
09-EXTPLL 02-5508 I²C Add.:
E²PROM 0xA0 Title
RTC/WD 0xDE
NV-MEM 0xAE Production - Overview of Decoder Board
TVM502 0x30 Size Document Number Rev
A3 101559 1.1
Date: Tuesday, December 26, 2000 Sheet 1 of 16
A B C D E
AMA[0..13] B +2V5-DENC C D E
ADR[0..20]
MA[0..13] ADR[0..20]
MD[0..15] +2V5-PCM DATA[0..15] DATA[0..15]
MD[0..15]
#JTAG_RESET +2V5-PLL VCC3
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
ADR10
ADR11
ADR12
ADR13
ADR14
ADR15
ADR16
ADR17
ADR18
ADR19
ADR20
DATA0
DATA1
DATA2
DATA3
DATA4
DATA5
DATA6
DATA7
DATA8
DATA9
U1 VCC3 +2V5 R1 JUMPER3 R2
ADR1
ADR2
ADR3
ADR4
ADR5
ADR6
ADR7
ADR8
ADR9
1
4 10K 10K
POWERON 2 JP1 R347 TP1
107
136
159
184
119
149
171
198
VDD_PLL 122
ADR1 161
ADR2 162
ADR3 163
ADR4 164
ADR5 165
ADR6 166
ADR7 167
ADR8 168
ADR9 169
ADR10 170
ADR11 173
ADR12 174
ADR13 175
ADR14 176
ADR15 177
ADR16 178
ADR17 179
ADR18 180
ADR19 181
ADR20 182
ADR21 183
DATA0 141
DATA1 142
DATA2 143
DATA3 144
DATA4 145
DATA5 146
DATA6 147
DATA7 148
151
152
153
154
155
156
157
158
TC4S81F 10K
47
81
14
37
64
94
VDD_PCM 48
VDD_RGB 23
VDD_YCC 30
R3 NS U2
4
4 #SMICS0 R4 0R0 74 RAMCLK 118
R5 0R0 4
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD3
VDD2_5
VDD2_5
VDD2_5
VDD2_5
VDD2_5
VDD2_5
VDD2_5
VDD2_5
DATA8
DATA9
DATA10
DATA11
DATA12
DATA13
DATA14
DATA15
#SMICS0 75 SMICS0 RAMCLK
#SMIRAS R6 0R0 76 SMICS1 R7 0R0
#SMIRAS #SMICAS R8 0R0 77 SMIRAS CAS1/SDCS0 140 #SDCS0
#SMICAS #SMIWE R9 0R0 78 SMICAS RAS1/SDCS1 138 R10 0R0
#SMIWE SMIDQML R11 0R0 79 SMIWE RAS0/SDRAS 135 R12 0R0 #SDRAS
SMIDQML SMIDQMU R13 0R0 80 SMIDQML CAS0/SDCAS 139 R14 0R0 #SDCAS
SMIDQMU SMIDQMU R/W/SDWE 130 R15 0R0 #SDWE
SMICLK R16 0R0 95 SMICLKOUT BE0/DQML 128 R17 0R0 DQML
SMICLK 82 SMICLKIN BE1/DQMH 129 DQMH
VCC3 WAIT 131 R/#W
MA0 69 134 R18 33R #WE
MA1 68 SMIADR0 CE1 133 #CE1
R19 10K TRIGIN MA2 67 SMIADR1 CE2 132 R20 33R
R21 10K TRIGOUT MA3 66 SMIADR2 CE3 117 R22 33R #CE3
R23 10K MA4 58 SMIADR3 OE #OE
R24 10K MA5 59 SMIADR4 R25 33R
R26 10K MA6 60 SMIADR5 ATAPI_RD/PIO0_1 187 R27 33R #ATAPI_RD
R28 10K MA7 61 SMIADR6 ATAPI_WR/PIO0_2 188 #ATAPI_WR
R29 10K MA8 62 SMIADR7 127 R32 10K
MA9 63 SMIADR8 IRQ0 126 FEINT
MA10 70 SMIADR9 IRQ1 125 R30 10K FEINT
MA11 71 SMIADR10 IRQ2
J1 MA12 72 SMIADR11 57 R31 33R
MA13 73 SMIADR12 SPDIF_OUT SPDIF_OUT
2 1 SMIADR13
4 3 MD0 84 ADC_PCMCLK 106
103
6 5 MD1 85 SMIDATA0 ADC_SCLK
8 7 MD2 SMIDATA1 ADC_LRCLK 104
R36
86 R35 10K
3 10 9 MD3 87 SMIDATA2 ADC_DATA 105 3
12 11 MD4 88 SMIDATA3 33R
14 13 MD5 89 SMIDATA4 DAC_PCMCLK 55
51
R37
R38 33R AUDCLK
16 15 MD6 SMIDATA5 DAC_SCLK DAC_SCLK
R41
90 R39 33R
18 17 SMIDATA6 DAC_LRCLK 56 DAC_LRCLK
ST Microelectronics
75R
MD7 91 R40 33R

20 19 SMIDATA7 DAC_DATA0 52 R42 33R DAC_DATA0
MD8 92 DAC_DATA1 53 R43 33R DAC_DATA1
HEADER2X10 SMIDATA8 DAC_DATA2 54 R44 DAC_DATA2
75R
MD9 93 33R
PIO2_6/DAC_DATA 2
SHROUDED MD10 97
MD11 98
MD12 99
MD13100
MD14101
SMIDATA9
SMIDATA10
SMIDATA11
SMIDATA12
SMIDATA13
STi5508/80 PWM1/BOOTFROMROM 115
PWM0/HSYNC 116
PWM2/VSYNC 114
BOOTFROMROM
TP31
TP32
DAC_DATA
MD15102 SMIDATA14 120 PIXCLK

SMIDATA15 PIXCLK _27Mhz PIXCLK
#RESET 124 RESET RED
#RESET R_OUT 27 GREEN RED
TCK 113 TCK G_OUT 26
25 BLUE GREEN
TDI 112 B_OUT BLUE
TDO R45 56R 111 TDI 32 LUMA
TMS 110 TDO Y_OUT 33 CHROMA LUMA
#TRST 109 TMS C_OUT CHROMA
TRST CVBS
BPPIO0 BPPIO0 205 PARA_REQ/PIO2_1 CVBS_OUT 34 CVBS
BPPIO1 201 PARA_SYNC/PIO1_5
BPPIO1
BPPIO2 BPPIO2 206 PARA_STR/PIO2_2 YUV0/PIO4_0 39
40
TP33
TP34 R46
BPPIO3 BPPIO3 196 PARA_DVALID/PIO1_2 YUV1/PIO4_1 41 TP35 75R
YUV2/PIO4_2 42 TP36 R47 R48
OPEN 6 YUV3/PIO4_3 43 TP37 10K 10K
2 OPEN
CLOSE
CLOSE 7
8
PARA_DATA0/PIO3_0
PARA_DATA1/PIO3_1
YUV4/PIO4_4 44
YUV5/PIO4_5 45 TP38 C1 2
TP6 PARA_DATA2/PIO3_2 YUV6/PIO4_6 46 TP39 47pF
FPIR 9 TP40
FPIR TP7 10 PARA_DATA3/CAP0/PIO3_3 YUV7/PIO4_7
TP8 11 PARA_DATA4/CAP1/PIO3_4
#SENSE 12 PARA_DATA5/CAP2/PIO3_5
28 V_REF DAC RGB
29 I_REF DAC RGB

35 V_REF DAC YCC
36 I_REF DAC YCC

#SENSE #PUSH 13 PARA_DATA6/PIO3_6
#PUSH PARA_DATA7/PIO3_7
DATA R49 220R 16 207 RTS
DATA BCLK R50 220R 17 B_DATA PIO2_3 208 CTS RTS
BCLK FLAG B_BCLK PIO2_4 TXD CTS
24 VSS_RGB
31 VSS_YCC
123 VSS_PLL
49 VSS_PCM
R51 220R 18 197
FLAG B_FLAG PIO1_3/TXD2 TXD
186 PIO0_0
189 PIO0_3
190 PIO0_4
191 PIO0_5
192 PIO0_6
193 PIO0_7
202 PIO1_6
203 PIO1_7
204 PIO2_0
1 PIO2_5
PIO2_7
SYNC R52 220R 19 200 RXD

SYNC 20 B_SYNC PIO1_4/RXD2 RXD
B_WCLK/NRSS_CLK R53 SCL
5 VSS
15 VSS
38 VSS
50 VSS
65 VSS
83 VSS
96 VSS
108 VSS
121 VSS
137 VSS
150 VSS
160 VSS
172 VSS
185 VSS
199 VSS
21 B_V4/NRSS_IN PIO1_1/SCL 195 33R SCL
22 R54 33R SDA
NRRS_OUT PIO1_0/SDA 194 SDA
STi5508
or STi5580 TP9 VCC
3
R55 4K7
MC MC TP10
MD MD
TP5 R57 R58 R56 4K7
ML ML
TP11 20K0 20K0
FPCLK 1% 1%
FPCLK FPDATA C2 C3
FPDATA FPSTB 47pF 47pF
FPSTB
#SOFT_RESET
1 TP12 1
#FERESET R59 0R0 R60
#FERESET R61 NS 10K
#AUXRESET R62 0R0
R63 NS Title
#BPRESET R64 NS Production - STi5508 Core
#BPRESET R65 0R0
Size Document Number Rev
A3 101559 1.1
Ravisent Proprietary Information Date: Tuesday, December 26, 2000 Sheet 2 of 16
A B C D E
A B C D E
Firmware Flash ROM
4 4
DATA[0..15] DATA[0..15]
ADR[0..20] ADR[0..20]
VCC-FLASH
VCC 37
U3
ADR1 25 29 DATA0
ADR2 A0
24 DQ0 31 DATA1
ADR3 A1
23 DQ1 33 DATA2
ADR4 A2
22 DQ2 35 DATA3
ADR5 A3
21 DQ3 38 DATA4
ADR6 A4
20 DQ4 40 DATA5
3 ADR7 A5
19 DQ5 42 DATA6 3
ADR8 A6
18 DQ6 44 DATA7
ADR9 A7
8 DQ7
ADR10 A8
7 30 DATA8
ADR11 A9
6 DQ8 32 DATA9
ADR12 A10
5 DQ9 34 DATA10
ADR13 A11
4 DQ10 36 DATA11
ADR14 A12
3 DQ11 39 DATA12 INSTALL ZERO OHM
ADR15 A13
2 DQ12 41 DATA13
ADR16 A14
1 DQ13 43 DATA14 RESISTORS FOR INTEL
ADR17 A15
48 DQ14 45 DATA15 AND MICRON FLASH
ADR18 A16
17 DQ15/A-1
ADR19 A17
16 47 R66 SUPPORT. DO NOT
ADR20 A18/NC
9 BYTE
A19/NC 0R0 INSTALL FOR OTHER
VPP 13 R67
#CE3 26 CE 14 VENDORS.
#CE3 #OE #WP #RESET
27 VSS
46 VSS
#OE 28 OE RP 12 0R0
#WE 11 WE 15
#WE RB
FLASH_1024KX16 R68
2 or FLASH_512x16 ZERO OHM RESISTOR 2
100ns NS-0R0 REQUIRED FOR SOME
TSOP48
16MB DEVICES -
A19 ON PIN 15
#RESET
1 1
Title
Production - FLASH ROM Memory
A4 101599 1.1
A B C D E
A B C D E
Dedicated System Memory (Optional)

DATA[0..15]
DATA[0..15]
ADR[0..20]
ADR[0..20] U20/1
4 ADR1 23 2 DATA0 4
ADR2 24 A0 D0 4 DATA1
ADR9 33 A7 D7
ADR10 34 A8 42 DATA8
ADR11 22 A9 D8 44 DATA9
ADR12 35 A10 D9 45 DATA10
ADR15 21 A11 D10 47 DATA11
ADR16 20 A12_BA1 D11 48 DATA12
A13_BA0 D12 50 DATA13
#SDRAS 18 D13 51 DATA14
#SDRAS #SDCAS 17 RAS D14 53 DATA15
#SDCAS #SDWE 16 CAS D15
#SDWE #SDCS0 19 WE
#SDCS0 DQML 15 CS
DQML DQMH 39 LDQM
3 DQMH UDQM 3
RAMCLK 38 CLK
RAMCLK
VCC3 37 CKE
SDRAM_4MX16
125MHz TSOP(II)54
R69 R70 R71 R72 R73 R74 R75 3.3V
75R 75R 75R 75R 75R 75R 75R
U20/2
ADR1 21 DATA0
ADR2 22 A0 D0 2
3 DATA1
ADR3 23 A1 D1 DATA2
C4
47pF
C5
47pF
C6
47pF
C7
47pF
C8
47pF
C9
47pF
C10
47pF ADR6 28 A4 D4 8
9 DATA5
ADR7 29 A5 D5 DATA6
ADR9 31 A7 D7 12
ADR10 32 A8 DATA8
ADR11 20 A9 D8 39 DATA9
2 ADR12 19 A10 D9 40
42 DATA10 2
A11 D10 43 DATA11
17 RAS D11 DATA12
16 CAS D12 45 DATA13
15 WE D13 46
48 DATA14
18 CS D14 DATA15
14 LDQM D15 49
36 UDQM Overlap footprints
35 CLK of /1 and /2 parts
VCC3 34 CKE
NS-SDRAM_1MX16
125MHz
3.3V
TSOP(II)50_400
1 1
Title
Note: Production - System DRAM Memory
- place RC termination close to U5 A4 1.1
- route SDCLK as short as possible 101599
Ravisent Proprietary Information - 125MHz SDRAMs are required Date: Tuesday, December 26, 2000 Sheet 4 of 16
A B C D E
A B C D E
Decoder / SMI Memory

4 4
MD[0..15]
MD[0..15]
MA[0..13]
MA[0..13] U4
MA0 23 2 MD0
MA1 24 A0 D0 4 MD1
MA2 25 A1 D1 5 MD2
MA3 26 A2 D2 7 MD3
MA4 29 A3 D3 8 MD4
MA5 30 A4 D4 10 MD5
MA6 31 A5 D5 11 MD6
MA7 32 A6 D6 13 MD7
MA8 33 A7 D7
MA9 34 A8 42 MD8
MA10 22 A9 D8 44 MD9
MA11 35 A10 D9 45 MD10
MA12 21 A11 D10 47 MD11
MA13 20 A12_BA1 D11 48 MD12
3 A13_BA0 D12 50 MD13 3
#SMIRAS 18 D13 51 MD14
#SMIRAS #SMICAS 17 RAS D14 53 MD15
#SMICAS #SMIWE 16 CAS D15
#SMIWE #SMICS0 19 WE
#SMICS0 SMIDQML 15 CS
SMIDQML SMIDQMU 39 LDQM
SMIDQMU UDQM
SMICLK 38 CLK
SMICLK 37 CKE
VCC3
SDRAM_4MX16
125MHz
R76 R77 R78 R79 R80 R81 R82 3.3V
75R 75R 75R 75R 75R 75R 75R TSOP(II)54
ROUTE SMICLK IN A LOOP FROM

5508 PIN 95 TO SDRAM THEN BACK
2 C11 C12 C13 C14 C15 C16 C17 TO 5508 PIN 82 2
47pF 47pF 47pF 47pF 47pF 47pF 47pF
1 1
Title
Note: Production - Decoder SDRAM Memory
- place RC termination close to U6 A4 1.1
- route SDCLK as short as possible 101599
Ravisent Proprietary Information - 125MHz SDRAMs are required Date: Tuesday, December 26, 2000 Sheet 5 of 16
A B C D E
A B C D E
4 4
ATAPI
ADR[0..20] DATA[0..15]
ADR[0..20] ADR[0..20] DATA[0..15] DATA[0..15]
#FERESET #FERESET #FERESET
3 #CE1 3
#CE1 R/#W #CE1
R/#W R/#W
#ATAPI_WR
#ATAPI_WR #ATAPI_RD #ATAPI_WR FEINT
#ATAPI_RD #ATAPI_RD FEINT FEINT
07-ATAPI
TVM502
#FERESET DATA
#FERESET DATA BCLK DATA
SCL BCLK FLAG BCLK
SCL SDA SCL FLAG SYNC FLAG
SDA SDA SYNC SYNC
OPEN
OPEN CLOSE OPEN
CLOSE #SENSE CLOSE
#SENSE #PUSH #SENSE FEINT
#PUSH #PUSH FEINT
08-TVM502
2 2
1 1
Title
Production - Front End Options
A4 101599 1.1
Ravisent Proprietary Information
A B C D E
A B C D E
VCC VCC VCC
R83 R84 R85

10K 1K 10K
4 DATA[0..15] 4
DATA[0..15]
ADR[0..20]
ADR[0..20]
HEADER2X20
J2 SHROUDED
#FERESET 1 R86 220R ADR16
#FERESET RESET HA0 35 R87 220R ADR17
ADR19 R88 220R 37 HA1 33 R89 220R ADR18
VCC3
ADR20 R90 220R 38 CS0 HA2 36 U5
CS1 DD0 DATA0
#ATAPI_WR 23 HD0 17 DD1
2 A1 B1 18
DATA1
#ATAPI_WR #ATAPI_RD 25 IOW HD1 15 DD2
3 A2 B2 17
DATA2
#ATAPI_RD IOR HD2 13 DD3
4 A3 B3 16
DATA3
TP13 21 HD3 11 DD4
5 A4 B4 15
DATA4
29 DMARQ HD4 9 DD5
6 A5 B5 14
DATA5
DMACK HD5 7 DD6
7 A6 B6 13
DATA6
27 HD6 5 DD7
8 A7 B7 12
DATA7
TP14 32 IOCHRDY HD7 3 9 A8 B8 11
3 34 HIO16 DD8 3
PDIAG HD8 4 DD9
1
19 DIR
FEINT 31 HD9 6 DD10 OE
FEINT INTRQ HD10 8 DD11
39 HD11 10 DD12
20 VCC
DASP HD12 12 DD13
28 HD13 14 DD14
74LC245
R91
10K CSEL HD14 16 DD15
HD15 18 U6
2 2 18 DATA8
19 GND A1 B1 DATA9
GND GND 40 3 A2 B2 17
DATA10
20 KEY
22 GND GND 30 4 A3 B3 16
24 DATA11
GND GND 26 5
6 A4 B4 15
14 DATA12
7 A5 B5 13 DATA13
8 A6 B6 12 DATA14
9 A7 B7 11 DATA15
A8 B8
1
19 DIR
OE
2 R/#W R/#W 2
#CE1 #CE1 20 VCC
74LC245
1 1
Title
Production - ATAPI Interface
A4 101599 1.1
A B C D E
A B C D E
4 VCC-S J3
4
L1
1
22uH 2
C19 C18 LOCKHEADER2
C20 C21 .1uF
.1uF L2 .1uF 47uF
U7
22uH
10 OUT2
+12V +8V VCC3-S VCC-S 9 P2
J4 8 VCC1
TRAY MOTOR
2 1 7 VCC2
R333 NS
R334 0R0 4 3 R92 OPEN 6 IN2
6 5 15R C22 OPEN
8 7 1/4W .1uF CLOSE 5 IN1
10 9 CLOSE
PICOFLEX10 +8V 4 V2
3 P1
FFC10 CAN
BE STUFFED 2 OUT1
3 3
3
IN SAME 1 GND
FOOTPRINT C24 D1
C23 6.8V
.1uF 100uF LB1641
1
16V
+12V
VCC
+8V +12V VCC-S VCC3-S

J10 C25 R93 R94
1 R95 .1uF 1K
2 1 12K1 1K
8
SYNC SYNC SYNC 3 2 1%
FLAG FLAG FLAG 4 3 3
DATA DATA DATA 5 4 + 1 R96 0R0
BCLK BCLK BCLK 6 5 R97 R98 2 #SENSE
7 6 100K 7V -
#FERESET #FERESET #FERESET 8 7 0R0 U8A
FEINT FEINT FEINT 9 8 R99 0R0
4
SCL SCL SCL 10 9 R100 LM393 #PUSH
SDA SDA SDA 11 10 10K0
12 11 1%
13 12
2 14
15
13
14 in1, in2, out1, out2 2
16 15 pin5, pin6, pin2, pin10
17 16 0, 0, 0, 0 (idle)
18 17
R102 0R0 19 18 R101 U8B 0, 1, 0, 1 (open)
R103 NS 19
1, 0, 1, 0 (close)
8
5K6 LM393
TRAY MOTOR FFC19 5 1, 1, 0, 0 (brake)
+ 7
6 * Tray motor must be in
FFC12 CAN - idle state for push
TVM DRIVE TRAY MOTOR POWER BE STUFFED
IN SAME R104
4 sense to operate
TVM502A --> 12V FOOTPRINT 10K C26
TVM502B --> 8V .1uF
3
1 1
SOT23
6V8
1 2 Title
Production - TVM502 Drive Interface
A3 101599 1.1
A B C D E
A B C D E
Stuffed, if no ext.
PLL is used
VCC
4 OSC1 4
1 NC VCC 8
4 GND CLK 5
27MHz
Optional for better SPDIF support
VCC R346 CAN BE INSTALLED INSTEAD OF
VCC3 U10 FOR APPLICATIONS WITH NO BACK
R105
33R PANEL
VDD3 16
U9
VDD 3
VDDPLL 8
#BPRESET 18 R106 PIXCLK
#BPRESET RESET MCK0 10 PIXCLK
ML 1 ML/SR0 NS
ML MD 19 MD/FS0 MCK0 11 R107
3 MD MC 20 MC/FS1
3
MC U10-1 0R0 R109
C27 5 XT2 NS
R108 NS AUDCLK
33pF Y1 SCKO1 12 R110 NS
1 7 AUDCLK
256fs 7W34
27MHz SCKO2 14 R346
GNDPLL
C28 6 XT1 R111 NS NS
384fs R112 NS U10-3
SCKO3 17
GND
15 GND
33pF 2 MODE
9 NC 768fs R113 NS PCMCLK
SCKO4 13 3 5 PCMCLK
R115 PLL1700 7W34 R114
0R0 VCC3 0R0
4
7
U11
R116
PR 7
2 D R117
R118 NS Q 5
2 NS 1 CLK NS 2
Stuffed, if ext.
CL
PIXCLK source Q 3
6
NS-TC7W74FU
Stuffing options for

back panel DACs
1 1
Title
Production - System and Audio Clocks
A4 101599 1.1
A B C D E
A B C D E
4 4
VCC
U12 DB9 PINOUT
1 C1+ VCC 16 (FEMALE)
3 C29 C30 TXD
RXD
:
:
2
3
3
.1uF .1uF CTS : 7
3 C1- GND 15 RTS : 8
4 C2+ V+ 2 GND : 5
C31 C32
.1uF .1uF
5 C2- V- 6
11 TIN1 TOUT1 14 TXD_B J7
TXD 10 TIN2 TOUT2 7 RTS_B
RTS 1 2
12 ROUT1 RIN1 13 RXD_B 3 4
RXD 9 ROUT2 RIN2 8 CTS_B 5 6
CTS 7 8
MAX232 9 10
HEADER2X5
SHROUDED
2 R119 NS 2
R120 NS
R121 NS
R122 NS
1 1
Title
Production - RS232 Transceiver
A4 101599 1.1
A B C D E
A B C D E
BACK PANEL PIO FUNCTIONS
SIGNAL HIGH/LOW
BPPIO0 -- 4:3/16:9
VCC
BPPIO1 -- POWER/STANDBY J11
4 BPPIO2 -- #BPRESET 4
#BPRESET 1
BPPIO3 -- SPDIF_OUT SPDIF_OUT 2
3
DAC_DATA DAC_DATA 4
5
DAC_PCMCLK DAC_PCMCLK 6
7 PLAYER REAR
DAC_SCLK DAC_SCLK 8
DAC_LRCLK DAC_LRCLK 9 PANEL
DAC_DATA0 DAC_DATA0 10 CONNECTOR
DAC_DATA1 DAC_DATA1 11
DAC_DATA2 DAC_DATA2 12
13
R123 BPPIO0 BPPIO0 14
DAC_DATA0 BPPIO1 BPPIO1 15
BPPIO2 BPPIO2 16
0R0 BPPIO3 BPPIO3 17
SCL SCL 18
R124 SDA SDA 19
DAC_DATA 20
3 FFC20
3
NS
J12
VCC-PCM TV/DVD
C33 R125 1 SPDIF
2 OUTPUT
LOCKHEADER2
VA 7
U13 10uF 562R C34

SDATA 1 SDATA AOUTL 8 ELCO
16V
R126 1%
100K 1500pF J13
DAC_SCLK 2 SCLK 1%
DAC_LRCLK 3 LRCLK LEFT TV/DVD
1
AGND
DAC_PCMCLK 4 MCLK RIGHT 2 AUDIO

3
AOUTR 5 OUTPUT
LOCKHEADER3
CS4335 C35 R128
R127
6
2 75R 2
10uF 562R C36
ELCO R129 1%
C37 16V 100K 1500pF
1%
47pF
1 1
Title
Production - Audio Output
A4 101599 1.1
A B C D E
A B C D E
VCC3 +12V +8VA -8VA +5VA

J14
1
E 2 E
3
4
5
6
VIDEOFILTER 7
RED RED_OUT 8 PLAYER
RED RED RED_OUT 9
GREEN GREEN_OUT 10 REAR
GREEN GREEN GREEN_OUT 11 PANEL
BLUE BLUE_OUT 12
BLUE BLUE BLUE_OUT 13
CHROMA CHROMA_OUT 14
CHROMA CHROMA CHROMA_OUT 15
LUMA LUMA_OUT 16
LUMA LUMA LUMA_OUT 17
D CVBS CVBS_OUT 18 D
CVBS CVBS CVBS_OUT 19
13-VIDEO AMP 20
FFC20
J15
+12V 1
2
3
4
5 DVD/TV
6
R130 7 OUTPUT
10K 8
C 9 C
R131 2 Q1 10
BC848BL 1 BC858BL LOCKHEADER10
R132 Q2 3
3 10K R336
STANDBY 1
2
10K R133
100R
10K
B SOT23 B
858
3
1 2
SOT23
848
1 2
A Title
A
Production - Video Outputs
A4 101599 1.1
A B C D E
A B C D E
NS R134 NS R135
VCC-DENC VCC-DENC
C38 R136 C39 C40 R137 C41

8R2 8R2
3300pF .1uF 3300pF .1uF
4 R138 R139 4
825R R140 825R R141
1% 12R1 1% 12R1
TP15 1% TP16 1%
C42 2 Q3 TP17 C43 2 Q4 TP18
RED 2N2907 CHROMA 2N2907
1 L3 1 L4
100uF 3 100uF 3
16V RED_OUT 16V CHROMA_OUT
R142 R143 2.7uH R144 R145 2.7uH
200R 2K21 R146 C44 C45 200R 2K21 R147 C46 C47
1% 1% 75R0 1% 1% 75R0
1% 390pF 390pF 1% 390pF 390pF
NS R148 NS R149
VCC-DENC VCC-DENC
3 3
C48 R150 C49 C50 R151 C51
8R2 8R2
3300pF .1uF 3300pF .1uF
R152 R153
825R R154 825R R155
1% 12R1 1% 12R1
TP19 1% TP20 1%
C52 2 Q5 TP21 C53 2 Q6 TP22
GREEN 2N2907 LUMA 2N2907
1 L5 1 L6
100uF 3 100uF 3
16V GREEN_OUT 16V LUMA_OUT
R156 R157 2.7uH R158 R159 2.7uH
200R 2K21 R160 C54 C55 200R 2K21 R161 C56 C57
1% 1% 75R0 1% 1% 75R0
1% 390pF 390pF 1% 390pF 390pF
NS R162 NS R163
2 2
VCC-DENC VCC-DENC
C58 R164 C59 C60 R165 C61 3

8R2 8R2
3300pF .1uF 3300pF .1uF
SOT23
R166 R167 2907
825R R168 825R R169
1% 12R1 1% 12R1
TP23 1% TP24 1% 1 2
C62 2 Q7 TP25 C63 2 Q8 TP26
BLUE 2N2907 CVBS 2N2907
1 L7 1 L8
100uF 3 100uF 3
16V BLUE_OUT 16V CVBS_OUT
R170 R171 2.7uH R172 R173 2.7uH
200R 2K21 R174 C64 C65 200R 2K21 R175 C66 C67
1% 1% 75R0 1% 1% 75R0
1% 390pF 390pF 1% 390pF 390pF
1 1
Title
Production - Video Buffers / Filters
A3 101599 1.1
A B C D E
A B C D E
4 4
IR1
TSOP1840
VCC
OUT
GND
VCC
VCC
R337
100R
1
2
3
R338 R339 R340 R341
4K7 4K7 4K7 4K7
C152
3 FPIR 10uF 3
FPIR 16V
ELCO
FPDATA R342 0R0 R343 0R0
FPDATA FPCLK R344 0R0
FPCLK FPSTB R345 0R0
FPSTB
C153 VCC
NS J16
C154 1
NS 2
C155 3
4
NS-47pF 5
6
LOCKHEADER6
2 2
VCC
J17
SCL SCL 1 I2C HEADER

SDA SDA 2
3
4
LOCKHEADER4
1 1
Title
Production - Front Panel
A4 101599 1.1
A B C D E
A B C D E
4 4
U14
SCL SCL 6 SCL A0 1
SDA SDA 5 SDA A1 2
A2 3
WC 7
24C02
3-5V
VCC VCC
R335
VCC 1K
U15 R178
NS-0R0
SDA 5
SCL 6 SDA VCC 8
SCL
RESET 3
1 NC/XIN
WP/VBACK 7
4
3 2 NC/XOUT GND R179 3
0R0
NS-X4043
VCC
C70
NS-.1uF
U16
3 MR VCC 4
1 GND RST 2
NS-TC1270
2 VCC 2
C71
R180 .1uF
PUSHBUTTON SWITCH 10K
1 4 U17
S1
1 MR RESET 8
1 3
2 VCC RESET 7 POWERON
2 4
JP7 3 GND NC 6
JUMPER2 R181
2 3 4 PFI PFO 5 10K
PINS 1 AND 2 ARE CONNECTED
INTERNALLY ADM707
PINS 3 AND 4 ARE CONNECTED
INTERNALLY
VCC
U20
2 VCC
1
1 3 GND RST 1
DS1812
3
SOT23 Title
DS1812
Production - Serial EEPROM and Reset
1 2
Ravisent Proprietary Information A3 101599 1.1
A B C D E
A B C D E
NS-NDS8934 VCC-S ST-LD1117
Q9-1 VCC U18 SOT223 +2V5
4
J8 VCC VCC3 +12V -8VA +8VA 2 7 NS-NDS8934 VCC3-S LINEAR TECH 3 VI VO 2
GND
Q9-2 DESIGNED OUT
+5V 1 8 4 5 - USE ST OR SOT-223 TAB 4 C73 C74
1 LD1117 C72
NATIONAL .1uF
1
+3.3V 3 6 10uF .1uF
2 1 2 3 16V
+3.3V 3
4 +12V
U19
TMM DRIVE SUPPLY +8V 4
GND 4 R182 R183 2 1 VI VO 3
GND
GND 0R0 0R0 C76 C77
5
DPAK C75 78M08
+12V 78M08 .1uF DPAK
2
6 100uF .1uF
16V
-8VA 7 1 3
C78 C79 C80 C81 C82 C83 C84 C85 C86 C87
+8VA 8
100uF .1uF 100uF .1uF 100uF .1uF 100uF .1uF 100uF .1uF ALTERNATE PACKAGE FOR HIGH CURRENT
16V 16V
16V 16V 16V +12V +5VA
VCC
JP8 U21/1
FPPWD 1 VI
FPPWD VO 3
GND
JUMPER2
TO-220
U1 U5 U6 U7 & U8 U4 7805
STi5508/80 SDRAM-EMI SDRAM-SMI 74LVT16245 Flash ROM U10 NS-7805
2
PLL TO-220
3 VCC3 +2V5 +2V5 VCC3 VCC3 VCC3 VCC VCC-FLASH
VCC
1 2 3
3
C88 C89 C90 C91 C92 C93 R186
4 14 149 1 1 20 C94 C95
NS 37 3
.1uF .1uF .1uF .1uF .1uF .1uF 2 U21/2 ANALOG 5V
C96 C97 C98 C99 C100 C101 .1uF NS-.1uF
C102 1 VI VO 3
GND
47 37 171 14 14 20 C103 8 DPAK C105
.1uF .1uF .1uF .1uF .1uF .1uF 37 78M05
C107 C108 C109 C110 C111 NS-.1uF 78M05
C104 C106
2
C112 .1uF C113 DPAK 100uF
81 64 198 27 27 1 3 .1uF .1uF
16V
C114
.1uF .1uF .1uF .1uF .1uF 10uF 32 NS-10uF
C115 C116 C117 C118 C119 ELCO ELCO
107 94 3 3 16V VCC3 .1uF 16V
10uF R187 C120 VCC3
.1uF .1uF ELCO .1uF .1uF R188
C121 C122 16V C123 C124
136 119 9 9 0R0 10uF C125 0R0
ELCO 16
.1uF .1uF .1uF .1uF 16V
C126 C127 C128 NS-.1uF
159 43 43 C129
2 VCC VDD VCC3 VDD3 2
.1uF .1uF .1uF NS-10uF
C130 C131 C132 ELCO
184 49 49 16V
.1uF .1uF .1uF GND VSS
C133 C134 C135
L9 +2V5-PLL
10uF 10uF 10uF
ELCO C137 ELCO ELCO GNDA VSSA
16V 22uH 22uF 16V 16V
C136
ELCO
.1uF 16V U3 OSC1 U11 U13 U2
TC4S81F Oscillator TC7W34F MAX232 CS4335 +5VA VCC-DENC
GND PROBES L13
TP27 L11 +2V5-PCM VCC3 VCC VCC3 VCC VCC VCC-PCM
TP28 NS-22uH C156
TP29 C138 C139 C140 C141 L12 C142 NS-10uF
TP30 C144 R348 ELCO
22uH 22uF 5 14 8 16 7 16V
C143 22uH
ELCO 0R0
.1uF 16V .1uF .1uF .1uF .1uF .1uF
U2 C145 +5VA C146
1 MOUNTING HOLES
MH1 I2C U39 U12 L10 Ravisent Proprietary Information 1
MH2 L14 +2V5-DENC EEPROM EEPROM/POR TC7W74F 10uF 10uF
MH3 ELCO NS-22uH ELCO
MH4 16V 16V
MH5 C148 VCC VCC VCC3
MH6 22uH 22uF C149 C150 C151 Title
C147
ELCO 8 8 Production - Power Supply and Decoupling
.1uF 16V
.1uF .1uF .1uF A3 101599 1.1
A B C D E

11AK46 Full TV+DVD SCH+SM 66p

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CONTENTS

- The figure of PERI-TV socket-

1 Audio right output 0.5Vrms / 1K

2.1 Vision IF amplifier3

2.2 QSS Sound circuit (QSS versions)

2.4 FM demodulator and audio amplifier :

2.5 Video switching

2.6 Synchronization circuit

2.7 Chroma and luminance processing:

2.8 RGB output circuit:

The main functions of the video part are:

Channel coverage of UV1316:

OFF-AIR CHANNELS CABLE CHANNELS

(1). Enough margin is available to tune down to 45.25 MHz.

Noise Typical Max. Gain Min. Typical Max.

BAND CHANNELS FREQUENCY

5. SOUND OUTPUT STAGE TDA7496

6. VERTICAL OUTPUT STAGE WITH TDA8174A

7. VIDEO OUTPUT DISCRETE AMPLIFIERS

8. POWER SUPPLY (SMPS)

10. SERIAL ACCESS CMOS 8K EEPROM 24C08

12. SAW FILTERS

Saw filter type: Model:

IC DESCRIPTIONS AND INTERNAL BLOCK DIAGRAM

General description of UV1316:

PINNING PIN VALUE

1. Gain control voltage (AGC) :4.0V, Max:4.5V

General description of UV1336:

1. Gain control voltage :4.0V, Max:4.5V

-5+5W OUTPUT POWER

PINNING PIN VALUE

• Integrated start–up current source

PINNING PIN VALUE

PINNING PIN VALUE

1. Write protect enable :0V

Saw filter’s list:

PAL II' J1981

PSBGDKK' II' K3958M K9356

2 IF1 IF Coarse Adjust

BIT-7 NOT USED

BIT-6 1, Display “AV-3” as “F-AV”

OP2 – Reception Standard Options

BIT-7 1, 3-button keyboard (V-, P+, V+)

BIT-1 RESERVED (Keep as "0")

BIT-0 1, WFI available

OP3 – Video Options

BIT-7 Xtal Configuration

BIT-7 1, Headphone is available (for STEREO models)

BIT-1 1, 3-band tuning (VHF1, VHF3, UHF)

OP5 – Channel Tables

BIT-7 1, Extra 150 msec blanking more for VST

BIT-4 1, French OS Channel Table is available

TX1 – Teletext Options

BIT-7 NOT USED

BIT-6 RESERVED (must be 0)

BIT-4 000, Group 1 – West

BIT-3 (English, French, Swedish, Czech, German, Portuguese, Italien, Rumanian)

BIT-2 2 1 0 Device type selection

AK46/TITANIUM – Languages Groups

1. CHANGE HISTORY .................................................................................................................... 4

2.4 FRONT PANEL

2.5 REAR PANEL

ATAPI Drive Interface J23

TMM Tray Connector J5

TMM Tray Connector J5

TMM Power Connector J6

TMM FFC19 Connector J8

Table 8 TMM FFC19 Connector J8

JTAG Programming Interface J2

Table 9 JTAG Programming Interface J2

RS232 Serial Port Header J9

Table 10 RS232 Serial Port Header J9

Digital YUV Output Header J20

Analog Video Input Header J19

SCART Connectors J10