Lecture on Flip-Flops

Level-Sensitive Flip-Flop
• Level-sensitive flip-flop (also called a “latch”)
• “Q” changes whenever clock is “high”
CLK

D Q

6 Transistors
CLK

CLK

Q
 Level-Sensitive Flip-Flop
CLK
• NMOS transistor often
replaced with D Q
“transmission gate”

• “Transmission gate”
includes both NMOS and 6 Transistors
CLK
PMOS transistors because
NMOS good at passing “0”
CLK
and PMOS good at
passing “1” D Q
CLK
CLK
CLK
Transmission
Gate

8 Transistors
CLK
CLK
 Master-Slave Edge-Triggered Flip-Flop
• Can connect two level-sensitive latches in Master-Slave
configuration to form edge-triggered flip-flop
• Master latch “catches” value of “D” at “QM” when CLK is low
• Slave latch causes “Q” to change only at rising edge of CLK
QM
D Q
Master Slave
Latch Latch
CLK 2 x 8 = 16 Transistors
CLK

CLK

QM

Q
 Master-Slave Edge-Triggered Flip-Flop

MASTER SLAVE

QM
D Q

CLK

CLK

2 x 8 = 16 Transistors
 More Efficient Master-Slave
Edge-Triggered Flip-Flop
• Called a C2MOS (Clocked CMOS) design
MASTER SLAVE
VDD VDD

CLK CLK

D Q

CLK CLK

8 Transistors
GND GND
 Using Logic Gates to Build Flip-Flops
• From previous slides, you can see that it’s possible to
build an edge-triggered flip-flop using just 8 transistors

• In a conventional “Digital Logic” course, transistor-level

flip-flop designs are not usually taught

• Instead, flip-flop designs using “cross-coupled” logic

gates are usually taught
 RS-Latch as Cross-Coupled NOR Gates
• If R = 1, Q resets to 0
R
• If S = 1, Q sets to 1 Q

• If RS = 00, no change
• RS = 11 is not allowed
Q
because leads to S

oscillation

SR Q
00 No change
01 0
10 1
11 Undefined
 Level-Sensitive RS-Latch
• “Q” only changes when CLK is high (i.e. level-sensitive)
• When CLK is high, behavior same as RS latch
S
Q

CLK

Q
R

CLK SR Q
0 XX No change
1 00 No change
1 01 0
1 10 1
1 11 Undefined
 Level-Sensitive D-Latch
• Make level-sensitive D-latch from level-sensitive RS-latch
by connecting S = D and R = not D
D
Q

CLK

Q 18 Transistors

• Compared to transistor version

CLK

D Q
CLK
CLK 8 Transistors

CLK
 Master-Slave Edge-Triggered Flip-Flop
• Master-Slave configuration
MASTER SLAVE
D

CLK

CLK 36 Transistors
• Compared to transistor version
VDD VDD

CLK CLK
D Q
CLK CLK
8 Transistors
GND GND
 Alternative Edge-Triggered Flip-Flop
VDD VDD

Q CLK CLK

D Q
CLK
CLK CLK
Q

GND GND
D

24 Transistors 8 Transistors
 JK Flip-Flop from D-Latch
• Same as RS-Latch except “toggle” on 11

Q
D
K
Latch
Q
CLK

J Q CLK JK Q
0 XX No change
CLK JK-FF
1 00 No change
K 1 01 0
1 10 1
1 11 Toggle
 Toggle Flip-Flop from D-Latch
• Toggles stored value if T = 1 when CLK is high

Q
T D
Latch
CLK

T Q CLK T Q
0 X No change
T-FF
1 0 No change
CLK 1 1 Toggle