Answer All Questions

PART A – (10 x 2 = 20 Marks)

1. Define SSI, MSI, LSI and VLSI.

2. Compare CMOS and Bipolar technology.
3. List out the advantages of SOI process?
4. Define rise time and fall time.
5. Define body effect? Which parameters are responsible for it?
6. Briefly summaries RTL?
7. Define port and name all ports.
8. Differentiate between full custom and cell based ASICs.
9. Which MOS can pass logic 1 and logic 0 strongly?
10. Define PLD.

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PART – B [5 x 16 = 80 Marks]

11. (a) Discuss the steps involved in IC fabrication process. (16)

(OR)

(b) Differentiate the p-well CMOS process from n-well CMOS process. Explain
the n-well CMOS process to fabricate the n-switches. (16)

12. (a) (i) Explain channel length modulation and body effect. (8)
(ii) Write a note on MOS models. (8)

(OR)

(b) Discuss the origin of latch up problems in CMOS circuits with necessary
diagrams. Explain the remedial measures. (16)

13. (a) Explain the following statements in detail with examples:

(a) Procedural assignments
(b) Conditional statements
(c) Data flow continuous assignment statement (16)

(OR)

(b) (i) Write a program for comparator using verilog HDL. (8)
(ii) Write a program for encoder using verilog HDL. (8)

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14. (a) (i) Explain the Field programmable gate array with the architecture and logic
blocks. (10)
(ii) . Draw the physical layout for the following Boolean expression
y = (a +b)’ + c + de (6)

(OR)

(b) With neat diagrams explain the different types of ASICS. (16)

15.(a) (i) Draw and explain the design flow of an ASIC. (12)
(ii) Give the application of PLA. (4)

(OR)

(b) (i) Explain the programmable ASIC interconnect. (8)

(ii)Write a verilog description to design Flip Flops( JK, D, T). (8)

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