ABSTRACT

Asynchronous design styles have been increasing in popularity as device sizes shrink and
concurrency is exploited to increase system performance. However, asynchronous designs are
difficult to implement correctly because the presence of hazards, which are of little consequence
to most parts of synchronous systems, can cause improper circuit operation. Many asynchronous
design styles, together with accompanying automated synthesis algorithms, address the issues of
design complexity and correctness. Typically, these synthesis systems take a high-level
description of an asynchronous system and produce a logic-level description of the resultant
design that is hazard-free for transitions of interest. The designer then must manually translate
this logic-level description into a technologyspecific implementation composed of an
interconnection of elements from a semi-custom cell library. At this stage, the designer must be
careful not to introduce new hazards into the design. The size of designs is limited in part by the
inability to safely (and reliably) map the technology-independent description into an
implementation. In this thesis, we address the problem of technology mapping for two different
asynchronous design styles. We first addressed the problem for burst-mode designs. We
developed theorems and algorithms for hazard-free mapping of burst-mode designs, and
implemented these algorithms on top of an existing synchronous technology mapper. We
incorporated this mapper into a toolkit for asynchronous design, and used the toolkit to
implement a low-power infrared communications chip. We then extended this work to apply to
the problem of hazard-free technology mapping of speed-independent designs. The difficulty in
this design style is in the decomposition phase of the mapping algorithm, and we developed
theory and algorithms for correct hazard-free decomposition of this design style. We also
developed an exact covering algorithm which takes advantage of logic sharing within the design.
These algorithms were implemented within the burstmode technology mapper to produce a
technology mapper suitable for speed-independent designs.