projeto_digital.

vhd Tue Dec 14 10:02:56 2010

1 ----------------------------------------------------------------------------------
2 -- Company:
3 -- Engineer:
4 --
5 -- Create Date: 14:59:20 12/10/2010
6 -- Design Name:
7 -- Module Name: projeto_digital - Behavioral
8 -- Project Name:
9 -- Target Devices:
10 -- Tool versions:
11 -- Description:
12 --
13 -- Dependencies:
14 --
15 -- Revision:
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
18 --
19 ----------------------------------------------------------------------------------
20 library IEEE;
21 use IEEE.STD_LOGIC_1164.ALL;
22
23 -- Uncomment the following library declaration if using
24 -- arithmetic functions with Signed or Unsigned values
25 --use IEEE.NUMERIC_STD.ALL;
26
27 -- Uncomment the following library declaration if instantiating
28 -- any Xilinx primitives in this code.
29 --library UNISIM;
30 --use UNISIM.VComponents.all;
31
32 entity projeto_digital is
33 port(B0 : in std_logic;
34 B1 : in std_logic;
35 B2 : in std_logic;
36 B3 : in std_logic;
37 A : in std_logic;
38 clk50MHz : in std_logic;
39 disp : out bit_vector(6 downto 0);
40 an : out bit_vector(3 downto 0);
41 leds : out bit_vector(7 downto 0));
42
43
44 end projeto_digital;
45
46 architecture Behavioral of projeto_digital is
47 --signal M0: std_logic;
48 --signal M1: std_logic;
49 signal D : std_logic:='0';
50 signal mux1: std_logic_vector(1 downto 0);
51 signal mux2: integer range 0 to 40000;
52 signal clk : std_logic;
53 signal I : std_logic;
54 signal C : std_logic;
55 signal T : std_logic;
56 signal Digito: std_logic_vector(1 downto 0);
57 type stateT is (q0,q1,q2,q3,q4,q5,q6,q7,q8,q9,q10,q11,q12,q13,q14,q15,q16,q17,q18,q19,

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q20);
58 signal aponta : integer range 0 to 3;
59 signal E : std_logic;
60 signal bt0 : std_logic;
61 signal bt1 : std_logic;
62 signal bt2 : std_logic;
63 signal bt3 : std_logic;
64 signal state :stateT:=q0;
65 signal m: std_logic_vector(1 downto 0);
66
67 begin
68
69
70
71 with m select
72 mux1<= "00" when "00",
73 "01" when "01",
74 "10" when "10",
75 "11" when others;
76
77 E<= '1' when mux1=digito else '0';
78
79
80
81
82 with I select
83 mux2<= 0 when '0',
84 40000 when others;
85
86
87
88 --Clock 10khz
89 process(clk50MHz)
90 variable cont : integer range 0 to 4999;
91 begin
92 if (clk50MHz'event and clk50MHz = '1')then
93 cont := cont + 1;
94 if cont = 4999 then
95 clk <='1';
96 cont := 0;
97 else
98 clk <= '0';
99 end if;
100 end if;
101 end process;
102
103 --Contador
104 process(clk)
105 variable cont : integer range 0 to 49999;
106 begin
107 if rising_edge(clk) then
108 if C='0' then
109 cont := mux2;
110 T <= '0';
111 else
112 if cont= 49999 then
113 T <= '1';

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114 cont := mux2;
115
116 else
117 cont := cont+1;
118 T<='0';
119 end if;
120 end if;
121 END IF;
122 end process;
123
124
125 --Debounce
126 process(clk)
127 variable vet:std_logic_vector (3 downto 0):="0000";
128 variable cont1 : integer range 0 to 19;
129 begin
130 if (clk'event and clk='1') then
131 if cont1=19 then
132 vet:=B0&vet(3 downto 1);
133 if vet = "1111" then
134 bt0 <='1';
135 else
136 bt0<='0';
137 end if;
138 end if;
139 cont1:= cont1 +1;
140 end if;
141 end process;
142
143 process(clk)
144 variable vet:std_logic_vector (3 downto 0):="0000";
145 variable cont1 : integer range 0 to 19;
146 begin
147 if (clk'event and clk='1') then
148 if cont1=19 then
149 vet:=B1&vet(3 downto 1);
150 if vet = "1111" then
151 bt1 <='1';
152 else
153 bt1<='0';
154 end if;
155 end if;
156 cont1:= cont1 +1;
157 end if;
158 end process;
159
160 process(clk)
161 variable vet:std_logic_vector (3 downto 0):="0000";
162 variable cont1 : integer range 0 to 19;
163 begin
164 if (clk'event and clk='1') then
165 if cont1=19 then
166 vet:=B2&vet(3 downto 1);
167 if vet = "1111" then
168 bt2 <='1';
169 else
170 bt2<='0';

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171 end if;
172 end if;
173 cont1:= cont1 +1;
174 end if;
175 end process;
176
177 process(clk)
178 variable vet:std_logic_vector (3 downto 0):="0000";
179 variable cont1 : integer range 0 to 19;
180 begin
181 if (clk'event and clk='1') then
182 if cont1=19 then
183 vet:=B3&vet(3 downto 1);
184 if vet = "1111" then
185 bt3 <='1';
186 else
187 bt3<='0';
188 end if;
189 end if;
190 cont1:= cont1 +1;
191 end if;
192
193 end process;
194
195 --Botao sensivel a borda de subida
196 process(clk)
197 variable bt0a,bt1a,bt2a,bt3a : std_logic:='0';
198 begin
199 if (clk'event and clk='1') then
200 D <= '0';
201 Digito <= "00";
202 if bt0a='0' and bt0='1' then
203 D <='1';
204 Digito <="00";
205 elsif bt1a='0' and bt1='1' then
206 D <='1';
207 Digito <="01";
208 elsif bt2a='0' and bt2='1' then
209 D <='1';
210 Digito <="10";
211 elsif bt3a='0' and bt3='1' then
212 D <='1';
213 Digito <="11";
214 end if;
215 bt0a:=bt0;
216 bt1a:=bt1;
217 bt2a:=bt2;
218 bt3a:=bt3;
219 end if;
220 end process;
221
222
223
224 --Display
225 process(clk)
226 variable cont: integer range 0 to 20;
227 begin

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228 if (clk'event and clk='1') then
229 if cont=19 then
230 if aponta=3 then
231 aponta <=0 ;
232 else
233 aponta <= aponta +1;
234 end if;
235 cont := 0;
236 else
237 cont:= cont +1;
238 end if;
239 end if;
240 end process ;
241 an <= "1110" when aponta = 0 else
242 "1101" when aponta = 1 else
243 "1011" when aponta = 2 else
244 "0111";
245
246 process(state,aponta)
247 begin
248 case state is
249 when (q0) =>
250 case aponta is
251 when 3 => disp <= "0010010"; --S
252 when 2 => disp <= "0000110"; --E
253 when 1 => disp <= "0101011"; --N
254 when 0 => disp <= "0001001"; --H
255 end case;
256
257 when (q1) =>
258 case aponta is
259 when 3 => disp <= "0000000"; --8
260 when 2 => disp <= "0111111"; --_
261 when 1 => disp <= "0111111"; --_
262 when 0 => disp <= "0111111"; --_
263 end case;
264
265 when (q2) =>
266 case aponta is
267 when 3 => disp <= "0000000"; --8
268 when 2 => disp <= "0111111"; --_
269 when 1 => disp <= "0111111"; --_
270 when 0 => disp <= "0111111"; --_
271 end case;
272
273 when (q3) =>
274 case aponta is
275 when 3 => disp <= "0000000"; --8
276 when 2 => disp <= "0000000"; --8
277 when 1 => disp <= "0111111"; --_
278 when 0 => disp <= "0111111"; --_
279 end case;
280
281 when (q4) =>
282 case aponta is
283 when 3 => disp <= "0000000"; --8
284 when 2 => disp <= "0000000"; --8

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285 when 1 => disp <= "0111111"; --_
286 when 0 => disp <= "0111111"; --_
287 end case;
288
289 when (q5) =>
290 case aponta is
291 when 3 => disp <= "0000000"; --8
292 when 2 => disp <= "0000000"; --8
293 when 1 => disp <= "0000000"; --8
294 when 0 => disp <= "0111111"; --_
295 end case;
296
297 when (q6) =>
298 case aponta is
299 when 3 => disp <= "0000000"; --8
300 when 2 => disp <= "0000000"; --8
301 when 1 => disp <= "0000000"; --8
302 when 0 => disp <= "0111111"; --_
303 end case;
304
305 when (q7) =>
306 case aponta is
307 when 3 => disp <= "0000000"; --8
308 when 2 => disp <= "0000000"; --8
309 when 1 => disp <= "0000000"; --8
310 when 0 => disp <= "0000000"; --8
311 end case;
312
313 when (q8) =>
314 case aponta is
315 when 3 => disp <= "0000000"; --8
316 when 2 => disp <= "0000000"; --8
317 when 1 => disp <= "0000000"; --8
318 when 0 => disp <= "0000000"; --8
319 end case;
320
321 when (q9) =>
322 case aponta is
323 when 3 => disp <= "0000110"; --E
324 when 2 => disp <= "0101111"; --r
325 when 1 => disp <= "0101111"; --r
326 when 0 => disp <= "0100011"; --o
327 end case;
328
329 when (q10) =>
330 case aponta is
331 when 3 => disp <= "0000000"; --8
332 when 2 => disp <= "0111111"; --_
333 when 1 => disp <= "0111111"; --_
334 when 0 => disp <= "0111111"; --_
335 end case;
336
337 when (q11) =>
338 case aponta is
339 when 3 => disp <= "0000000"; --8
340 when 2 => disp <= "0111111"; --_
341 when 1 => disp <= "0111111"; --_

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342 when 0 => disp <= "0111111"; --_
343 end case;
344
345 when (q12) =>
346 case aponta is
347 when 3 => disp <= "0000000"; --8
348 when 2 => disp <= "0000000"; --8
349 when 1 => disp <= "0111111"; --_
350 when 0 => disp <= "0111111"; --_
351 end case;
352
353 when (q13) =>
354 case aponta is
355 when 3 => disp <= "0000000"; --8
356 when 2 => disp <= "0000000"; --8
357 when 1 => disp <= "0111111"; --_
358 when 0 => disp <= "0111111"; --_
359 end case;
360
361 when (q14) =>
362 case aponta is
363 when 3 => disp <= "0000000"; --8
364 when 2 => disp <= "0000000"; --8
365 when 1 => disp <= "0000000"; --8
366 when 0 => disp <= "0111111"; --_
367 end case;
368
369 when (q15) =>
370 case aponta is
371 when 3 => disp <= "0000000"; --8
372 when 2 => disp <= "0000000"; --8
373 when 1 => disp <= "0000000"; --8
374 when 0 => disp <= "0111111"; --_
375 end case;
376
377 when (q16) =>
378 case aponta is
379 when 3 => disp <= "0000000"; --8
380 when 2 => disp <= "0000000"; --8
381 when 1 => disp <= "0000000"; --8
382 when 0 => disp <= "0000000"; --8
383 end case;
384
385 when (q17) =>
386 case aponta is
387 when 3 => disp <= "0000000"; --8
388 when 2 => disp <= "0000000"; --8
389 when 1 => disp <= "0000000"; --8
390 when 0 => disp <= "0000000"; --8
391 end case;
392
393 when (q18) =>
394 case aponta is
395 when 3 => disp <= "1000110"; --C
396 when 2 => disp <= "0100011"; --o
397 when 1 => disp <= "0101111"; --r
398 when 0 => disp <= "0101111"; --r

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399 end case;
400
401 when (q19) =>
402 case aponta is
403 when 3 => disp <= "1000110"; --C
404 when 2 => disp <= "0100011"; --o
405 when 1 => disp <= "0101111"; --r
406 when 0 => disp <= "0101111"; --r
407 end case;
408
409 when (q20) =>
410 case aponta is
411 when 3 => disp <= "0001000"; --A
412 when 2 => disp <= "0000011"; --b
413 when 1 => disp <= "0101111"; --r
414 when 0 => disp <= "0000110"; --E
415 end case;
416
417
418
419 end case;
420 end process;
421
422 --FSM Controlador
423 process(clk)
424 begin
425 if (clk'event and clk ='1') then
426 case state is
427 when q0 =>
428 if D='1' and E='0' and T='0' then
429 state <= q1;
430 elsif T='1' then
431 state <=q0;
432 elsif D='1' and E='1' and T='0' then
433 state <= q10;
434
435 end if;
436
437 when q1 =>
438 if D='1' and T='0' then
439 state <= q2;
440 elsif D='0' and T='0' then
441 state <=q1;
442 elsif D='0' and T='1' then
443 state <=q0;
444 end if;
445
446 when q2 =>
447 state <=q3;
448
449 when q3 =>
450 if D='1' and T='0' then
451 state <= q4;
452 elsif D='0' and T='0' then
453 state <=q3;
454 elsif D='0' and T='1' then
455 state <=q0;

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456 end if;
457
458 when q4 =>
459 state <=q5;
460
461 when q5 =>
462 if D='1' and T='0' then
463 state <= q6;
464 elsif D='0' and T='0' then
465 state <=q5;
466 elsif D='0' and T='1' then
467 state <=q0;
468 end if;
469
470 when q6 =>
471 state <=q7;
472
473
474 when q7 =>
475 if T='0' then
476 state <= q7;
477 else
478 state <=q8;
479 end if;
480
481 when q8 =>
482 state <=q9;
483
484 when q9 =>
485 if T='0' then
486 state <= q9;
487 else
488 state <=q0;
489 end if;
490
491 when q10 =>
492 if D='1' and E='1' and T='0' then
493 state <= q11;
494 elsif D='1' and E='0' then
495 state <= q2;
496 elsif D='0' and T='0' then
497 state <=q10;
498 elsif T='1' then
499 state <=q0;
500 end if;
501
502 when q11 =>
503 state <= q12;
504
505 when q12 =>
506 if D='1' and E='1' then
507 state <= q13;
508 elsif D='1' and E='0' then
509 state <= q4;
510 elsif D='0' and T='0' then
511 state <=q12;
512 elsif T='1' then

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513 state <=q0;
514 end if;
515
516 when q13 =>
517 state <=q14;
518
519 when q14 =>
520 if D='1' and E='1' then
521 state <= q15;
522 elsif D='1' and E='0' then
523 state <= q6;
524 elsif D='0' and T='0' then
525 state <=q14;
526 elsif T='1' then
527 state <=q0;
528 end if;
529
530 when q15 =>
531 state <=q16;
532
533 when q16 =>
534 if T='0' then
535 state <= q16;
536 elsif T='1' then
537 state <= q17;
538 end if;
539
540 when q17 =>
541 state <=q18;
542
543
544 when q18 =>
545 if T='0' then
546 state <= q18;
547 elsif T='1' then
548 state <= q19;
549 end if;
550
551
552 when q19 =>
553 if A='0' then
554 state <= q19;
555 elsif A='1' then
556 state <= q20;
557 end if;
558
559
560 when q20 =>
561 if A='1' then
562 state <= q20;
563 elsif A='0' then
564 state <= q0;
565 end if;
566
567
568
569

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570 end case;
571 end if;
572
573 end process;
574
575 leds(7 downto 2)<="000000";
576
577 --FSM COntrolador
578 process(state)
579 begin
580
581 case state is
582 when q0 =>
583 m<="00";
584 C<='0';
585 I<='0';
586 leds(0)<='1';
587 leds(1)<='0';
588 when q1 =>
589 m<="01";
590 C<='1';
591 I<='0' ;
592 leds(0)<='0';
593 leds(1)<='0';
594 when q2 =>
595 m<="01";
596 C<='0';
597 I<='0';
598 leds(1)<='0';
599 leds(1)<='0';
600 when q3 =>
601 m<="10";
602 C<='1';
603 I<='0';
604 leds(0)<='0';
605 leds(1)<='0';
606 when q4 =>
607 m<="10";
608 C<='0';
609 I<='0';
610 leds(0)<='0';
611 leds(1)<='0';
612 when q5 =>
613 m<="11";
614 C<='1';
615 I<='0';
616 leds(0)<='0';
617 leds(1)<='0';
618 when q6 =>
619 m<="11";
620 C<='0';
621 I<='1';
622 leds(0)<='0';
623 leds(1)<='0';
624 when q7 =>
625 m<="11";
626 C<='1';

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627 I<='0';
628 leds(0)<='0';
629 leds(1)<='0';
630 when q8 =>
631 m<="11";
632 C<='0';
633 I<='1';
634 leds(0)<='0';
635 leds(1)<='0';
636 when q9 =>
637 m<="00";
638 C<='1';
639 I<='0';
640 leds(0)<='0';
641 leds(1)<='0';
642 when q10 =>
643 m<="01";
644 C<='1';
645 I<='0';
646 leds(0)<='0';
647 leds(1)<='0';
648 when q11 =>
649 m<="10";
650 C <='0';
651 I <='0';
652 leds(0)<='0';
653 leds(1)<='0';
654 when q12 =>
655 m<="10";
656 C<='1';
657 I<='0';
658 leds(0)<='0';
659 leds(1)<='0';
660 when q13 =>
661 m<="11";
662 C<='0';
663 I<='0';
664 leds(0)<='0';
665 leds(1)<='0';
666 when q14 =>
667 m<="11";
668 C<='1';
669 I<='0';
670 leds(0)<='0';
671 leds(1)<='0';
672 when q15 =>
673 m<="11";
674 C<='0';
675 I<='1';
676 leds(0)<='0';
677 leds(1)<='0';
678 when q16 =>
679 m<="11";
680 C<='1';
681 I<='1';
682 leds(0)<='0';
683 leds(1)<='0';

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684 when q17 =>
685 m<="11";
686 C<='0';
687 I<='1';
688 leds(0)<='0';
689 leds(1)<='0';
690
691 when q18 =>
692 m<="11";
693 C<='1';
694 I<='1';
695 leds(0)<='0';
696 leds(1)<='1';
697
698 when q19 =>
699 m<="11";
700 C<='1';
701 I<='1';
702 leds(0)<='0';
703 leds(1)<='0';
704
705 when q20 =>
706 m<="11";
707 C<='1';
708 I<='1';
709 leds(0)<='0';
710 leds(1)<='0';
711
712 end case;
713
714 end process;
715
716
717
718
719
720
721
722
723 end Behavioral;
724
725

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