Combinational Circuits

y A combinational circuit consists of logic gates whose outputs

at any time are determined directly from the present combinations of inputs without regards of previous inputs.

y For n input variable, there are 2n combinations. y For each possible input combination there is one and only

one possible output.

Procedures
y Two important procedure for combinational circuit y Design:
y Given the specifications, build it

y Analysis:
y Given circuit schematic, explain its behavior

Design Procedure
y Problem is specified y From Specifications, determine the required number of y y y y

inputs and outputs Assign a variable to each input and output Derive a truth table that defines the required relationship between inputs and outputs Perform logic minimization Draw the logic diagram

ADDERS
y Adder performs the addition function of the given inputs
y y y y

0+0 =0 0+1=1 1+0=1 1+1=10

y Half adder is the combinational circuit that performs addition of

two bits. y Full adder is the combinational circuit of three bits (two significant bits and a previous carry). y Two half adders can be employed to implement a full adder

y From the half adders specification, we find that this circuit

needs two binary inputs and two binary outputs. y We arbitrarily assign symbols x and y to the two inputs and S to the sum and C for the carry. y We can develop its truth table

Design procedure of half adder

y The boolean functions for S (sum) and C(carry) can be

obtained directly as sum of minterms ( which are 1 in both cases)

y S=xy+xy y C=xy

y They are simplified too. y We can draw logic diagram for this implementation.

Implementation of Half adder

Implementation of Half adder

y There can be other various implementation of half adder y We can show the implementation in product of sums
y S=(x+y)(x+y) y C=xy

Implementation of Half adder

y We also note that S is an exclusive OR function of x and y y S=xy+xy y If we take complement of it we can obtain an equivalence y y y y

function of x and y S=xy+xy But C=xy So S = C+xy S= (C+xy)

Implementation of Half adder

Implementation of Half adder

y We can represent S and C both as product of sums

Implementation of Half adder

y Lastly we can represent half adder with an exclusive OR (for

S) and a AND gate (for C)

Design Procedure for Full Adder

y From the specification of full adder, we can find that there

are three input variables and two output variables y We give names to input variable as x, y and z y The x and y denotes the significant bits to be added and z denotes carry from the previous lower significant position. y We also give name to outputs as S (least significant bit of sum) and C(carry)

y Truth table
X+y+z

y S= xyz+ xyz+xyz+ xyz (z,y,x empty) y C=xyz+ xyz+ xyz+ xyz

(X,Y,Z)

y Simplifying

y Representing full adder ( sum of products form)

y Can you represent it as product of sums ??

y A full adder can be represented by two cascaded half adders

SUBTRACTORS
y Subtraction of two binary numbers may be accomplished by taking y y y y

the complement of the subtrahend and adding it to the minuend. Half Subtractor Full Subtractor In case of x-y, two situations When x>=y
y 0-0=0 y 1-0=1 y 1-1=0

y When x<y
y 0-1 , it is necessary to borrow 1 from higher stage

Half Subtractor (x-y)

y A half subtractor is a combinational circuit that subtracts two y y y y

bits and produces their differences It also has an output to specify if a 1 has been borrowed. Designate minuend bit as x and the subtrahend bit by y Designate the difference output as D Designate the other output as B (borrow), generates the binary signal that informs the next stage that 1 has been borrowed

y Truth table

y B is 0 for x>=y y B is 1 for x=0 and y=1 y Expressing Boolean functions as B and D

y It is important to note that logic for D is exactly the same as

S in half adder

y Representing half subtractor

Full Subtractor (x-y)-z

y Full subtractor is a combinational circuit that performs

subtraction of three bits y Designate inputs as x, y and z y Designate outputs as B and D

y Truth table

Design procedure of code conversion example

Analysis Procedure of Combination Circuit

Analysis Procedure
y Analysis process is reverse of the design process y This starts with the logical diagram and culminates with a set

of Boolean functions, a truth table or verbal explanation of circuit operation. y For the analysis of combinational circuit, make sure that it does not contain any feedback path or memory elements.
y A feedback path is a connection from the output of one gate to

the input of a second gate that forms part of the input to the first gate.

Example

The circuit consists of three variables A,B ,C and two binary outputs F1 and F2 The output of gates that are function of input variables T1, T2 and F2

y Boolean function of F2, T1 and T2

y Next consider the output of gates that are function of already

defined symbols

y Substitute the value of T3 and T2 to obtain F1

Derivation of truth table

y We can also derive the truth table from the logical circuit and

the procedure is :

Multilevel NAND Circuits

NAND Gate is also known as Universal Gate, because any digital system can be implemented with it.

Boolean Function Implementation using NAND gates

From the given algebraic expression, draw the logical diagram with AND, OR and NOT gates. Assume both normal and complement inputs are available 2. Draw second logic diagram with equivalent NAND gates 3. Remove any two cascaded inverters from the diagram, since double inversion does not perform a logic function. Remove inverters connected to single external inputs and complement the corresponding variable.
1.

Example
y Obtain NAND gate implementation of the

F=A(B+CD)+BC
C D B A B C F

Substituting equivalent NAND gates

C D B AND OR

AND A AND B C

OR

Removing cascaded NAND gates

C D B

B C

Example
y Develop NAND implementation of (A+B)(CD+E)

Analysis Procedure
y Develop Boolean function of the given circuit
C D T1

T3 B T4 A F B C T2

y T1=(CD)=C+D y T2=(BC)=B+C y T3=(BT1)=(BC + BD)

=(B+C)(B+D)=B+CD y T4=(AT3)=[A(B+CD)] y F=(T2T4)={ (BC)[A(B+CD)]} =BC+A(B+CD)

y Draw the truth table of the given circuit

C D T1

T3 B T4 A F T2 B C

Block Transformation
y How can you convert a NAND logic diagram to its

equivalent AND-OR logic diagram y Substitute the NAND gate with invert OR gate y Cancel the circles that appear on one line

Multilevel NOR Gates

NOR gate universal gate

Boolean Function Implementation using NOR gates

From the given algebraic expression, draw the logical diagram with AND, OR and NOT gates. Assume both normal and complement inputs are available 2. Draw second logic diagram with equivalent NOR gates 3. Remove any two cascaded inverters from the diagram, since double inversion does not perform a logic function. Remove inverters connected to single external inputs and complement the corresponding variable.
1.

Example
y Obtain NOR gate implementation of the

F=A(B+CD)+BC
C D B A B C F

Analysis Procedure

Block Diagram toTransformation Convert the following NOR circuit diagram

AND OR equivalent diagram