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INTRODUCTION
1218 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 34, NO. 4 OCTOBER 1998
advantage of the DSMC scheme is its insensitivity _ _CONVERTER
,DC-AC _________________------------.---..--
to parameter variations and load disturbances, which PWM INVERTER LCFILTER LOAD
L r , i. i. :
leads to invariant steady-state response in the ideal
case, while its disadvantages are that it is not easy to
find an appropriate sliding surface and its performance
will be degraded with a limited sampling rate.
With the availability of 16-bit high-performance
DSP chips, most of its instructions can be
I__._______..____.__.-.-..----.--
a f-,to)
-__---
t;.iti
accomplished in one instruction cycle and complicated
control algorithms can be executed with fast speed.
This work describes the design and implementation 320614 DSP-Based DC-AC ConverterController
TZOU & JUNG: FULL CONTROL OF A PWM DC-AC CONVERTER FOR AC VOLTAGE REGULATION 1219
The transfer function of the inverter output voltage vu
to the filter output voltage vo is
-
VOb) -
G,(s) = - b,s+b,
(3)
VJS) a2s2 + als + a0
where b, = rcRC, bo = R, a2 = ( R + rc)LC, a , = L +
(rL + r,)RC + rLrcC, and a. = rL + R. The open-loop
output impedance is defined as
-
Z0(S) = --
z0(s) LCS+ ~ (r, + rc)Cs + 1 ‘
(4)
-1SdSl I
id It can be observed from (3) that the capacitor
(b)
ESR rc will introduce a zero located at z, = --I/r,C.
Fig. 2. Modeling of a dc-ac converter. (a) Equivalent circuit. This left-half plane zero compared with the natural
(b) Block diagram representation. resonant pole of the LC filter located at po = - 1 / m
has a ratio of
improvement in the performance of microprocessors (5)
and digital control integrated circuits (ICs) [ 151.
With the recently developed high-performance DSP, The capacitor ESR rc is usually very small and this
realization of digital controllers with higher sampling zero is high above the resonant frequency of the LC
rate becomes possible and this makes the sampling
tank. If the ESRs of the LC filter are small enough
frequency gradually approach the switching frequency and can be neglected, (1) and (2) can be simplified as
of a digital-controlled power converting system.
The dynamics of a dc-ac converter is mainly
determined by the LC filter and connected load. The
complexity in the modeling and control of a dc-ac
converter used for UPS applications comes from the
:[=I:[ C
-
I&)
second-order system with state variables vc and i,
output load voltage vo and input voltage vu, which The modeling of a digital-controlled PWM dc-ac
takes three values 0.5&,, 0.5&,, or zero. Consider converter can be represented by a block diagram as
the inductor equivalent series resistance (ESR) rL shown in Fig. 2(b). As shown in Fig. 2(b), there is a
and capacitor ESR rc, the state equation and output discrete duty ratio d ( k ) applied to a PWM modulator.
equation become The d(k) is determined at every sampling interval
To from a digital controller. The PWM modulator
generates the PWM gating signals according to a
modulation strategy. A variety of PWM methods
have been developed to reduce both the switching
losses and current ripples [16]. The digital unipolar
PWM method as shown in Fig. 3 has characteristics
1 of minimum current ripple and simple switching
+[;]vu mechanism and is adopted here for the generation of
the PWM switching patterns.
1220 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 34, NO. 4 OCTOBER 1998
n
(b)
Fig. 3. Unipolar pulsewidth modulation of a full-bridge converter.
(a) Circuit diagram. (b) Timing diagram.
When the current loop gain K2 approaches to Fig. 5. Decoupling effect of analog current control, and root loci
infinity, one of its poles will approach to -1/RC, of s2RLC + sL + R + K,(sRC + 1 + K , R ) = 0.
and it will be canceled out by the zero of (1l),
another pole will approach to -K,/L and becomes the will be limited by the filter inductor and permissible
dominant pole. From the above analysis, the current current-loop gain.
loop has the effect of decoupling the resonant poles By adding a current loop to control the inductor
produced by the LC filter and the dominant pole current as shown in Fig. 4(c), the output reflected
TZOU & JUNG: FULL CONTROL OF A PWM DC-AC CONVERTER FOR AC VOLTAGE REGULATION 1221
(15), then (12) can be approximated by
"O t
i, = iE SL + (Y,
K2 + K2)'
f = 1 K2
--
The current-loop gain K2 has a unit of ohm. If v, 2nL'
is viewed as a disturbance, it can be seen from (12) The inclusion of an inner CLC in the closed-loop
that a step change of Avo has an influence on i, with regulation of a PWM dc-ac converter has the
magnitude of Avo/(rL+ K2) as shown in Fig. 6. The following advantages:
usual condition is rL << K2, therefore, the influence of
Avo on i, is Av0/K2.If this steady-state current error 1) eliminate the influences of the inductor
should be less than p,iE with 0 _< pi I 1, then parameter variation,
2) has the effect of decoupling the LC-filter
resonant poles and making the design of the LC-filter
9
Ki
< piiL (13)
easier,
which means K2 > Avo/piiE. If we define Avo = pV&, 3) inherent current limiting capability,
with 0 5 pv 5 1, then the current loop gain K2 should 4) the minor CLC and the major voltage-loop
satisfy the following requirement controller (VLC) can be designed and implemented
separately.
Fig. 7. Block diagram of multiloop digital control scheme for the voltage regulation fo PWM ddac converter for ac voltage generation.
1222 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 34, NO. 4 OCTOBER 1998
A. Digital Current-Loop Controller where
e(k) = v,(k) - v,(k). (28)
If the sampling period of the CLC is much smaller
than the electrical time constant of the filter inductor, The controller parameters of (27) are determined
Le., To << L/rL, a linear approximation of the inductor by using the least-squares error (LSE) fitting of
current can be used to derive the dead beat control a specified time response based on an identified
algorithm for the inductor current control. The current-controlled plant model. We can measure a time
proposed discrete current control algorithm is series of {iE(k),v,(k)} when the PWM dc-ac converter
is current regulated, connected with a rated resistive
Ai,r(k) = iL(k) - iL(k) (20) load, and closed-loop controlled by employing a
L simple proportional gain in the VLC to ensure its
v,(k) AiL(k)- + vo(k) + i,r(k)rL (21) stability.
TD With the measured time series of {i;(k),vo(k)}, the
4 k ) = v,(k)/V,,(k) (22) plant model of the current-regulated dc-ac converter
from the current command iL(k) to the output voltage
where v&) is the feedback output voltage and V,,(k) vo(k) under closed-loop control can be identified,
is the dc link voltage. which is denoted as
The maximum current incremental during one
sampling interval can be expressed as vo(k) = b,vo(k - 1) + liOiL(k)+ li,iL(k - 1) + li,iE(k - 2).
(29)
The model parameters of (29) can be determined
This current incremental reaches its maximum when by using the recursive LSE system identification
the output voltage and current are both zero, and technique [ 181.
reaches its minimum when both are maximum. If we With a specified input series of {v,(k)}, we can
define define a cost function
N
n~"' = b c - vo(maw) - k(max)'L (24)
as the minimum effective control voltage and select i=l
the sampling interval of the CLC as where N is the number of points for the time-response
curve fitting. The controller parameters { b ,,ao,al}
of (27) can be determined by minimizing the cost
function defined by (30) [19].
then the maximum current incremental in the worst
condition is
C. Digital Feedforward Controller
TZOU & JUNG: FULL CONTROL OF A PWM DC-AC CONVERTER FOR AC VOLTAGE REGULATION 1223
Fig. 8. Output voltage and current waveforms under rated step resistive load change. (a) Simulation. (b) Experimental results.
a lower loop gain to keep stability and prevent from close to the simulation results. Experimental results
limit-cycle ringing. The FC proposed here is designed show the output voltage transient due to a step load
empirically. It is hard to prove the stability of the change can be reduced to 10% within 0.6 ms.
converter system analytically. In this paper, the Fig. 9 shows the experimental steady-state
stability is checked experimentally by applying the responses of output voltage and current waveforms.
worst loading conditions. The corresponding power spectrum of each voltage
waveform are also depicted in the same figure.
The THD of voltage waveform was measured by a
IV. IMPLEMENTATION A N D EXPERIMENTAL RESULTS dynamic signal analyzer (HP3562A). Since only the
To verify the proposed control scheme, a 1 kW harmonics of 60 Hz are concerned here, a frequency
PWM dc-ac converter using the IGBT GT50J101 span of 5 kHz was set during measurement. The
from the Toshiba Co. [20] was constructed. harmonics of sampling and switching frequencies
A single-chip DSP from Texas Instruments were ignored in our application due to their little
(TMS320C14) was chosen to implement the proposed relevance to the quality of output voltage. The
digital control scheme. The TMS320C14 is essentially definition of THD is defined as
a 16-bit microcontroller with DSP architecture; most
of its instructions can be executed in one instruction (33)
cycle of 160 ns. This single-chip DSP includes a
16-bit digital 110, 4 timers, 6 channels of PWM, 4 where vi represents the ith harmonics inside the
capture inputs, a serial port with UART mode, and 15 measured frequency span. The crest factor is defined
interrupts. With its high operation speed and on-chip as the ratio of the peak value to the rms value of a
UOs, this single-chip DSP is a good choice for the periodic waveform. For UPS applications, the output
control of power converters and motor drives. voltage is required to have a THD below 5% under
The sampling frequency of the digital CLC is rated rectifier load with a current crest factor of 3. The
set at 15.36 kHz, therefore there are 256 samples THD in Fig. 9(c) is -30 dB which is about 3.16%.
in one period of a 60 Hz sinusoidal waveform. The These results show that the proposed digital control
sampling frequency of the digital VLC and FC is set scheme can also satisfy the required performance
at 7.68 kHz. The switching frequency of the PWM specifications which conventionally use analog control
power stage should be an integral multiple of the technique.
sampling frequency to reduce sideband harmonics;
at the same time, it is also easier for software
V. CONCLUSION
and hardware design. In the designed system, the
switching frequency of the PWM inverter is set at In this paper, a single-chip DSP-based
30.72 kHz. (TMS320C 14) fully digitally controlled PWM
Fig. 8 shows the simulation and experimental dc-to-ac converter has been implemented to verify
results of the output voltage and current waveforms the proposed multiloop digital control scheme. The
under a step load change from no load to rated output voltage error for a step-rated load change can
resistive load. The simulation of the PWM dc-ac be reduced below 10% within 5 sampling intervals
converter with digital control algorithm is carried out when operating at 1lOV, 15A, and 60 Hz. THD below
by using the EMTP circuit simulation package [17]. 5% of a rated rectifier load at crest factor of 3 can be
It can be found that the experimental results are very achieved. The constructed DSP-based PWM dc-to-ac
1224 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 34, NO. 4 OCTOBER 1998
d0
200, 1 ria I I
HZ
(cl) (c2)
Fig. 9. Experimental steady-state output voltage and current waveforms and output voltage spectrum under (a) no-load, (b) rated
resistive load, and (c) rated rectifier load with crest factor of 3.
converter system can achieve fast dynamic response [3] Kemick, A., Stechschulte, D. L., and Shireman, D. W.
and with low THD for rectifier-type loads. (1977)
Static inverter with synchronous output waveform
synthesized by time-optimal response feedback.
REFERENCES IEEE Transactions on Industrial Electronics and Control
Instrumentation, IECI-24, 4 (1977), 197-305.
[l] Patel, H. S., and Hoft, R. G. (1973)
Generalized techniques of harmonic elimination and Sekino, Y., Shibata, M., and Hotaka, N. (1983)
[4]
voltage control in thyristor inverters-Part I: Harmonic Inverter output voltage waveform closed-loop control
elimination, Part 11: Voltage control techniques. technique.
IEEE Transactions on Industry Applications, IA-9 (1973), In Proceedings of INTELEC Tokyo, Oct. 1983, 205-212.
310-317.
[2] Pitel, L. J., Talukdar, S. N., and Wood, P. (1980) [5] Kawamura, A,, and Hoft, R. (1984)
Characterization of programmed-waveform pulsewidth Instantaneous feedback controlled PWM inverter with
modulation. adaptive hysteresis.
IEEE Transactions on Industry Applications, IA-16 IEEE Transactions on Industry Applications, IA-20, 4
(Sept.-Oct. 1980), 707-715. (1984), 769-775.
TZOU & JUNG: FULL CONTROL OF A PWM DC-AC CONVERTER FOR AC VOLTAGE REGULATION 1225
[6] Bose, B. K. (1990) Jung, S. L., and Tzou, Y. Y. (1993)
An adaptive hysteresis-band current control technique of Sliding mode control of a closed-loop regulated PWM
a voltage-fed PWM inverter for machine drive system. inverter under large load variations.
IEEE Transactions on Industrial Electronics, 37, 5 (Oct. In IEEE Power Electronics Specialists’ Conference Record,
1990), 402-408. June 1993.
[7] Bose, B. K. (Ed.) (1987) TMS32OCIx User’s Guide (1991)
Microcomputer Control of Power Electronics and Drives. Texas Instruments, July 1991.
. New York: IEEE Press, 1987. Kawamura, A. (1987)
[8] Dote, Y. (1990) Sampled-data model of power electronics system driven
Servo Motor and Motion Control Using Digital Signal by a PWM inverter.
Processors. In Conference Record of JIEE (in Japanese), 1987,
Englewood Cliffs, NJ: Prentice-Hall, 1990. 636-637.
[9] Cha, H.-J., et al. (1990) Le-Huy, H. (1994)
Real-time digital control of PWM inverter with PI Microprocessors and digital IC’s for motion control.
compensator for uninterruptible power supply. Proceedings of the IEEE, 82, 8 (Aug. 1994), 1140-1163.
Int. Conj I d . Electronics Contl: a d Inst., 2 (1990), Tal, J. (1976)
1125-1128. Design and analysis of pulsewidth-modulated amplifiers
[lo] Kawabata, T., Shikano, Y., and Higashino, S. (1986) for dc servo system.
Chargeless UPS using multi-functional BIMOS IEEE Transactions on Industrial Electronics and Control
inverter-sinusoidal voltage waveform inverter with Instrumentation,IECI-23, 1 (Feb. 1976), 47-55.
current minor loop. The EMTP User’s Guide (1993).
In Proceedings of the IEEE IAS Annual Meeting, 1986, Ljung, L. (1987)
513-520. System Identification: Theoryfor the User.
[Ill Hua, C., and Hoft, R. G. (1992) Englewood Cliffs, NJ: Prentice-Hall, 1987.
High performance deadbeat controlled PWM inverter The Optimization Toolboxfor Use with PC-MATLAB (1993)
using a current source compensator for nonlinear loads. The Mathworks, Inc., 1993.
In IEEE Power Electronics Specialists’ Conference Record, Catalog of the GTR Module (IGBT) (1992)
1992, 443450. Toshiba, 1992.
Ying-Yu Tzou (S’81-M’88) was born in Taiwan, R.O.C., on February 13, 1956.
He received the B.S. and M.S. degree in control engineering from the National
Chiao Tung University, Hsinchu, Taiwan, and the Ph.D. degree in electrical
engineering from the Institute of Electronics Engineering of National Chiao Tung
University in 1978, 1983, and 1987, respectively.
During 1980-1981 he was with the Electronic Research and Service
Organization (ERSO) of Industry Technology Research Institute (ITRI) as a
design engineer in the control system department. During 1983-1986 he was
with Microtek Automation, Inc., as a project manager for the development of
a computer numerical controller (CNC) for machine tools. He is currently a
Professor of the Department of Electrical and Control Engineering of National
Chiao Tung University, and also serves as an industrial consultant for many
local power electronics and automation companies. He was the Director of the
Institute of Control Engineering during 1992-1994. His special interests now are
sensorless ac drives, intelligent UPS, FPGA-based control ICs for motor drives
and power converters, and DSP applications in power electronics and motion
control.
1226 IEEE TRANSACTIONS ON AEROSPACE AND ELECTRONIC SYSTEMS VOL. 34, NO. 4 OCTOBER 1998