MULTIPLEXER:

module mux(y,a,s);
input [7:0]a;
input [2:0]s;
output y;
wire [2:0]sn;
wire [7:0]w;
not(sn[0],s[0]);
not(sn[1],s[1]);
not(sn[2],s[2]);
and(w[0],a[0],sn[2],sn[1],sn[0]);
and(w[1],a[1],sn[2],sn[1],s[0]);
and(w[2],a[2],sn[2],s[1],sn[0]);
and(w[3],a[3],sn[2],s[1],s[0]);
and(w[4],a[4],s[2],sn[1],sn[0]);
and(w[5],a[5],s[2],sn[1],s[0]);
and(w[6],a[6],s[2],s[1],sn[0]);
and(w[7],a[7],s[2],s[1],s[0]);
or(y,w[7],w[6],w[5],w[4],w[3],w[2],w[1],w[0]);
endmodule
Demultiplexer:
module demux(d,s,i);
input i;
input [2:0]s;
output [7:0]d;
wire w1,w2,w3;
not(w1,s[0]);
not(w2,s[1]);
not(w3,s[2]);
and(d[0],i,w3,w2,w1);
and(d[1],i,w3,w2,s[0]);
and(d[2],i,w3,s[1],w1);
and(d[3],i,w3,s[1],s[0]);
and(d[4],i,s[2],w2,w1);
and(d[5],i,s[2],w2,s[0]);
and(d[6],i,s[2],s[1],w1);
and(d[7],i,s[2],s[1],s[0]);
endmodule

module bin-up-down(a,up,down);
input up,down;
output [3:0]a;
wire w1,w2,w3,w4,w5,w6;

wire [3:0]an;
not(w1,up);
and(w2,w1,down);
or(w3,up,w2);
t-flipflop(a[0],clk,w3);
an[0]=~a[0];
and(w4,w2,an[0]);
and(w5,up,a[0]);
or(w6,w4,w5);
t-flipflop(a[1],clk,w6);
an[1]=~a[1];
and(w7,w4,an[1]);
and(w8,w5,a[1]);
or(w9,w8,w7);
t-flipflop(a[2],clk,w9);
an[2]=~a[2];
and(w10,w7,an[2]);
and(w11,w8,a[2]);
or(w12,w11,w10);
t-flipflop(a[3],clk,w9);