TITLE: JK FLIP-FLOP

INSTRUCTIONAL AIMS:
The trainee must be able to:
1. Verify the JK flip-flop truth table.
2. Understand the concept of edge triggering versus master-slave triggering.

TOOLS, EQUIPMENTS AND MATERIALS:

1. Breadboard
2. Power supply
3. IC 7476
4. Led
5. Jumper wires

DRAWING, DATA, TABLE:

Refer to pages with the procedure instructions.

GENERAL INSTRUCTION:
Trainees are going to examine the JK flip-flop, verify its truth table and understand what
is a T flip-flop.

PROCEDURE:

JK flip-flop

Note:
Circle denotes data transferred
to output on negative clock transition.

Note:
П indicates a master slave triggering
condition.
The data switch should be set LOW,
HIGH,
LOW.

a. IC 7476 master slave triggered Dual JK flip-flop was installed in the Logic Lab
Breadboard
b. The circuit was constructed as shown in figure above.
c. Data was set up in the JK truth table. Data switch SW3 was set П. The output
must be record indication of L1.
d. The output toggles was observe every time the data switch produces a HIGH to
LOW transition.
 e. The output Q waveform was drawn with their inputs waveform combination.

JK FLIP-FLOP TRUTH TABLE

INPUTS OUTPUT
STATEMENT
PRE CLR J=SW2 K=SW1 CLK=SW3 Q=L1
0 0 0 0 П 1 PROHIBITED
0 0 0 1 П 1 PROHIBITED
0 1 1 0 П 1 SET
0 1 1 1 П 1 SET
1 0 0 0 П 0 RESET
1 0 1 0 П 0 RESET
1 1 0 0 П 0 HOLD
1 1 0 1 П 0 RESET
1 1 1 0 П 1 SET
1 1 1 1 П 1 HOLD
1 1 1 1 П 0 SET
1 1 1 1 П 1 TOGGLE

PROCEDURES:

Therefore we can observe that when J=HIGH, K=HIGH the output toggle. This circuit
condition called a T flip-flop and can be shown symbolically as:

f. Set data switch SW1 and SW2 to HIGH. The output indication changes was
plotted at HIGH to LOW transition point of the clock shown in the diagram
below:

SW3 CLOCK
OR T INPUT

HIGH
OUTPUT INDICATION
LOW

Therefore, we can observe from the diagram above that the output changes state ½ as fast
as the clock input. Thus the T flip-flop can be used to divide any input frequency by 1/F
PROCEDURE:

JK flip-flop

a. A 7400 NAND Gate was installed into Logic Lab breadboard.

b. The circuit was constructed as shown in figure above.
c. Data was set up as shown in the JK truth table. The L1 indicator was recorded.
d. The JK output truth table was compared with the standard JK output truth table.

JK FLIP-FLOP TRUTH TABLE

INPUTS OUTPUT
STATEMENT
J (SW2) K (SW1) Q = L1 Q’ = L2
0 0 0 0 HOLD
0 1 0 1 RESET
1 0 1 0 SET
1 1 1 0 TOGGLE
1 1 TOGGLE
0 0 0 0 HOLD
0 1 1 0 RESET
1 0 0 1 SET
1 1 TOGGLE
1 1 TOGGLE
PROCEDURE:

Master Slave JK flip-flop

a. IC 7408 2 – inputs NAND gate, 3-input NAND gate 7410 and led was installed
into the logic lab breadboard.
b. The circuit was constructed such figure above.
c. The data was set up as shown in the Master Slave JK truth table. The L1 indicator
was recorded.

Master Slave JK FLIP-FLOP TRUTH TABLE

INPUTS OUTPUT STATEMENT
J=SW1 K=SW2 CLK=SW3 Qm Qs
0 0 П 0 0 (delay) HOLD
0 1 П 0 0 (delay) RESET
1 0 П 1 1 SET
1 1 П 1 0 TOGGLE
1 1 П 0 1 TOGGLE
0 0 П 0 0 HOLD
0 1 П 0 0 RESET
1 0 П 1 1 (delay) SET
1 1 П 0 0 (delay) TOGGLE
1 1 П 1 1 (delay) TOGGLE
1 1 1Hz 1 1 (delay) TOGGLE
1 1 1Hz 0 0 (delay) TOGGLE
1 1 1Hz 1 1 (delay) TOGGLE
 1 1 1Hz 0 0 (delay) TOGGLE

CONCLUSION:
Berdasarkan eksperimen yang telah dijalankan, didapati bahawa apabila J=1, K=1, ia
akan berfungsi sebagai Flip – Flop T. Bagi pengujian Flip – Flop JK Master Slave,
Keluaran slave (Qs) akan lengah (Delay) selepas keluaran master (Qm). Operasinya
adalah sama seperti Flip – Flop JK.

Question

1. If the following three sets J=HIGH, K=LOW, CLK=П ; J=LOW, K=HIGH, CLK=П
; were applied to a 7476 JK flip-flop, the final output state would be;

C. Q = toggle

2. In what state must the preset and clear inputs be held to allow normal 7476
operation:

B. HIGH

3. Does JK flip-flop have any invalid input conditions?

No

4. What are the synchronous inputs of the JK flip-flop?

Set and Reset

5. How to make the Q output of JK flip-flop always changes upon the occurrence of
the active transition?
Set J = HIGH and K = HIGH